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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann: "Driver updates for ARM SoCs, these contain various things that touch the drivers/ directory but got merged through arm-soc for practical reasons. For the most part, this is now related to power management controllers, which have not yet been abstracted into a separate subsystem, and typically require some code in drivers/soc or arch/arm to control the power domains. Another large chunk here is a rework of the NVIDIA Tegra USB3.0 support, which was surprisingly tricky and took a long time to get done. Finally, reset controller handling as always gets merged through here as well" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (97 commits) arm-ccn: Enable building as module soc/tegra: pmc: Add generic PM domain support usb: xhci: tegra: Add Tegra210 support usb: xhci: Add NVIDIA Tegra XUSB controller driver dt-bindings: usb: xhci-tegra: Add Tegra210 XUSB controller support dt-bindings: usb: Add NVIDIA Tegra XUSB controller binding PCI: tegra: Support per-lane PHYs dt-bindings: pci: tegra: Update for per-lane PHYs phy: tegra: Add Tegra210 support phy: Add Tegra XUSB pad controller support dt-bindings: phy: tegra-xusb-padctl: Add Tegra210 support dt-bindings: phy: Add NVIDIA Tegra XUSB pad controller binding phy: core: Allow children node to be overridden clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs drivers: firmware: psci: make two helper functions inline soc: renesas: rcar-sysc: Add support for R-Car H3 power areas soc: renesas: rcar-sysc: Add support for R-Car E2 power areas soc: renesas: rcar-sysc: Add support for R-Car M2-N power areas soc: renesas: rcar-sysc: Add support for R-Car M2-W power areas soc: renesas: rcar-sysc: Add support for R-Car H2 power areas ...
This commit is contained in:
Linus Torvalds
@@ -1,16 +1,20 @@
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NVIDIA Tegra Power Management Controller (PMC)
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== Power Management Controller Node ==
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The PMC block interacts with an external Power Management Unit. The PMC
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mostly controls the entry and exit of the system from different sleep
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modes. It provides power-gating controllers for SoC and CPU power-islands.
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Required properties:
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- name : Should be pmc
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- compatible : For Tegra20, must contain "nvidia,tegra20-pmc". For Tegra30,
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must contain "nvidia,tegra30-pmc". For Tegra114, must contain
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"nvidia,tegra114-pmc". For Tegra124, must contain "nvidia,tegra124-pmc".
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Otherwise, must contain "nvidia,<chip>-pmc", plus at least one of the
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above, where <chip> is tegra132.
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- compatible : Should contain one of the following:
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For Tegra20 must contain "nvidia,tegra20-pmc".
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For Tegra30 must contain "nvidia,tegra30-pmc".
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For Tegra114 must contain "nvidia,tegra114-pmc"
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For Tegra124 must contain "nvidia,tegra124-pmc"
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For Tegra132 must contain "nvidia,tegra124-pmc"
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For Tegra210 must contain "nvidia,tegra210-pmc"
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- reg : Offset and length of the register set for the device
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- clocks : Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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@@ -68,6 +72,11 @@ Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'
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Defaults to 0. Valid values are described in section 12.5.2
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"Pinmux Support" of the Tegra4 Technical Reference Manual.
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Optional nodes:
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- powergates : This node contains a hierarchy of power domain nodes, which
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should match the powergates on the Tegra SoC. See "Powergate
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Nodes" below.
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Example:
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/ SoC dts including file
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@@ -113,3 +122,76 @@ pmc@7000f400 {
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};
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...
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};
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== Powergate Nodes ==
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Each of the powergate nodes represents a power-domain on the Tegra SoC
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that can be power-gated by the Tegra PMC. The name of the powergate node
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should be one of the below. Note that not every powergate is applicable
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to all Tegra devices and the following list shows which powergates are
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applicable to which devices. Please refer to the Tegra TRM for more
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details on the various powergates.
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Name Description Devices Applicable
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3d 3D Graphics Tegra20/114/124/210
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3d0 3D Graphics 0 Tegra30
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3d1 3D Graphics 1 Tegra30
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aud Audio Tegra210
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dfd Debug Tegra210
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dis Display A Tegra114/124/210
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disb Display B Tegra114/124/210
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heg 2D Graphics Tegra30/114/124/210
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iram Internal RAM Tegra124/210
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mpe MPEG Encode All
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nvdec NVIDIA Video Decode Engine Tegra210
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nvjpg NVIDIA JPEG Engine Tegra210
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pcie PCIE Tegra20/30/124/210
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sata SATA Tegra30/124/210
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sor Display interfaces Tegra124/210
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ve2 Video Encode Engine 2 Tegra210
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venc Video Encode Engine All
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vdec Video Decode Engine Tegra20/30/114/124
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vic Video Imaging Compositor Tegra124/210
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xusba USB Partition A Tegra114/124/210
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xusbb USB Partition B Tegra114/124/210
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xusbc USB Partition C Tegra114/124/210
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Required properties:
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- clocks: Must contain an entry for each clock required by the PMC for
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controlling a power-gate. See ../clocks/clock-bindings.txt for details.
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- resets: Must contain an entry for each reset required by the PMC for
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controlling a power-gate. See ../reset/reset.txt for details.
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- #power-domain-cells: Must be 0.
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Example:
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pmc: pmc@7000e400 {
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compatible = "nvidia,tegra210-pmc";
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reg = <0x0 0x7000e400 0x0 0x400>;
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clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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powergates {
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pd_audio: aud {
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clocks = <&tegra_car TEGRA210_CLK_APE>,
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<&tegra_car TEGRA210_CLK_APB2APE>;
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resets = <&tegra_car 198>;
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#power-domain-cells = <0>;
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};
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};
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};
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== Powergate Clients ==
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Hardware blocks belonging to a power domain should contain a "power-domains"
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property that is a phandle pointing to the corresponding powergate node.
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Example:
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adma: adma@702e2000 {
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...
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power-domains = <&pd_audio>;
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...
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};
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@@ -0,0 +1,79 @@
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SAMSUNG Exynos SoCs SROM Controller driver.
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Required properties:
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- compatible : Should contain "samsung,exynos4210-srom".
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- reg: offset and length of the register set
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Optional properties:
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The SROM controller can be used to attach external peripherals. In this case
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extra properties, describing the bus behind it, should be specified as below:
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- #address-cells: Must be set to 2 to allow device address translation.
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Address is specified as (bank#, offset).
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- #size-cells: Must be set to 1 to allow device size passing
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- ranges: Must be set up to reflect the memory layout with four integer values
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per bank:
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<bank-number> 0 <parent address of bank> <size>
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Sub-nodes:
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The actual device nodes should be added as subnodes to the SROMc node. These
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subnodes, in addition to regular device specification, should contain the following
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properties, describing configuration of the relevant SROM bank:
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Required properties:
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- reg: bank number, base address (relative to start of the bank) and size of
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the memory mapped for the device. Note that base address will be
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typically 0 as this is the start of the bank.
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- samsung,srom-timing : array of 6 integers, specifying bank timings in the
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following order: Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
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Each value is specified in cycles and has the following
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meaning and valid range:
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Tacp : Page mode access cycle at Page mode (0 - 15)
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Tcah : Address holding time after CSn (0 - 15)
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Tcoh : Chip selection hold on OEn (0 - 15)
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Tacc : Access cycle (0 - 31, the actual time is N + 1)
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Tcos : Chip selection set-up before OEn (0 - 15)
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Tacs : Address set-up before CSn (0 - 15)
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Optional properties:
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- reg-io-width : data width in bytes (1 or 2). If omitted, default of 1 is used.
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- samsung,srom-page-mode : if page mode is set, 4 data page mode will be configured,
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else normal (1 data) page mode will be set.
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Example: basic definition, no banks are configured
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memory-controller@12570000 {
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compatible = "samsung,exynos4210-srom";
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reg = <0x12570000 0x14>;
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};
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Example: SROMc with SMSC911x ethernet chip on bank 3
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memory-controller@12570000 {
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x04000000 0x20000 // Bank0
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1 0 0x05000000 0x20000 // Bank1
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2 0 0x06000000 0x20000 // Bank2
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3 0 0x07000000 0x20000>; // Bank3
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compatible = "samsung,exynos4210-srom";
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reg = <0x12570000 0x14>;
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ethernet@3,0 {
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compatible = "smsc,lan9115";
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reg = <3 0 0x10000>; // Bank 3, offset = 0
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phy-mode = "mii";
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interrupt-parent = <&gpx0>;
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interrupts = <5 8>;
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reg-io-width = <2>;
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smsc,irq-push-pull;
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smsc,force-internal-phy;
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samsung,srom-page-mode;
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samsung,srom-timing = <9 12 1 9 1 1>;
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};
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};
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@@ -1,8 +1,26 @@
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Flash device on ARM Versatile board
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These flash chips are found in the ARM reference designs like Integrator,
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Versatile, RealView, Versatile Express etc.
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They are regular CFI compatible (Intel or AMD extended) flash chips with
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some special write protect/VPP bits that can be controlled by the machine's
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system controller.
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Required properties:
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- compatible : must be "arm,versatile-flash";
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- compatible : must be "arm,versatile-flash", "cfi-flash";
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- reg : memory address for the flash chip
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- bank-width : width in bytes of flash interface.
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For the rest of the properties, see mtd-physmap.txt.
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The device tree may optionally contain sub-nodes describing partitions of the
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address space. See partition.txt for more detail.
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Example:
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flash@34000000 {
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compatible = "arm,versatile-flash", "cfi-flash";
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reg = <0x34000000 0x4000000>;
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bank-width = <4>;
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};
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@@ -60,11 +60,14 @@ Required properties:
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- afi
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- pcie_x
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Required properties on Tegra124 and later:
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Required properties on Tegra124 and later (deprecated):
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- phys: Must contain an entry for each entry in phy-names.
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- phy-names: Must include the following entries:
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- pcie
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These properties are deprecated in favour of per-lane PHYs define in each of
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the root ports (see below).
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Power supplies for Tegra20:
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- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
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- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
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@@ -122,11 +125,22 @@ Required properties:
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- Root port 0 uses 4 lanes, root port 1 is unused.
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- Both root ports use 2 lanes.
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Example:
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Required properties for Tegra124 and later:
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- phys: Must contain an phandle to a PHY for each entry in phy-names.
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- phy-names: Must include an entry for each active lane. Note that the number
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of entries does not have to (though usually will) be equal to the specified
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number of lanes in the nvidia,num-lanes property. Entries are of the form
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"pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
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Examples:
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=========
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Tegra20:
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--------
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SoC DTSI:
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pcie-controller {
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pcie-controller@80003000 {
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compatible = "nvidia,tegra20-pcie";
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device_type = "pci";
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reg = <0x80003000 0x00000800 /* PADS registers */
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@@ -186,10 +200,9 @@ SoC DTSI:
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};
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};
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Board DTS:
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pcie-controller {
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pcie-controller@80003000 {
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status = "okay";
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vdd-supply = <&pci_vdd_reg>;
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@@ -222,3 +235,204 @@ if a device on the PCI bus provides a non-probeable bus such as I2C or SPI,
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device nodes need to be added in order to allow the bus' children to be
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instantiated at the proper location in the operating system's device tree (as
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illustrated by the optional nodes in the example above).
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Tegra30:
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--------
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SoC DTSI:
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pcie-controller@00003000 {
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compatible = "nvidia,tegra30-pcie";
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device_type = "pci";
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reg = <0x00003000 0x00000800 /* PADS registers */
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0x00003800 0x00000200 /* AFI registers */
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0x10000000 0x10000000>; /* configuration space */
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reg-names = "pads", "afi", "cs";
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
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GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
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interrupt-names = "intr", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
|
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0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
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0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
|
||||
0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
|
||||
0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
|
||||
|
||||
clocks = <&tegra_car TEGRA30_CLK_PCIE>,
|
||||
<&tegra_car TEGRA30_CLK_AFI>,
|
||||
<&tegra_car TEGRA30_CLK_PLL_E>,
|
||||
<&tegra_car TEGRA30_CLK_CML0>;
|
||||
clock-names = "pex", "afi", "pll_e", "cml";
|
||||
resets = <&tegra_car 70>,
|
||||
<&tegra_car 72>,
|
||||
<&tegra_car 74>;
|
||||
reset-names = "pex", "afi", "pcie_x";
|
||||
status = "disabled";
|
||||
|
||||
pci@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
|
||||
reg = <0x000800 0 0 0 0>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
nvidia,num-lanes = <2>;
|
||||
};
|
||||
|
||||
pci@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
|
||||
reg = <0x001000 0 0 0 0>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
nvidia,num-lanes = <2>;
|
||||
};
|
||||
|
||||
pci@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
|
||||
reg = <0x001800 0 0 0 0>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
nvidia,num-lanes = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
Board DTS:
|
||||
|
||||
pcie-controller@00003000 {
|
||||
status = "okay";
|
||||
|
||||
avdd-pexa-supply = <&ldo1_reg>;
|
||||
vdd-pexa-supply = <&ldo1_reg>;
|
||||
avdd-pexb-supply = <&ldo1_reg>;
|
||||
vdd-pexb-supply = <&ldo1_reg>;
|
||||
avdd-pex-pll-supply = <&ldo1_reg>;
|
||||
avdd-plle-supply = <&ldo1_reg>;
|
||||
vddio-pex-ctl-supply = <&sys_3v3_reg>;
|
||||
hvdd-pex-supply = <&sys_3v3_pexs_reg>;
|
||||
|
||||
pci@1,0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pci@3,0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
Tegra124:
|
||||
---------
|
||||
|
||||
SoC DTSI:
|
||||
|
||||
pcie-controller@01003000 {
|
||||
compatible = "nvidia,tegra124-pcie";
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
|
||||
0x0 0x01003800 0x0 0x00000800 /* AFI registers */
|
||||
0x0 0x02000000 0x0 0x10000000>; /* configuration space */
|
||||
reg-names = "pads", "afi", "cs";
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
|
||||
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
|
||||
interrupt-names = "intr", "msi";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
|
||||
0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
|
||||
0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
|
||||
0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
|
||||
0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
|
||||
|
||||
clocks = <&tegra_car TEGRA124_CLK_PCIE>,
|
||||
<&tegra_car TEGRA124_CLK_AFI>,
|
||||
<&tegra_car TEGRA124_CLK_PLL_E>,
|
||||
<&tegra_car TEGRA124_CLK_CML0>;
|
||||
clock-names = "pex", "afi", "pll_e", "cml";
|
||||
resets = <&tegra_car 70>,
|
||||
<&tegra_car 72>,
|
||||
<&tegra_car 74>;
|
||||
reset-names = "pex", "afi", "pcie_x";
|
||||
status = "disabled";
|
||||
|
||||
pci@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
|
||||
reg = <0x000800 0 0 0 0>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
nvidia,num-lanes = <2>;
|
||||
};
|
||||
|
||||
pci@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
|
||||
reg = <0x001000 0 0 0 0>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
nvidia,num-lanes = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
Board DTS:
|
||||
|
||||
pcie-controller@01003000 {
|
||||
status = "okay";
|
||||
|
||||
avddio-pex-supply = <&vdd_1v05_run>;
|
||||
dvddio-pex-supply = <&vdd_1v05_run>;
|
||||
avdd-pex-pll-supply = <&vdd_1v05_run>;
|
||||
hvdd-pex-supply = <&vdd_3v3_lp0>;
|
||||
hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
|
||||
vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
|
||||
avdd-pll-erefe-supply = <&avdd_1v05_run>;
|
||||
|
||||
/* Mini PCIe */
|
||||
pci@1,0 {
|
||||
phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
|
||||
phy-names = "pcie-0";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Gigabit Ethernet */
|
||||
pci@2,0 {
|
||||
phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
|
||||
phy-names = "pcie-0";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,6 +1,12 @@
|
||||
Device tree binding for NVIDIA Tegra XUSB pad controller
|
||||
========================================================
|
||||
|
||||
NOTE: It turns out that this binding isn't an accurate description of the XUSB
|
||||
pad controller. While the description is good enough for the functional subset
|
||||
required for PCIe and SATA, it lacks the flexibility to represent the features
|
||||
needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt.
|
||||
The binding described in this file is deprecated and should not be used.
|
||||
|
||||
The Tegra XUSB pad controller manages a set of lanes, each of which can be
|
||||
assigned to one out of a set of different pads. Some of these pads have an
|
||||
associated PHY that must be powered up before the pad can be used.
|
||||
|
||||
58
Documentation/devicetree/bindings/reset/oxnas,reset.txt
Normal file
58
Documentation/devicetree/bindings/reset/oxnas,reset.txt
Normal file
@@ -0,0 +1,58 @@
|
||||
Oxford Semiconductor OXNAS SoC Family RESET Controller
|
||||
================================================
|
||||
|
||||
Please also refer to reset.txt in this directory for common reset
|
||||
controller binding usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "oxsemi,ox810se-reset"
|
||||
- #reset-cells: 1, see below
|
||||
|
||||
Parent node should have the following properties :
|
||||
- compatible: Should be "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"
|
||||
|
||||
For OX810SE, the indices are :
|
||||
- 0 : ARM
|
||||
- 1 : COPRO
|
||||
- 2 : Reserved
|
||||
- 3 : Reserved
|
||||
- 4 : USBHS
|
||||
- 5 : USBHSPHY
|
||||
- 6 : MAC
|
||||
- 7 : PCI
|
||||
- 8 : DMA
|
||||
- 9 : DPE
|
||||
- 10 : DDR
|
||||
- 11 : SATA
|
||||
- 12 : SATA_LINK
|
||||
- 13 : SATA_PHY
|
||||
- 14 : Reserved
|
||||
- 15 : NAND
|
||||
- 16 : GPIO
|
||||
- 17 : UART1
|
||||
- 18 : UART2
|
||||
- 19 : MISC
|
||||
- 20 : I2S
|
||||
- 21 : AHB_MON
|
||||
- 22 : UART3
|
||||
- 23 : UART4
|
||||
- 24 : SGDMA
|
||||
- 25 : Reserved
|
||||
- 26 : Reserved
|
||||
- 27 : Reserved
|
||||
- 28 : Reserved
|
||||
- 29 : Reserved
|
||||
- 30 : Reserved
|
||||
- 31 : BUS
|
||||
|
||||
example:
|
||||
|
||||
sys: sys-ctrl@000000 {
|
||||
compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
|
||||
reg = <0x000000 0x100000>;
|
||||
|
||||
reset: reset-controller {
|
||||
compatible = "oxsemi,ox810se-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
@@ -7,6 +7,7 @@ Required properties for power domain controller:
|
||||
- compatible: Should be one of the following.
|
||||
"rockchip,rk3288-power-controller" - for RK3288 SoCs.
|
||||
"rockchip,rk3368-power-controller" - for RK3368 SoCs.
|
||||
"rockchip,rk3399-power-controller" - for RK3399 SoCs.
|
||||
- #power-domain-cells: Number of cells in a power-domain specifier.
|
||||
Should be 1 for multiple PM domains.
|
||||
- #address-cells: Should be 1.
|
||||
@@ -16,8 +17,18 @@ Required properties for power domain sub nodes:
|
||||
- reg: index of the power domain, should use macros in:
|
||||
"include/dt-bindings/power/rk3288-power.h" - for RK3288 type power domain.
|
||||
"include/dt-bindings/power/rk3368-power.h" - for RK3368 type power domain.
|
||||
"include/dt-bindings/power/rk3399-power.h" - for RK3399 type power domain.
|
||||
- clocks (optional): phandles to clocks which need to be enabled while power domain
|
||||
switches state.
|
||||
- pm_qos (optional): phandles to qos blocks which need to be saved and restored
|
||||
while power domain switches state.
|
||||
|
||||
Qos Example:
|
||||
|
||||
qos_gpu: qos_gpu@ffaf0000 {
|
||||
compatible ="syscon";
|
||||
reg = <0x0 0xffaf0000 0x0 0x20>;
|
||||
};
|
||||
|
||||
Example:
|
||||
|
||||
@@ -30,6 +41,7 @@ Example:
|
||||
pd_gpu {
|
||||
reg = <RK3288_PD_GPU>;
|
||||
clocks = <&cru ACLK_GPU>;
|
||||
pm_qos = <&qos_gpu>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -45,12 +57,41 @@ Example:
|
||||
};
|
||||
};
|
||||
|
||||
Example 2:
|
||||
power: power-controller {
|
||||
compatible = "rockchip,rk3399-power-controller";
|
||||
#power-domain-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pd_vio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <RK3399_PD_VIO>;
|
||||
|
||||
pd_vo {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <RK3399_PD_VO>;
|
||||
|
||||
pd_vopb {
|
||||
reg = <RK3399_PD_VOPB>;
|
||||
};
|
||||
|
||||
pd_vopl {
|
||||
reg = <RK3399_PD_VOPL>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Node of a device using power domains must have a power-domains property,
|
||||
containing a phandle to the power device node and an index specifying which
|
||||
power domain to use.
|
||||
The index should use macros in:
|
||||
"include/dt-bindings/power/rk3288-power.h" - for rk3288 type power domain.
|
||||
"include/dt-bindings/power/rk3368-power.h" - for rk3368 type power domain.
|
||||
"include/dt-bindings/power/rk3399-power.h" - for rk3399 type power domain.
|
||||
|
||||
Example of the node using power domain:
|
||||
|
||||
@@ -65,3 +106,9 @@ Example of the node using power domain:
|
||||
power-domains = <&power RK3368_PD_GPU_1>;
|
||||
/* ... */
|
||||
};
|
||||
|
||||
node {
|
||||
/* ... */
|
||||
power-domains = <&power RK3399_PD_VOPB>;
|
||||
/* ... */
|
||||
};
|
||||
|
||||
120
Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt
Normal file
120
Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt
Normal file
@@ -0,0 +1,120 @@
|
||||
NVIDIA Tegra xHCI controller
|
||||
============================
|
||||
|
||||
The Tegra xHCI controller supports both USB2 and USB3 interfaces exposed by
|
||||
the Tegra XUSB pad controller.
|
||||
|
||||
Required properties:
|
||||
--------------------
|
||||
- compatible: Must be:
|
||||
- Tegra124: "nvidia,tegra124-xusb"
|
||||
- Tegra132: "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"
|
||||
- Tegra210: "nvidia,tegra210-xusb"
|
||||
- reg: Must contain the base and length of the xHCI host registers, XUSB FPCI
|
||||
registers and XUSB IPFS registers.
|
||||
- reg-names: Must contain the following entries:
|
||||
- "hcd"
|
||||
- "fpci"
|
||||
- "ipfs"
|
||||
- interrupts: Must contain the xHCI host interrupt and the mailbox interrupt.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clock/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
- xusb_host
|
||||
- xusb_host_src
|
||||
- xusb_falcon_src
|
||||
- xusb_ss
|
||||
- xusb_ss_src
|
||||
- xusb_ss_div2
|
||||
- xusb_hs_src
|
||||
- xusb_fs_src
|
||||
- pll_u_480m
|
||||
- clk_m
|
||||
- pll_e
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- xusb_host
|
||||
- xusb_ss
|
||||
- xusb_src
|
||||
Note that xusb_src is the shared reset for xusb_{ss,hs,fs,falcon,host}_src.
|
||||
- nvidia,xusb-padctl: phandle to the XUSB pad controller that is used to
|
||||
configure the USB pads used by the XHCI controller
|
||||
|
||||
For Tegra124 and Tegra132:
|
||||
- avddio-pex-supply: PCIe/USB3 analog logic power supply. Must supply 1.05 V.
|
||||
- dvddio-pex-supply: PCIe/USB3 digital logic power supply. Must supply 1.05 V.
|
||||
- avdd-usb-supply: USB controller power supply. Must supply 3.3 V.
|
||||
- avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
|
||||
- avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
|
||||
- avdd-usb-ss-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
|
||||
- hvdd-usb-ss-supply: High-voltage PCIe/USB3 power supply. Must supply 3.3 V.
|
||||
- hvdd-usb-ss-pll-e-supply: High-voltage PLLE power supply. Must supply 3.3 V.
|
||||
|
||||
For Tegra210:
|
||||
- dvddio-pex-supply: PCIe/USB3 analog logic power supply. Must supply 1.05 V.
|
||||
- hvddio-pex-supply: High-voltage PCIe/USB3 power supply. Must supply 1.8 V.
|
||||
- avdd-usb-supply: USB controller power supply. Must supply 3.3 V.
|
||||
- avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
|
||||
- avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
|
||||
- dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
|
||||
- hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V.
|
||||
|
||||
Optional properties:
|
||||
--------------------
|
||||
- phys: Must contain an entry for each entry in phy-names.
|
||||
See ../phy/phy-bindings.txt for details.
|
||||
- phy-names: Should include an entry for each PHY used by the controller. The
|
||||
following PHYs are available:
|
||||
- Tegra124: usb2-0, usb2-1, usb2-2, hsic-0, hsic-1, usb3-0, usb3-1
|
||||
- Tegra132: usb2-0, usb2-1, usb2-2, hsic-0, hsic-1, usb3-0, usb3-1
|
||||
- Tegra210: usb2-0, usb2-1, usb2-2, usb2-3, hsic-0, usb3-0, usb3-1, usb3-2,
|
||||
usb3-3
|
||||
|
||||
Example:
|
||||
--------
|
||||
|
||||
usb@0,70090000 {
|
||||
compatible = "nvidia,tegra124-xusb";
|
||||
reg = <0x0 0x70090000 0x0 0x8000>,
|
||||
<0x0 0x70098000 0x0 0x1000>,
|
||||
<0x0 0x70099000 0x0 0x1000>;
|
||||
reg-names = "hcd", "fpci", "ipfs";
|
||||
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_SS>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
|
||||
<&tegra_car TEGRA124_CLK_PLL_U_480M>,
|
||||
<&tegra_car TEGRA124_CLK_CLK_M>,
|
||||
<&tegra_car TEGRA124_CLK_PLL_E>;
|
||||
clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src",
|
||||
"xusb_ss", "xusb_ss_div2", "xusb_ss_src",
|
||||
"xusb_hs_src", "xusb_fs_src", "pll_u_480m",
|
||||
"clk_m", "pll_e";
|
||||
resets = <&tegra_car 89>, <&tegra_car 156>, <&tegra_car 143>;
|
||||
reset-names = "xusb_host", "xusb_ss", "xusb_src";
|
||||
|
||||
nvidia,xusb-padctl = <&padctl>;
|
||||
|
||||
phys = <&{/padctl@0,7009f000/pads/usb2/usb2-1}>, /* mini-PCIe USB */
|
||||
<&{/padctl@0,7009f000/pads/usb2/usb2-2}>, /* USB A */
|
||||
<&{/padctl@0,7009f000/pads/pcie/pcie-0}>; /* USB A */
|
||||
phy-names = "utmi-1", "utmi-2", "usb3-0";
|
||||
|
||||
avddio-pex-supply = <&vdd_1v05_run>;
|
||||
dvddio-pex-supply = <&vdd_1v05_run>;
|
||||
avdd-usb-supply = <&vdd_3v3_lp0>;
|
||||
avdd-pll-utmip-supply = <&vddio_1v8>;
|
||||
avdd-pll-erefe-supply = <&avdd_1v05_run>;
|
||||
avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
|
||||
hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
|
||||
hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;
|
||||
};
|
||||
@@ -31,16 +31,28 @@ should provide its own implementation of of_xlate. of_xlate is used only for
|
||||
dt boot case.
|
||||
|
||||
#define of_phy_provider_register(dev, xlate) \
|
||||
__of_phy_provider_register((dev), THIS_MODULE, (xlate))
|
||||
__of_phy_provider_register((dev), NULL, THIS_MODULE, (xlate))
|
||||
|
||||
#define devm_of_phy_provider_register(dev, xlate) \
|
||||
__devm_of_phy_provider_register((dev), THIS_MODULE, (xlate))
|
||||
__devm_of_phy_provider_register((dev), NULL, THIS_MODULE, (xlate))
|
||||
|
||||
of_phy_provider_register and devm_of_phy_provider_register macros can be used to
|
||||
register the phy_provider and it takes device and of_xlate as
|
||||
arguments. For the dt boot case, all PHY providers should use one of the above
|
||||
2 macros to register the PHY provider.
|
||||
|
||||
Often the device tree nodes associated with a PHY provider will contain a set
|
||||
of children that each represent a single PHY. Some bindings may nest the child
|
||||
nodes within extra levels for context and extensibility, in which case the low
|
||||
level of_phy_provider_register_full() and devm_of_phy_provider_register_full()
|
||||
macros can be used to override the node containing the children.
|
||||
|
||||
#define of_phy_provider_register_full(dev, children, xlate) \
|
||||
__of_phy_provider_register(dev, children, THIS_MODULE, xlate)
|
||||
|
||||
#define devm_of_phy_provider_register_full(dev, children, xlate) \
|
||||
__devm_of_phy_provider_register_full(dev, children, THIS_MODULE, xlate)
|
||||
|
||||
void devm_of_phy_provider_unregister(struct device *dev,
|
||||
struct phy_provider *phy_provider);
|
||||
void of_phy_provider_unregister(struct phy_provider *phy_provider);
|
||||
|
||||
@@ -1535,6 +1535,8 @@ Q: http://patchwork.kernel.org/project/linux-renesas-soc/list/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git next
|
||||
S: Supported
|
||||
F: arch/arm64/boot/dts/renesas/
|
||||
F: drivers/soc/renesas/
|
||||
F: include/linux/soc/renesas/
|
||||
|
||||
ARM/RISCPC ARCHITECTURE
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
@@ -1584,6 +1586,7 @@ F: arch/arm/mach-s5p*/
|
||||
F: arch/arm/mach-exynos*/
|
||||
F: drivers/*/*s3c2410*
|
||||
F: drivers/*/*/*s3c2410*
|
||||
F: drivers/memory/samsung/*
|
||||
F: drivers/soc/samsung/*
|
||||
F: drivers/spi/spi-s3c*
|
||||
F: sound/soc/samsung/*
|
||||
@@ -1648,6 +1651,8 @@ F: arch/arm/configs/shmobile_defconfig
|
||||
F: arch/arm/include/debug/renesas-scif.S
|
||||
F: arch/arm/mach-shmobile/
|
||||
F: drivers/sh/
|
||||
F: drivers/soc/renesas/
|
||||
F: include/linux/soc/renesas/
|
||||
|
||||
ARM/SOCFPGA ARCHITECTURE
|
||||
M: Dinh Nguyen <dinguyen@opensource.altera.com>
|
||||
|
||||
@@ -52,8 +52,9 @@
|
||||
};
|
||||
|
||||
flash@24000000 {
|
||||
compatible = "cfi-flash";
|
||||
compatible = "arm,versatile-flash", "cfi-flash";
|
||||
reg = <0x24000000 0x02000000>;
|
||||
bank-width = <4>;
|
||||
};
|
||||
|
||||
fpga {
|
||||
|
||||
@@ -119,8 +119,9 @@
|
||||
};
|
||||
|
||||
flash@34000000 {
|
||||
compatible = "arm,versatile-flash";
|
||||
reg = <0x34000000 0x4000000>;
|
||||
/* 64 MiB NOR flash in non-interleaved chips */
|
||||
compatible = "arm,versatile-flash", "cfi-flash";
|
||||
reg = <0x34000000 0x04000000>;
|
||||
bank-width = <4>;
|
||||
};
|
||||
|
||||
|
||||
@@ -173,12 +173,12 @@ config ARCH_BRCMSTB
|
||||
select ARM_GIC
|
||||
select ARM_ERRATA_798181 if SMP
|
||||
select HAVE_ARM_ARCH_TIMER
|
||||
select BRCMSTB_GISB_ARB
|
||||
select BRCMSTB_L2_IRQ
|
||||
select BCM7120_L2_IRQ
|
||||
select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
|
||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
select SOC_BRCMSTB
|
||||
select SOC_BUS
|
||||
help
|
||||
Say Y if you intend to run the kernel on a Broadcom ARM-based STB
|
||||
chipset.
|
||||
|
||||
@@ -18,6 +18,7 @@ menuconfig ARCH_EXYNOS
|
||||
select COMMON_CLK_SAMSUNG
|
||||
select EXYNOS_THERMAL
|
||||
select EXYNOS_PMU
|
||||
select EXYNOS_SROM
|
||||
select HAVE_ARM_SCU if SMP
|
||||
select HAVE_S3C2410_I2C if I2C
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
@@ -26,11 +27,13 @@ menuconfig ARCH_EXYNOS
|
||||
select PINCTRL_EXYNOS
|
||||
select PM_GENERIC_DOMAINS if PM
|
||||
select S5P_DEV_MFC
|
||||
select SAMSUNG_MC
|
||||
select SOC_SAMSUNG
|
||||
select SRAM
|
||||
select THERMAL
|
||||
select THERMAL_OF
|
||||
select MFD_SYSCON
|
||||
select MEMORY
|
||||
select CLKSRC_EXYNOS_MCT
|
||||
select POWER_RESET
|
||||
select POWER_RESET_SYSCON
|
||||
|
||||
@@ -31,11 +31,6 @@
|
||||
|
||||
static struct map_desc exynos4_iodesc[] __initdata = {
|
||||
{
|
||||
.virtual = (unsigned long)S5P_VA_SROMC,
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_CMU,
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
|
||||
.length = SZ_128K,
|
||||
@@ -58,15 +53,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct map_desc exynos5_iodesc[] __initdata = {
|
||||
{
|
||||
.virtual = (unsigned long)S5P_VA_SROMC,
|
||||
.pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device exynos_cpuidle = {
|
||||
.name = "exynos_cpuidle",
|
||||
#ifdef CONFIG_ARM_EXYNOS_CPUIDLE
|
||||
@@ -138,9 +124,6 @@ static void __init exynos_map_io(void)
|
||||
{
|
||||
if (soc_is_exynos4())
|
||||
iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
|
||||
|
||||
if (soc_is_exynos5())
|
||||
iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
|
||||
}
|
||||
|
||||
static void __init exynos_init_io(void)
|
||||
|
||||
@@ -25,7 +25,4 @@
|
||||
|
||||
#define EXYNOS4_PA_COREPERI 0x10500000
|
||||
|
||||
#define EXYNOS4_PA_SROMC 0x12570000
|
||||
#define EXYNOS5_PA_SROMC 0x12250000
|
||||
|
||||
#endif /* __ASM_ARCH_MAP_H */
|
||||
|
||||
@@ -1,53 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5P SROMC register definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __PLAT_SAMSUNG_REGS_SROM_H
|
||||
#define __PLAT_SAMSUNG_REGS_SROM_H __FILE__
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
#define S5P_SROMREG(x) (S5P_VA_SROMC + (x))
|
||||
|
||||
#define S5P_SROM_BW S5P_SROMREG(0x0)
|
||||
#define S5P_SROM_BC0 S5P_SROMREG(0x4)
|
||||
#define S5P_SROM_BC1 S5P_SROMREG(0x8)
|
||||
#define S5P_SROM_BC2 S5P_SROMREG(0xc)
|
||||
#define S5P_SROM_BC3 S5P_SROMREG(0x10)
|
||||
#define S5P_SROM_BC4 S5P_SROMREG(0x14)
|
||||
#define S5P_SROM_BC5 S5P_SROMREG(0x18)
|
||||
|
||||
/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
|
||||
|
||||
#define S5P_SROM_BW__DATAWIDTH__SHIFT 0
|
||||
#define S5P_SROM_BW__ADDRMODE__SHIFT 1
|
||||
#define S5P_SROM_BW__WAITENABLE__SHIFT 2
|
||||
#define S5P_SROM_BW__BYTEENABLE__SHIFT 3
|
||||
|
||||
#define S5P_SROM_BW__CS_MASK 0xf
|
||||
|
||||
#define S5P_SROM_BW__NCS0__SHIFT 0
|
||||
#define S5P_SROM_BW__NCS1__SHIFT 4
|
||||
#define S5P_SROM_BW__NCS2__SHIFT 8
|
||||
#define S5P_SROM_BW__NCS3__SHIFT 12
|
||||
#define S5P_SROM_BW__NCS4__SHIFT 16
|
||||
#define S5P_SROM_BW__NCS5__SHIFT 20
|
||||
|
||||
/* applies to same to BCS0 - BCS3 */
|
||||
|
||||
#define S5P_SROM_BCX__PMC__SHIFT 0
|
||||
#define S5P_SROM_BCX__TACP__SHIFT 4
|
||||
#define S5P_SROM_BCX__TCAH__SHIFT 8
|
||||
#define S5P_SROM_BCX__TCOH__SHIFT 12
|
||||
#define S5P_SROM_BCX__TACC__SHIFT 16
|
||||
#define S5P_SROM_BCX__TCOS__SHIFT 24
|
||||
#define S5P_SROM_BCX__TACS__SHIFT 28
|
||||
|
||||
#endif /* __PLAT_SAMSUNG_REGS_SROM_H */
|
||||
@@ -34,10 +34,11 @@
|
||||
#include <asm/smp_scu.h>
|
||||
#include <asm/suspend.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <plat/pm-common.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "regs-srom.h"
|
||||
|
||||
#define REG_TABLE_END (-1U)
|
||||
|
||||
@@ -53,15 +54,6 @@ struct exynos_wkup_irq {
|
||||
u32 mask;
|
||||
};
|
||||
|
||||
static struct sleep_save exynos_core_save[] = {
|
||||
/* SROM side */
|
||||
SAVE_ITEM(S5P_SROM_BW),
|
||||
SAVE_ITEM(S5P_SROM_BC0),
|
||||
SAVE_ITEM(S5P_SROM_BC1),
|
||||
SAVE_ITEM(S5P_SROM_BC2),
|
||||
SAVE_ITEM(S5P_SROM_BC3),
|
||||
};
|
||||
|
||||
struct exynos_pm_data {
|
||||
const struct exynos_wkup_irq *wkup_irq;
|
||||
unsigned int wake_disable_mask;
|
||||
@@ -343,8 +335,6 @@ static void exynos_pm_prepare(void)
|
||||
/* Set wake-up mask registers */
|
||||
exynos_pm_set_wakeup_mask();
|
||||
|
||||
s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
|
||||
|
||||
exynos_pm_enter_sleep_mode();
|
||||
|
||||
/* ensure at least INFORM0 has the resume address */
|
||||
@@ -375,8 +365,6 @@ static void exynos5420_pm_prepare(void)
|
||||
/* Set wake-up mask registers */
|
||||
exynos_pm_set_wakeup_mask();
|
||||
|
||||
s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
|
||||
|
||||
exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
|
||||
/*
|
||||
* The cpu state needs to be saved and restored so that the
|
||||
@@ -467,8 +455,6 @@ static void exynos_pm_resume(void)
|
||||
/* For release retention */
|
||||
exynos_pm_release_retention();
|
||||
|
||||
s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
|
||||
|
||||
if (cpuid == ARM_CPU_PART_CORTEX_A9)
|
||||
scu_enable(S5P_VA_SCU);
|
||||
|
||||
@@ -535,8 +521,6 @@ static void exynos5420_pm_resume(void)
|
||||
|
||||
pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3);
|
||||
|
||||
s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
|
||||
|
||||
early_wakeup:
|
||||
|
||||
tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
|
||||
|
||||
@@ -29,7 +29,6 @@
|
||||
#include <linux/amba/kmi.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/platform_data/clk-integrator.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_address.h>
|
||||
@@ -146,65 +145,6 @@ static int __init irq_syscore_init(void)
|
||||
|
||||
device_initcall(irq_syscore_init);
|
||||
|
||||
/*
|
||||
* Flash handling.
|
||||
*/
|
||||
static int ap_flash_init(struct platform_device *dev)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
|
||||
ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
|
||||
|
||||
tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) |
|
||||
INTEGRATOR_EBI_WRITE_ENABLE;
|
||||
writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
|
||||
|
||||
if (!(readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET)
|
||||
& INTEGRATOR_EBI_WRITE_ENABLE)) {
|
||||
writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
|
||||
writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
|
||||
writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ap_flash_exit(struct platform_device *dev)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
|
||||
ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
|
||||
|
||||
tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
|
||||
~INTEGRATOR_EBI_WRITE_ENABLE;
|
||||
writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
|
||||
|
||||
if (readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
|
||||
INTEGRATOR_EBI_WRITE_ENABLE) {
|
||||
writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
|
||||
writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
|
||||
writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
|
||||
}
|
||||
}
|
||||
|
||||
static void ap_flash_set_vpp(struct platform_device *pdev, int on)
|
||||
{
|
||||
if (on)
|
||||
writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
|
||||
ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
|
||||
else
|
||||
writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
|
||||
ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
|
||||
}
|
||||
|
||||
static struct physmap_flash_data ap_flash_data = {
|
||||
.width = 4,
|
||||
.init = ap_flash_init,
|
||||
.exit = ap_flash_exit,
|
||||
.set_vpp = ap_flash_set_vpp,
|
||||
};
|
||||
|
||||
/*
|
||||
* For the PL010 found in the Integrator/AP some of the UART control is
|
||||
* implemented in the system controller and accessed using a callback
|
||||
@@ -266,8 +206,6 @@ static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
|
||||
"kmi0", NULL),
|
||||
OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
|
||||
"kmi1", NULL),
|
||||
OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
|
||||
"physmap-flash", &ap_flash_data),
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user