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Merge tag 'omap-for-v5.17/fixes-for-merge-window-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/fixes

Browse Source 
Fixes for omaps

A series of fixes for omap variants for minor issues, and a fix for a timer
regression for some omap3 beagleboard versions.

The timer fix needs to patch both the dts and the timer code because
otherwise the timer quirk handling for old dtbs will prevent the dts fix
from working.

The other changes are for issues found by automated analysis, a macasp
typo fix, and two cosmetic fixes for clocks.

* tag 'omap-for-v5.17/fixes-for-merge-window-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: dts: Don't use legacy clock defines for dra7 clkctrl
  clk: ti: Move dra7 clock devices out of the legacy section
  ARM: dts: Fix timer regression for beagleboard revision c
  ARM: dts: am335x-wega: Fix typo in mcasp property rx-num-evt
  ARM: OMAP2+: adjust the location of put_device() call in omapdss_init_of
  ARM: OMAP2+: hwmod: Add of_node_put() before break

Link: https://lore.kernel.org/r/pull-1641801310-149268@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2022-02-07 17:42:43 +01:00
parent 63a8728579 31aa7056bb
commit 486343d372
10 changed files with 74 additions and 54 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
Documentation/devicetree/bindings/arm/omap/omap.txt
View File

@@ -119,6 +119,9 @@ Boards (incomplete list of examples):
- OMAP3 BeagleBoard : Low cost community board
compatible = "ti,omap3-beagle", "ti,omap3430", "ti,omap3"
- OMAP3 BeagleBoard A to B4 : Early BeagleBoard revisions A to B4 with a timer quirk
compatible = "ti,omap3-beagle-ab4", "ti,omap3-beagle", "ti,omap3430", "ti,omap3"
- OMAP3 Tobi with Overo : Commercial expansion board with daughter board
compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"

1
arch/arm/boot/dts/Makefile
View File

@@ -806,6 +806,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += \
logicpd-som-lv-37xx-devkit.dtb \
omap3430-sdp.dtb \
omap3-beagle.dtb \
omap3-beagle-ab4.dtb \
omap3-beagle-xm.dtb \
omap3-beagle-xm-ab.dtb \
omap3-cm-t3517.dtb \

2
arch/arm/boot/dts/am335x-wega.dtsi
View File

@@ -55,7 +55,7 @@
2 1 0 0 /* # 0: INACTIVE, 1: TX, 2: RX */
>;
tx-num-evt = <16>;
rt-num-evt = <16>;
rx-num-evt = <16>;
status = "okay";
};

20
arch/arm/boot/dts/dra7.dtsi
View File

@@ -160,7 +160,7 @@
target-module@48210000 {
compatible = "ti,sysc-omap4-simple", "ti,sysc";
power-domains = <&prm_mpu>;
clocks = <&mpu_clkctrl DRA7_MPU_CLKCTRL 0>;
clocks = <&mpu_clkctrl DRA7_MPU_MPU_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
@@ -875,10 +875,10 @@
<0x58000014 4>;
reg-names = "rev", "syss";
ti,syss-mask = <1>;
clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 0>,
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>,
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 11>;
clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 0>,
<&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
<&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>,
<&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 11>;
clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
#address-cells = <1>;
#size-cells = <1>;
@@ -912,7 +912,7 @@
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,syss-mask = <1>;
clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
@@ -939,8 +939,8 @@
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
<&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
clock-names = "fck", "dss_clk";
#address-cells = <1>;
#size-cells = <1>;
@@ -979,7 +979,7 @@
compatible = "vivante,gc";
reg = <0x0 0x700>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dss_clkctrl DRA7_BB2D_CLKCTRL 0>;
clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>;
clock-names = "core";
};
};
@@ -1333,7 +1333,7 @@
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>;
assigned-clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>;
assigned-clock-parents = <&sys_32k_ck>;
};
};

47
arch/arm/boot/dts/omap3-beagle-ab4.dts Normal file
View File

@@ -0,0 +1,47 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include "omap3-beagle.dts"
/ {
model = "TI OMAP3 BeagleBoard A to B4";
compatible = "ti,omap3-beagle-ab4", "ti,omap3-beagle", "ti,omap3430", "ti,omap3";
};
/*
* Workaround for capacitor C70 issue, see "Boards revision A and < B5"
* section at https://elinux.org/BeagleBoard_Community
*/
/* Unusable as clocksource because of unreliable oscillator */
&counter32k {
status = "disabled";
};
/* Unusable as clockevent because of unreliable oscillator, allow to idle */
&timer1_target {
/delete-property/ti,no-reset-on-init;
/delete-property/ti,no-idle;
timer@0 {
/delete-property/ti,timer-alwon;
};
};
/* Preferred always-on timer for clocksource */
&timer12_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
/* Always clocked by secure_32k_fck */
};
};
/* Preferred timer for clockevent */
&timer2_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&gpt2_fck>;
assigned-clock-parents = <&sys_ck>;
};
};

33
arch/arm/boot/dts/omap3-beagle.dts
View File

@@ -304,39 +304,6 @@
phys = <0 &hsusb2_phy>;
};
/* Unusable as clocksource because of unreliable oscillator */
&counter32k {
status = "disabled";
};
/* Unusable as clockevent because if unreliable oscillator, allow to idle */
&timer1_target {
/delete-property/ti,no-reset-on-init;
/delete-property/ti,no-idle;
timer@0 {
/delete-property/ti,timer-alwon;
};
};
/* Preferred always-on timer for clocksource */
&timer12_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
/* Always clocked by secure_32k_fck */
};
};
/* Preferred timer for clockevent */
&timer2_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&gpt2_fck>;
assigned-clock-parents = <&sys_ck>;
};
};
&twl_gpio {
ti,use-leds;
/* pullups: BIT(1) */

2
arch/arm/mach-omap2/display.c
View File

@@ -263,9 +263,9 @@ static int __init omapdss_init_of(void)
}
r = of_platform_populate(node, NULL, NULL, &pdev->dev);
put_device(&pdev->dev);
if (r) {
pr_err("Unable to populate DSS submodule devices\n");
put_device(&pdev->dev);
return r;
}

4
arch/arm/mach-omap2/omap_hwmod.c
View File

@@ -752,8 +752,10 @@ static int __init _init_clkctrl_providers(void)
for_each_matching_node(np, ti_clkctrl_match_table) {
ret = _setup_clkctrl_provider(np);
if (ret)
if (ret) {
of_node_put(np);
break;
}
}
return ret;

2
drivers/clocksource/timer-ti-dm-systimer.c
View File

@@ -241,7 +241,7 @@ static void __init dmtimer_systimer_assign_alwon(void)
bool quirk_unreliable_oscillator = false;
/* Quirk unreliable 32 KiHz oscillator with incomplete dts */
if (of_machine_is_compatible("ti,omap3-beagle") ||
if (of_machine_is_compatible("ti,omap3-beagle-ab4") ||
of_machine_is_compatible("timll,omap3-devkit8000")) {
quirk_unreliable_oscillator = true;
counter_32k = -ENODEV;

14
include/dt-bindings/clock/dra7.h
View File

@@ -84,17 +84,10 @@
#define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
/* iva clocks */
#define DRA7_IVA_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_SL2IF_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
/* dss clocks */
#define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
/* gpu clocks */
#define DRA7_GPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* l3init clocks */
#define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
@@ -267,10 +260,17 @@
#define DRA7_L3INSTR_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_L3INSTR_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
/* iva clocks */
#define DRA7_IVA_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_SL2IF_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
/* dss clocks */
#define DRA7_DSS_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_DSS_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
/* gpu clocks */
#define DRA7_GPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* l3init clocks */
#define DRA7_L3INIT_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_L3INIT_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)