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arm64: dts: Add device trees for NanoPi R6S and R6C

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arm64: dts: Add device trees for NanoPi R6S and R6C

arm64: dts: Add device trees for NanoPi R6S and R6C

arm64: dts: Add device trees for NanoPi R6S and R6C
This commit is contained in:
Muhammed Efe Çetin
2023-04-14 16:17:34 +03:00
committed by Jianfeng Liu
parent b022c3c037
commit 3c65b6d52f
4 changed files with 907 additions and 0 deletions
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2
arch/arm64/boot/dts/rockchip/Makefile
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@@ -352,5 +352,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-rk806-single-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-v11.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb
subdir-y := $(dts-dirs) overlay

688
arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6-common.dtsi Normal file
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28
arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts Normal file
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@@ -0,0 +1,28 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 FriendlyElec Computer Tech. Co., Ltd.
* (http://www.friendlyelec.com)
*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rk3588s-nanopi-r6s.dts"
/ {
model = "FriendlyElec NanoPi R6C";
compatible = "friendlyelec,nanopi-r6c", "rockchip,rk3588";
aliases {
ethernet0 = &r8125_u25;
};
};
&lan2_led {
label = "user_led";
};
&pcie2x1l2 {
/delete-node/ pcie@40;
};

189
arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts Normal file
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@@ -0,0 +1,189 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
* (http://www.friendlyelec.com)
*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rk3588s-nanopi-r6-common.dtsi"
/ {
model = "FriendlyElec NanoPi R6S";
compatible = "friendlyelec,nanopi-r6s", "rockchip,rk3588";
aliases {
ethernet0 = &r8125_u25;
};
gpio_keys: gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&key1_pin>;
button@1 {
debounce-interval = <50>;
gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>;
label = "K1";
linux,code = <BTN_1>;
wakeup-source;
};
};
gpio_leds: gpio-leds {
compatible = "gpio-leds";
sys_led: led-0 {
gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
label = "sys_led";
linux,default-trigger = "heartbeat";
pinctrl-names = "default";
pinctrl-0 = <&sys_led_pin>;
};
wan_led: led-1 {
gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
label = "wan_led";
pinctrl-names = "default";
pinctrl-0 = <&wan_led_pin>;
};
lan1_led: led-2 {
gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
label = "lan1_led";
pinctrl-names = "default";
pinctrl-0 = <&lan1_led_pin>;
};
lan2_led: led-3 {
gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
label = "lan2_led";
pinctrl-names = "default";
pinctrl-0 = <&lan2_led_pin>;
};
};
vcc5v0_host_20: vcc5v0-host-20 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host20_en>;
regulator-name = "vcc5v0_host_20";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_usb>;
};
};
&pcie2x1l1 {
pcie@30 {
reg = <0x00300000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
r8125_u25: pcie@30,0 {
reg = <0x000000 0 0 0 0>;
local-mac-address = [ 00 00 00 00 00 00 ];
};
};
};
&pcie2x1l2 {
pcie@40 {
reg = <0x00400000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
r8125_u40: pcie@40,0 {
reg = <0x000000 0 0 0 0>;
local-mac-address = [ 00 00 00 00 00 00 ];
};
};
};
&pinctrl {
gpio-key {
key1_pin: key1-pin {
rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
gpio-leds {
sys_led_pin: sys-led-pin {
rockchip,pins =
<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
wan_led_pin: wan-led-pin {
rockchip,pins =
<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
lan1_led_pin: lan1-led-pin {
rockchip,pins =
<1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
};
lan2_led_pin: lan2-led-pin {
rockchip,pins =
<1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
vcc5v0_host20_en: vcc5v0-host20-en {
rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&i2c6 {
clock-frequency = <200000>;
status = "okay";
eeprom@53 {
compatible = "microchip,24c02", "atmel,24c02";
reg = <0x53>;
#address-cells = <2>;
#size-cells = <0>;
pagesize = <16>;
size = <256>;
eui_48: eui-48@fa {
reg = <0xfa 0x06>;
};
};
};
&u2phy0 {
status = "okay";
};
&u2phy0_otg {
phy-supply = <&vbus5v0_typec>;
status = "okay";
};
&u2phy2 {
status = "okay";
};
&u2phy2_host {
phy-supply = <&vcc5v0_host_20>;
status = "okay";
};
&vp0 {
rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 |
1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>;
rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART0>;
cursor-win-id = <ROCKCHIP_VOP2_ESMART3>;
};
&vp3 {
/delete-property/ rockchip,plane-mask;
/delete-property/ rockchip,primary-plane;
};