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Merge tag 'char-misc-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

Browse Source 
Pull char / misc driver updates from Greg KH:
 "Here is the large set of char and misc and other driver subsystem
  changes for 6.0-rc1.

  Highlights include:

   - large set of IIO driver updates, additions, and cleanups

   - new habanalabs device support added (loads of register maps much
     like GPUs have)

   - soundwire driver updates

   - phy driver updates

   - slimbus driver updates

   - tiny virt driver fixes and updates

   - misc driver fixes and updates

   - interconnect driver updates

   - hwtracing driver updates

   - fpga driver updates

   - extcon driver updates

   - firmware driver updates

   - counter driver update

   - mhi driver fixes and updates

   - binder driver fixes and updates

   - speakup driver fixes

  All of these have been in linux-next for a while without any reported
  problems"

* tag 'char-misc-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (634 commits)
  drivers: lkdtm: fix clang -Wformat warning
  char: remove VR41XX related char driver
  misc: Mark MICROCODE_MINOR unused
  spmi: trace: fix stack-out-of-bound access in SPMI tracing functions
  dt-bindings: iio: adc: Add compatible for MT8188
  iio: light: isl29028: Fix the warning in isl29028_remove()
  iio: accel: sca3300: Extend the trigger buffer from 16 to 32 bytes
  iio: fix iio_format_avail_range() printing for none IIO_VAL_INT
  iio: adc: max1027: unlock on error path in max1027_read_single_value()
  iio: proximity: sx9324: add empty line in front of bullet list
  iio: magnetometer: hmc5843: Remove duplicate 'the'
  iio: magn: yas530: Use DEFINE_RUNTIME_DEV_PM_OPS() and pm_ptr() macros
  iio: magnetometer: ak8974: Use DEFINE_RUNTIME_DEV_PM_OPS() and pm_ptr() macros
  iio: light: veml6030: Use DEFINE_RUNTIME_DEV_PM_OPS() and pm_ptr() macros
  iio: light: vcnl4035: Use DEFINE_RUNTIME_DEV_PM_OPS() and pm_ptr() macros
  iio: light: vcnl4000: Use DEFINE_RUNTIME_DEV_PM_OPS() and pm_ptr() macros
  iio: light: tsl2591: Use DEFINE_RUNTIME_DEV_PM_OPS() and pm_ptr()
  iio: light: tsl2583: Use DEFINE_RUNTIME_DEV_PM_OPS and pm_ptr()
  iio: light: isl29028: Use DEFINE_RUNTIME_DEV_PM_OPS() and pm_ptr()
  iio: light: gp2ap002: Switch to DEFINE_RUNTIME_DEV_PM_OPS and pm_ptr()
  ...
This commit is contained in:
Linus Torvalds
2022-08-04 11:05:48 -07:00
parent 798cd57cd5 b5276c9244
commit 228dfe98a3
706 changed files with 184551 additions and 11936 deletions
Download Patch File Download Diff File Expand all files Collapse all files

38
Documentation/ABI/testing/debugfs-driver-habanalabs
View File

@@ -101,6 +101,15 @@ Description: Specify the size of the DMA transaction when using DMA to read
When the write is finished, the user can read the "data_dma"
blob
What: /sys/kernel/debug/habanalabs/hl<n>/dump_razwi_events
Date: Aug 2022
KernelVersion: 5.20
Contact: fkassabri@habana.ai
Description: Dumps all razwi events to dmesg if exist.
After reading the status register of an existing event
the routine will clear the status register.
Usage: cat dump_razwi_events
What: /sys/kernel/debug/habanalabs/hl<n>/dump_security_violations
Date: Jan 2021
KernelVersion: 5.12
@@ -121,14 +130,16 @@ Date: Jan 2019
KernelVersion: 5.1
Contact: ogabbay@kernel.org
Description: Sets I2C device address for I2C transaction that is generated
by the device's CPU
by the device's CPU, Not available when device is loaded with secured
firmware
What: /sys/kernel/debug/habanalabs/hl<n>/i2c_bus
Date: Jan 2019
KernelVersion: 5.1
Contact: ogabbay@kernel.org
Description: Sets I2C bus address for I2C transaction that is generated by
the device's CPU
the device's CPU, Not available when device is loaded with secured
firmware
What: /sys/kernel/debug/habanalabs/hl<n>/i2c_data
Date: Jan 2019
@@ -136,39 +147,45 @@ KernelVersion: 5.1
Contact: ogabbay@kernel.org
Description: Triggers an I2C transaction that is generated by the device's
CPU. Writing to this file generates a write transaction while
reading from the file generates a read transaction
reading from the file generates a read transaction, Not available
when device is loaded with secured firmware
What: /sys/kernel/debug/habanalabs/hl<n>/i2c_len
Date: Dec 2021
KernelVersion: 5.17
Contact: obitton@habana.ai
Description: Sets I2C length in bytes for I2C transaction that is generated by
the device's CPU
the device's CPU, Not available when device is loaded with secured
firmware
What: /sys/kernel/debug/habanalabs/hl<n>/i2c_reg
Date: Jan 2019
KernelVersion: 5.1
Contact: ogabbay@kernel.org
Description: Sets I2C register id for I2C transaction that is generated by
the device's CPU
the device's CPU, Not available when device is loaded with secured
firmware
What: /sys/kernel/debug/habanalabs/hl<n>/led0
Date: Jan 2019
KernelVersion: 5.1
Contact: ogabbay@kernel.org
Description: Sets the state of the first S/W led on the device
Description: Sets the state of the first S/W led on the device, Not available
when device is loaded with secured firmware
What: /sys/kernel/debug/habanalabs/hl<n>/led1
Date: Jan 2019
KernelVersion: 5.1
Contact: ogabbay@kernel.org
Description: Sets the state of the second S/W led on the device
Description: Sets the state of the second S/W led on the device, Not available
when device is loaded with secured firmware
What: /sys/kernel/debug/habanalabs/hl<n>/led2
Date: Jan 2019
KernelVersion: 5.1
Contact: ogabbay@kernel.org
Description: Sets the state of the third S/W led on the device
Description: Sets the state of the third S/W led on the device, Not available
when device is loaded with secured firmware
What: /sys/kernel/debug/habanalabs/hl<n>/memory_scrub
Date: May 2022
@@ -182,7 +199,8 @@ Date: May 2022
KernelVersion: 5.19
Contact: dhirschfeld@habana.ai
Description: The value to which the dram will be set to when the user
scrubs the dram using 'memory_scrub' debugfs file
scrubs the dram using 'memory_scrub' debugfs file and
the scrubbing value when using module param 'memory_scrub'
What: /sys/kernel/debug/habanalabs/hl<n>/mmu
Date: Jan 2019
@@ -277,7 +295,7 @@ Description: Displays a list with information about the currently user
to DMA addresses
What: /sys/kernel/debug/habanalabs/hl<n>/userptr_lookup
Date: Aug 2021
Date: Oct 2021
KernelVersion: 5.15
Contact: ogabbay@kernel.org
Description: Allows to search for specific user pointers (user virtual

8
Documentation/ABI/testing/sysfs-bus-iio
View File

@@ -79,6 +79,11 @@ Description:
* "accel-base"
* "accel-display"
For devices where an accelerometer is housed in the swivel camera subassembly
(for AR application), the following standardized label is used:
* "accel-camera"
What: /sys/bus/iio/devices/iio:deviceX/current_timestamp_clock
KernelVersion: 4.5
Contact: linux-iio@vger.kernel.org
@@ -102,6 +107,9 @@ Description:
relevant directories. If it affects all of the above
then it is to be found in the base device directory.
The stm32-timer-trigger has the additional characteristic that
a sampling_frequency of 0 is defined to stop sampling.
What: /sys/bus/iio/devices/iio:deviceX/sampling_frequency_available
What: /sys/bus/iio/devices/iio:deviceX/in_intensity_sampling_frequency_available
What: /sys/bus/iio/devices/iio:deviceX/in_proximity_sampling_frequency_available

1
Documentation/ABI/testing/sysfs-bus-iio-sx9324
View File

@@ -5,6 +5,7 @@ Contact: Gwendal Grignou <gwendal@chromium.org>
Description:
SX9324 has 3 inputs, CS0, CS1 and CS2. Hardware layout
defines if the input is
+ not connected (HZ),
+ grounded (GD),
+ connected to an antenna where it can act as a base

31
Documentation/ABI/testing/sysfs-bus-iio-temperature-max31856
View File

@@ -1,31 +0,0 @@
What: /sys/bus/iio/devices/iio:deviceX/fault_oc
KernelVersion: 5.1
Contact: linux-iio@vger.kernel.org
Description:
Open-circuit fault. The detection of open-circuit faults,
such as those caused by broken thermocouple wires.
Reading returns either '1' or '0'.
=== =======================================================
'1' An open circuit such as broken thermocouple wires
has been detected.
'0' No open circuit or broken thermocouple wires are detected
=== =======================================================
What: /sys/bus/iio/devices/iio:deviceX/fault_ovuv
KernelVersion: 5.1
Contact: linux-iio@vger.kernel.org
Description:
Overvoltage or Undervoltage Input Fault. The internal circuitry
is protected from excessive voltages applied to the thermocouple
cables by integrated MOSFETs at the T+ and T- inputs, and the
BIAS output. These MOSFETs turn off when the input voltage is
negative or greater than VDD.
Reading returns either '1' or '0'.
=== =======================================================
'1' The input voltage is negative or greater than VDD.
'0' The input voltage is positive and less than VDD (normal
state).
=== =======================================================

20
Documentation/ABI/testing/sysfs-bus-iio-temperature-max31865
View File

@@ -1,20 +0,0 @@
What: /sys/bus/iio/devices/iio:deviceX/fault_ovuv
KernelVersion: 5.11
Contact: linux-iio@vger.kernel.org
Description:
Overvoltage or Undervoltage Input fault. The internal circuitry
is protected from excessive voltages applied to the thermocouple
cables at FORCE+, FORCE2, RTDIN+ & RTDIN-. This circuitry turn
off when the input voltage is negative or greater than VDD.
Reading returns '1' if input voltage is negative or greater
than VDD, otherwise '0'.
What: /sys/bus/iio/devices/iio:deviceX/in_filter_notch_center_frequency
KernelVersion: 5.11
Contact: linux-iio@vger.kernel.org
Description:
Notch frequency in Hz for a noise rejection filter. Used i.e for
line noise rejection.
Valid notch filter values are 50 Hz and 60 Hz.

18
Documentation/ABI/testing/sysfs-bus-iio-thermocouple Normal file
View File

@@ -0,0 +1,18 @@
What: /sys/bus/iio/devices/iio:deviceX/fault_ovuv
KernelVersion: 5.1
Contact: linux-iio@vger.kernel.org
Description:
Overvoltage or Undervoltage Input Fault. The internal circuitry
is protected from excessive voltages applied to the thermocouple
cables. The device can also detect if such a condition occurs.
Reading returns '1' if input voltage is negative or greater
than VDD, otherwise '0'.
What: /sys/bus/iio/devices/iio:deviceX/fault_oc
KernelVersion: 5.1
Contact: linux-iio@vger.kernel.org
Description:
Open-circuit fault. The detection of open-circuit faults,
such as those caused by broken thermocouple wires.
Reading returns '1' if fault, '0' otherwise.

8
Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
View File

@@ -90,14 +90,6 @@ Description:
Reading returns the current master modes.
Writing set the master mode
What: /sys/bus/iio/devices/triggerX/sampling_frequency
KernelVersion: 4.11
Contact: benjamin.gaignard@st.com
Description:
Reading returns the current sampling frequency.
Writing an value different of 0 set and start sampling.
Writing 0 stop sampling.
What: /sys/bus/iio/devices/iio:deviceX/in_count0_preset
KernelVersion: 4.12
Contact: benjamin.gaignard@st.com

33
Documentation/ABI/testing/sysfs-class-vduse Normal file
View File

@@ -0,0 +1,33 @@
What: /sys/class/vduse/
Date: Oct 2021
KernelVersion: 5.15
Contact: Yongji Xie <xieyongji@bytedance.com>
Description:
The vduse/ class sub-directory belongs to the VDUSE
framework and provides a sysfs interface for configuring
VDUSE devices.
What: /sys/class/vduse/control/
Date: Oct 2021
KernelVersion: 5.15
Contact: Yongji Xie <xieyongji@bytedance.com>
Description:
This directory entry is created for the control device
of VDUSE framework.
What: /sys/class/vduse/<device-name>/
Date: Oct 2021
KernelVersion: 5.15
Contact: Yongji Xie <xieyongji@bytedance.com>
Description:
This directory entry is created when a VDUSE device is
created via the control device.
What: /sys/class/vduse/<device-name>/msg_timeout
Date: Oct 2021
KernelVersion: 5.15
Contact: Yongji Xie <xieyongji@bytedance.com>
Description:
(RW) The timeout (in seconds) for waiting for the control
message's response from userspace. Default value is 30s.
Writing a '0' to the file means to disable the timeout.

61
Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update Normal file
View File

@@ -0,0 +1,61 @@
What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/sr_root_entry_hash
Date: Sep 2022
KernelVersion: 5.20
Contact: Russ Weight <russell.h.weight@intel.com>
Description: Read only. Returns the root entry hash for the static
region if one is programmed, else it returns the
string: "hash not programmed". This file is only
visible if the underlying device supports it.
Format: string.
What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/pr_root_entry_hash
Date: Sep 2022
KernelVersion: 5.20
Contact: Russ Weight <russell.h.weight@intel.com>
Description: Read only. Returns the root entry hash for the partial
reconfiguration region if one is programmed, else it
returns the string: "hash not programmed". This file
is only visible if the underlying device supports it.
Format: string.
What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/bmc_root_entry_hash
Date: Sep 2022
KernelVersion: 5.20
Contact: Russ Weight <russell.h.weight@intel.com>
Description: Read only. Returns the root entry hash for the BMC image
if one is programmed, else it returns the string:
"hash not programmed". This file is only visible if the
underlying device supports it.
Format: string.
What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/sr_canceled_csks
Date: Sep 2022
KernelVersion: 5.20
Contact: Russ Weight <russell.h.weight@intel.com>
Description: Read only. Returns a list of indices for canceled code
signing keys for the static region. The standard bitmap
list format is used (e.g. "1,2-6,9").
What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/pr_canceled_csks
Date: Sep 2022
KernelVersion: 5.20
Contact: Russ Weight <russell.h.weight@intel.com>
Description: Read only. Returns a list of indices for canceled code
signing keys for the partial reconfiguration region. The
standard bitmap list format is used (e.g. "1,2-6,9").
What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/bmc_canceled_csks
Date: Sep 2022
KernelVersion: 5.20
Contact: Russ Weight <russell.h.weight@intel.com>
Description: Read only. Returns a list of indices for canceled code
signing keys for the BMC. The standard bitmap list format
is used (e.g. "1,2-6,9").
What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/flash_count
Date: Sep 2022
KernelVersion: 5.20
Contact: Russ Weight <russell.h.weight@intel.com>
Description: Read only. Returns number of times the secure update
staging area has been flashed.
Format: "%u".

101
Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml Normal file
View File

@@ -0,0 +1,101 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm Coresight Address Translation Unit (CATU)
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The CoreSight Address Translation Unit (CATU) translates addresses between an
AXI master and system memory. The CATU is normally used along with the TMC to
implement scattering of virtual trace buffers in physical memory. The CATU
translates contiguous Virtual Addresses (VAs) from an AXI master into
non-contiguous Physical Addresses (PAs) that are intended for system memory.
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
const: arm,coresight-catu
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-catu
- const: arm,primecell
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
interrupts:
maxItems: 1
description: Address translation error interrupt
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: AXI Slave connected to another Coresight component
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
catu@207e0000 {
compatible = "arm,coresight-catu", "arm,primecell";
reg = <0x207e0000 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
in-ports {
port {
catu_in_port: endpoint {
remote-endpoint = <&etr_out_port>;
};
};
};
};
...

81
Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml Normal file
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@@ -0,0 +1,81 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: CoreSight CPU Debug Component
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight CPU debug component are compliant with the ARMv8 architecture
reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
external debug module is mainly used for two modes: self-hosted debug and
external debug, and it can be accessed from mmio region from Coresight and
eventually the debug module connects with CPU for debugging. And the debug
module provides sample-based profiling extension, which can be used to sample
CPU program counter, secure state and exception level, etc; usually every CPU
has one dedicated debug module to be connected.
select:
properties:
compatible:
contains:
const: arm,coresight-cpu-debug
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-cpu-debug
- const: arm,primecell
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
maxItems: 1
cpu:
description:
A phandle to the cpu this debug component is bound to.
$ref: /schemas/types.yaml#/definitions/phandle
power-domains:
maxItems: 1
description:
A phandle to the debug power domain if the debug logic has its own
dedicated power domain. CPU idle states may also need to be separately
constrained to keep CPU cores powered.
required:
- compatible
- reg
- clocks
- clock-names
- cpu
unevaluatedProperties: false
examples:
- |
debug@f6590000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0xf6590000 0x1000>;
clocks = <&sys_ctrl 1>;
clock-names = "apb_pclk";
cpu = <&cpu0>;
};
...

5
Documentation/devicetree/bindings/arm/coresight-cti.yaml → Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml
View File

@@ -2,7 +2,7 @@
# Copyright 2019 Linaro Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/coresight-cti.yaml#
$id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Coresight Cross Trigger Interface (CTI) device.
@@ -12,8 +12,7 @@ description: |
to one or more CoreSight components and/or a CPU, with CTIs interconnected in
a star topology via the Cross Trigger Matrix (CTM), which is not programmable.
The ECT components are not part of the trace generation data path and are thus
not part of the CoreSight graph described in the general CoreSight bindings
file coresight.txt.
not part of the CoreSight graph.
The CTI component properties define the connections between the individual
CTI and the components it is directly connected to, consisting of input and

126
Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml Normal file
View File

@@ -0,0 +1,126 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-dynamic-funnel.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Programmable Trace Bus Funnel
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The Coresight funnel merges 2-8 trace sources into a single trace
stream with programmable enable and priority of input ports.
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
const: arm,coresight-dynamic-funnel
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-dynamic-funnel
- const: arm,primecell
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
patternProperties:
'^port(@[0-7])?$':
description: Input connections from CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Output connection to CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
- out-ports
unevaluatedProperties: false
examples:
- |
funnel@20040000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x20040000 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
out-ports {
port {
funnel_out_port0: endpoint {
remote-endpoint = <&replicator_in_port0>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_in_port0: endpoint {
remote-endpoint = <&ptm0_out_port>;
};
};
port@1 {
reg = <1>;
funnel_in_port1: endpoint {
remote-endpoint = <&ptm1_out_port>;
};
};
port@2 {
reg = <2>;
funnel_in_port2: endpoint {
remote-endpoint = <&etm0_out_port>;
};
};
};
};
...

126
Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml Normal file
View File

@@ -0,0 +1,126 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-dynamic-replicator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm Coresight Programmable Trace Bus Replicator
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The Coresight replicator splits a single trace stream into two trace streams
for systems that have more than one trace sink component.
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
const: arm,coresight-dynamic-replicator
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-dynamic-replicator
- const: arm,primecell
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
qcom,replicator-loses-context:
type: boolean
description:
Indicates that the replicator will lose register context when AMBA clock
is removed which is observed in some replicator designs.
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Input connection from CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
patternProperties:
'^port(@[01])?$':
description: Output connections to CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
- out-ports
unevaluatedProperties: false
examples:
- |
replicator@20120000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x20120000 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
out-ports {
#address-cells = <1>;
#size-cells = <0>;
/* replicator output ports */
port@0 {
reg = <0>;
replicator_out_port0: endpoint {
remote-endpoint = <&tpiu_in_port>;
};
};
port@1 {
reg = <1>;
replicator_out_port1: endpoint {
remote-endpoint = <&etr_in_port>;
};
};
};
in-ports {
port {
replicator_in_port0: endpoint {
remote-endpoint = <&csys2_funnel_out_port>;
};
};
};
};
...

92
Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-etb10.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Embedded Trace Buffer
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The CoreSight Embedded Trace Buffer stores traces in a dedicated SRAM that is
used as a circular buffer.
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
const: arm,coresight-etb10
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-etb10
- const: arm,primecell
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Input connection from CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
unevaluatedProperties: false
examples:
- |
etb@20010000 {
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0x20010000 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
in-ports {
port {
etb_in_port: endpoint {
remote-endpoint = <&replicator_out_port0>;
};
};
};
};
...

156
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-etm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Embedded Trace MacroCell
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The Embedded Trace Macrocell (ETM) is a real-time trace module providing
instruction and data tracing of a processor.
select:
properties:
compatible:
contains:
enum:
- arm,coresight-etm3x
- arm,coresight-etm4x
- arm,coresight-etm4x-sysreg
required:
- compatible
allOf:
- if:
not:
properties:
compatible:
contains:
const: arm,coresight-etm4x-sysreg
then:
$ref: /schemas/arm/primecell.yaml#
required:
- reg
properties:
compatible:
oneOf:
- description:
Embedded Trace Macrocell with memory mapped access.
items:
- enum:
- arm,coresight-etm3x
- arm,coresight-etm4x
- const: arm,primecell
- description:
Embedded Trace Macrocell (version 4.x), with system register access only
const: arm,coresight-etm4x-sysreg
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
arm,coresight-loses-context-with-cpu:
type: boolean
description:
Indicates that the hardware will lose register context on CPU power down
(e.g. CPUIdle). An example of where this may be needed are systems which
contain a coresight component and CPU in the same power domain. When the
CPU powers down the coresight component also powers down and loses its
context.
arm,cp14:
type: boolean
description:
Must be present if the system accesses ETM/PTM management registers via
co-processor 14.
qcom,skip-power-up:
type: boolean
description:
Indicates that an implementation can skip powering up the trace unit.
TRCPDCR.PU does not have to be set on Qualcomm Technologies Inc. systems
since ETMs are in the same power domain as their CPU cores. This property
is required to identify such systems with hardware errata where the CPU
watchdog counter is stopped when TRCPDCR.PU is set.
cpu:
description:
phandle to the cpu this ETM is bound to.
$ref: /schemas/types.yaml#/definitions/phandle
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Output connection from the ETM to CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- clocks
- clock-names
- cpu
- out-ports
unevaluatedProperties: false
examples:
- |
ptm@2201c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x2201c000 0x1000>;
cpu = <&cpu0>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
out-ports {
port {
ptm0_out_port: endpoint {
remote-endpoint = <&funnel_in_port0>;
};
};
};
};
ptm@2201d000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x2201d000 0x1000>;
cpu = <&cpu1>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
out-ports {
port {
ptm1_out_port: endpoint {
remote-endpoint = <&funnel_in_port1>;
};
};
};
};
...

90
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-static-funnel.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Static Trace Bus Funnel
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The Coresight static funnel merges 2-8 trace sources into a single trace
stream.
properties:
compatible:
const: arm,coresight-static-funnel
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
patternProperties:
'^port@[0-7]$':
description: Input connections from CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Output connection to CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- in-ports
- out-ports
additionalProperties: false
examples:
- |
funnel {
/*
* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-static-funnel";
out-ports {
port {
combo_funnel_out: endpoint {
remote-endpoint = <&top_funnel_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
combo_funnel_in0: endpoint {
remote-endpoint = <&cluster0_etf_out>;
};
};
port@1 {
reg = <1>;
combo_funnel_in1: endpoint {
remote-endpoint = <&cluster1_etf_out>;
};
};
};
};
...

91
Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-static-replicator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Static Trace Bus Replicator
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The Coresight replicator splits a single trace stream into two trace streams
for systems that have more than one trace sink component.
properties:
compatible:
const: arm,coresight-static-replicator
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Input connection from CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
patternProperties:
'^port@[01]$':
description: Output connections to CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- in-ports
- out-ports
additionalProperties: false
examples:
- |
replicator {
/*
* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-static-replicator";
out-ports {
#address-cells = <1>;
#size-cells = <0>;
/* replicator output ports */
port@0 {
reg = <0>;
replicator_out_port0: endpoint {
remote-endpoint = <&etb_in_port>;
};
};
port@1 {
reg = <1>;
replicator_out_port1: endpoint {
remote-endpoint = <&tpiu_in_port>;
};
};
};
in-ports {
port {
replicator_in_port0: endpoint {
remote-endpoint = <&funnel_out_port0>;
};
};
};
};
...

101
Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight System Trace MacroCell
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The STM is a trace source that is integrated into a CoreSight system, designed
primarily for high-bandwidth trace of instrumentation embedded into software.
This instrumentation is made up of memory-mapped writes to the STM Advanced
eXtensible Interface (AXI) slave, which carry information about the behavior
of the software.
select:
properties:
compatible:
contains:
const: arm,coresight-stm
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-stm
- const: arm,primecell
reg:
maxItems: 2
reg-names:
items:
- const: stm-base
- const: stm-stimulus-base
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Output connection to the CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- out-ports
unevaluatedProperties: false
examples:
- |
stm@20100000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x20100000 0x1000>,
<0x28000000 0x180000>;
reg-names = "stm-base", "stm-stimulus-base";
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
out-ports {
port {
stm_out_port: endpoint {
remote-endpoint = <&main_funnel_in_port2>;
};
};
};
};
...

131
Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Trace Memory Controller
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
Trace Memory Controller is used for Embedded Trace Buffer(ETB), Embedded Trace
FIFO(ETF) and Embedded Trace Router(ETR) configurations. The configuration
mode (ETB, ETF, ETR) is discovered at boot time when the device is probed.
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
const: arm,coresight-tmc
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-tmc
- const: arm,primecell
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
arm,buffer-size:
$ref: /schemas/types.yaml#/definitions/uint32
deprecated: true
description:
Size of contiguous buffer space for TMC ETR (embedded trace router). The
buffer size can be configured dynamically via buffer_size property in
sysfs instead.
arm,scatter-gather:
type: boolean
description:
Indicates that the TMC-ETR can safely use the SG mode on this system.
arm,max-burst-size:
description:
The maximum burst size initiated by TMC on the AXI master interface. The
burst size can be in the range [0..15], the setting supports one data
transfer per burst up to a maximum of 16 data transfers per burst.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Input connection from the CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: AXI or ATB Master output connection. Used for ETR
and ETF configurations.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
unevaluatedProperties: false
examples:
- |
etr@20070000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x20070000 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
in-ports {
port {
etr_in_port: endpoint {
remote-endpoint = <&replicator2_out_port0>;
};
};
};
out-ports {
port {
etr_out_port: endpoint {
remote-endpoint = <&catu_in_port>;
};
};
};
};
...

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