ASoC: codecs: add aw882xx amp

Change-Id: Ia1249aa8971f6e7dee58858343ea56454862601c
Signed-off-by: Shunhua Lan <lsh@rock-chips.com>

sound/soc/codecs/Kconfig

@@ -2272,6 +2272,7 @@ config SND_SOC_LPASS_TX_MACRO
 	tristate "Qualcomm TX Macro in LPASS(Low Power Audio SubSystem)"
 
 source "sound/soc/codecs/aw87xxx/Kconfig"
+source "sound/soc/codecs/aw882xx/Kconfig"
 source "sound/soc/codecs/aw883xx/Kconfig"
 source "sound/soc/codecs/it6621/Kconfig"
 endmenu

sound/soc/codecs/Makefile

@@ -746,6 +746,7 @@ obj-$(CONFIG_SND_SOC_ZL38060)	+= snd-soc-zl38060.o
 
 # Amp
 obj-$(CONFIG_SND_SOC_AW87XXX)	+= aw87xxx/
+obj-$(CONFIG_SND_SOC_AW882XX)	+= aw882xx/
 obj-$(CONFIG_SND_SOC_AW883XX)	+= aw883xx/
 obj-$(CONFIG_SND_SOC_IT6621)	+= it6621/
 obj-$(CONFIG_SND_SOC_MAX9877)	+= snd-soc-max9877.o

sound/soc/codecs/aw882xx/Kconfig

@@ -0,0 +1,5 @@
+config SND_SOC_AW882XX
+	tristate "SoC Audio for awinic AW883XX series Smart PA"
+	depends on I2C
+	help
+	  This option enables support for AW883XX series Smart PA.

sound/soc/codecs/aw882xx/Makefile

@@ -0,0 +1,5 @@
+#for AWINIC AW883XX Smart PA
+snd-soc-aw882xx-objs := aw882xx.o aw882xx_device.o aw882xx_dsp.o aw882xx_monitor.o aw882xx_bin_parse.o aw882xx_init.o aw882xx_calib.o aw882xx_spin.o
+obj-$(CONFIG_SND_SOC_AW882XX) += snd-soc-aw882xx.o
+
+

sound/soc/codecs/aw882xx/aw882xx.h

@@ -0,0 +1,223 @@
+/* SPDX-License-Identifier: GPL-2.0
+ * aw882xx.h
+ *
+ * Copyright (c) 2020 AWINIC Technology CO., LTD
+ *
+ * Author: Nick Li <liweilei@awinic.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef _AW882XX_H_
+#define _AW882XX_H_
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include "aw882xx_device.h"
+
+/*
+ * i2c transaction on Linux limited to 64k
+ * (See Linux kernel documentation: Documentation/i2c/writing-clients)
+ */
+#define AW882XX_CHIP_ID_REG (0x00)
+#define MAX_I2C_BUFFER_SIZE					65536
+#define AW882XX_I2C_READ_MSG_NUM		2
+#define AW882XX_DC_DELAY_TIME	(1000)
+#define AW882XX_LOAD_FW_DELAY_TIME	(0)
+#define AW_START_RETRIES	(5)
+
+#define AW_PID_2055_VERSION_DIFF_REG	(0x23)
+
+#define AW_I2C_RETRIES			5	/* 5 times */
+#define AW_I2C_RETRY_DELAY		5	/* 5 ms */
+
+#define ACF_BIN_NAME	"aw882xx_acf.bin"
+
+#define AW882XX_RATES SNDRV_PCM_RATE_8000_48000
+#define AW882XX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
+						SNDRV_PCM_FMTBIT_S24_LE | \
+						SNDRV_PCM_FMTBIT_S32_LE)
+/*#define AW882XX_IRQ_START_FLAG*/
+enum {
+	AW882XX_STREAM_CLOSE = 0,
+	AW882XX_STREAM_OPEN,
+};
+
+enum aw882xx_chipid {
+	PID_1852_ID = 0x1852,
+	PID_2013_ID = 0x2013,
+	PID_2032_ID = 0x2032,
+	PID_2055_ID = 0x2055,
+	PID_2055A_ID = 0x2055A,
+	PID_2071_ID = 0x2071,
+	PID_2113_ID = 0x2113,
+	PID_2308_ID = 0x2308,
+};
+
+#define AW882XX_SOFT_RESET_REG		(0x00)
+#define AW882XX_SOFT_RESET_VALUE	(0x55aa)
+
+enum aw882xx_int_type {
+	INT_TYPE_NONE = 0,
+	INT_TYPE_UVLO = 0x1,
+	INT_TYPE_BSTOC = 0x2,
+	INT_TYPE_OCDI = 0x4,
+	INT_TYPE_OTHI = 0x8,
+};
+
+#if KERNEL_VERSION(4, 19, 1) <= LINUX_VERSION_CODE
+#define AW_KERNEL_VER_OVER_4_19_1
+#endif
+
+
+#if KERNEL_VERSION(5, 4, 0) <= LINUX_VERSION_CODE
+#define AW_KERNEL_VER_OVER_5_4_0
+MODULE_IMPORT_NS(VFS_internal_I_am_really_a_filesystem_and_am_NOT_a_driver);
+#endif
+
+#if KERNEL_VERSION(5, 10, 0) <= LINUX_VERSION_CODE
+#define AW_KERNEL_VER_OVER_5_10_0
+#endif
+#if KERNEL_VERSION(6, 1, 0) <= LINUX_VERSION_CODE
+#define AW_KERNEL_VER_OVER_6_1_0
+#endif
+
+
+#ifdef AW_KERNEL_VER_OVER_4_19_1
+typedef struct snd_soc_component aw_snd_soc_codec_t;
+typedef const struct snd_soc_component_driver aw_snd_soc_codec_driver_t;
+#else
+typedef struct snd_soc_codec aw_snd_soc_codec_t;
+typedef const struct snd_soc_codec_driver aw_snd_soc_codec_driver_t;
+#endif
+
+struct aw_componet_codec_ops {
+	aw_snd_soc_codec_t *(*kcontrol_codec)(struct snd_kcontrol *kcontrol);
+	void *(*codec_get_drvdata)(aw_snd_soc_codec_t *codec);
+	int (*add_codec_controls)(aw_snd_soc_codec_t *codec,
+		const struct snd_kcontrol_new *controls, unsigned int num_controls);
+	void (*unregister_codec)(struct device *dev);
+	int (*register_codec)(struct device *dev,
+			const aw_snd_soc_codec_driver_t *codec_drv,
+			struct snd_soc_dai_driver *dai_drv,
+			int num_dai);
+};
+
+enum {
+	AWRW_I2C_ST_NONE = 0,
+	AWRW_I2C_ST_READ,
+	AWRW_I2C_ST_WRITE,
+};
+
+#define AWRW_ADDR_BYTES (1)
+#define AWRW_DATA_BYTES (2)
+#define AWRW_HDR_LEN (24)
+
+
+enum {
+	KCTL_TYPE_PROFILE = 0,
+	KCTL_TYPE_SWITCH,
+	KCTL_TYPE_MONITOR,
+	KCTL_TYPE_VOLUME,
+	KCTL_TYPE_MON_HAL,
+	AW_KCTL_NUM,
+
+};
+
+enum {
+	AWRW_FLAG_WRITE = 0,
+	AWRW_FLAG_READ,
+};
+
+enum {
+	AW_BSTCFG_DISABLE = 0,
+	AW_BSTCFG_ENABLE,
+};
+
+enum {
+	AW_FRCSET_DISABLE = 0,
+	AW_FRCSET_ENABLE,
+};
+
+enum {
+	AW_BOP_DISABLE = 0,
+	AW_BOP_ENABLE,
+};
+
+enum {
+	AW_RENAME_DISABLE = 0,
+	AW_RENAME_ENABLE,
+};
+
+enum {
+	AWRW_HDR_WR_FLAG = 0,
+	AWRW_HDR_ADDR_BYTES,
+	AWRW_HDR_DATA_BYTES,
+	AWRW_HDR_REG_NUM,
+	AWRW_HDR_REG_ADDR,
+	AWRW_HDR_MAX,
+};
+
+struct aw882xx_i2c_packet {
+	char status;
+	unsigned int reg_num;
+	unsigned int reg_addr;
+	char *reg_data;
+};
+
+/********************************************
+ * struct aw882xx
+ *******************************************/
+struct aw882xx {
+	int sysclk;
+	int rate;
+	int pstream;
+	int cstream;
+
+	unsigned char phase_sync;	/* phase sync */
+	unsigned char dc_flag;
+	unsigned char dbg_en_prof;	/* debug enable/disable profile function */
+	unsigned char allow_pw;		/* allow power */
+	uint32_t rename_flag;
+	unsigned char sync_load;	/* sync load fw */
+
+	int reset_gpio;
+	int irq_gpio;
+	unsigned char fw_status;
+	unsigned char fw_retry_cnt;
+	unsigned char rw_reg_addr;	/* rw attr node store read addr */
+
+	aw_snd_soc_codec_t *codec;
+	struct aw_componet_codec_ops *codec_ops;
+
+	struct i2c_client *i2c;
+	struct device *dev;
+	struct aw882xx_i2c_packet i2c_packet;
+	struct aw_device *aw_pa;
+
+	struct workqueue_struct *work_queue;
+	struct delayed_work start_work;
+	struct delayed_work interrupt_work;
+	struct delayed_work dc_work;
+	struct delayed_work fw_work;
+
+	struct mutex lock;
+};
+
+void aw882xx_kcontorl_set(struct aw882xx *aw882xx);
+int aw882xx_get_version(char *buf, int size);
+int aw882xx_get_dev_num(void);
+int aw882xx_i2c_write(struct aw882xx *aw882xx,
+	unsigned char reg_addr, unsigned int reg_data);
+int aw882xx_i2c_read(struct aw882xx *aw882xx,
+	unsigned char reg_addr, unsigned int *reg_data);
+int aw882xx_i2c_write_bits(struct aw882xx *aw882xx,
+	unsigned char reg_addr, unsigned int mask, unsigned int reg_data);
+int aw882xx_init(struct aw882xx *aw882xx);
+int aw882xx_hw_reset(struct aw882xx *aw882xx);
+
+
+#endif
+

sound/soc/codecs/aw882xx/aw882xx_bin_parse.h

@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0
+ * aw882xx_bin_parse.h
+ *
+ * Copyright (c) 2020 AWINIC Technology CO., LTD
+ *
+ * Author: Nick Li <liweilei@awinic.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __AW882XX_BIN_PARSE_H__
+#define __AW882XX_BIN_PARSE_H__
+
+#include "aw882xx_device.h"
+
+#define NULL    ((void *)0)
+#define GET_32_DATA(w, x, y, z) ((unsigned int)((((uint32_t)w) << 24) | (((uint32_t)x) << 16) | (((uint32_t)y) << 8) | ((uint32_t)z)))
+#define BIN_NUM_MAX   100
+#define HEADER_LEN    60
+/*********************************************************
+ *
+ * header information
+ *
+ ********************************************************/
+enum bin_header_version_enum {
+	HEADER_VERSION_1_0_0 = 0x01000000,
+};
+
+enum data_type_enum {
+	DATA_TYPE_REGISTER = 0x00000000,
+	DATA_TYPE_DSP_REG = 0x00000010,
+	DATA_TYPE_DSP_CFG = 0x00000011,
+	DATA_TYPE_SOC_REG = 0x00000020,
+	DATA_TYPE_SOC_APP = 0x00000021,
+	DATA_TYPE_MULTI_BINS = 0x00002000,
+};
+
+enum data_version_enum {
+	DATA_VERSION_V1 = 0X00000001,	/*default little edian */
+	DATA_VERSION_MAX,
+};
+
+struct bin_header_info {
+	unsigned int header_len; /* Frame header length */
+	unsigned int check_sum; /* Frame header information-Checksum */
+	unsigned int header_ver; /* Frame header information-Frame header version */
+	unsigned int bin_data_type; /* Frame header information-Data type */
+	unsigned int bin_data_ver; /* Frame header information-Data version */
+	unsigned int bin_data_len; /* Frame header information-Data length */
+	unsigned int ui_ver; /* Frame header information-ui version */
+	unsigned char chip_type[8]; /* Frame header information-chip type */
+	unsigned int reg_byte_len; /* Frame header information-reg byte len */
+	unsigned int data_byte_len; /* Frame header information-data byte len */
+	unsigned int device_addr; /* Frame header information-device addr */
+	unsigned int valid_data_len; /* Length of valid data obtained after parsing */
+	unsigned int valid_data_addr; /* The offset address of the valid data obtained after parsing relative to info */
+
+	unsigned int reg_num; /* The number of registers obtained after parsing */
+	unsigned int reg_data_byte_len; /* The byte length of the register obtained after parsing */
+	unsigned int download_addr; /* The starting address or download address obtained after parsing */
+	unsigned int app_version; /* The software version number obtained after parsing */
+};
+
+/************************************************************
+ *
+ * function define
+ *
+ ************************************************************/
+struct bin_container {
+	unsigned int len; /* The size of the bin file obtained from the firmware */
+	unsigned char data[]; /* Store the bin file obtained from the firmware */
+};
+
+struct aw_bin {
+	unsigned char *p_addr; /* Offset pointer (backward offset pointer to obtain frame header information and important information) */
+	unsigned int all_bin_parse_num; /* The number of all bin files */
+	unsigned int multi_bin_parse_num; /* The number of single bin files */
+	unsigned int single_bin_parse_num; /* The number of multiple bin files */
+	struct bin_header_info header_info[BIN_NUM_MAX]; /* Frame header information and other important data obtained after parsing */
+	struct bin_container info; /* Obtained bin file data that needs to be parsed */
+};
+
+
+/*******************awinic audio parse acf***********************/
+
+int aw882xx_dev_parse_check_acf(struct aw_container *aw_cfg);
+int aw882xx_dev_parse_acf(struct aw_device *aw_dev, struct aw_container *aw_cfg);
+
+
+int aw882xx_dev_get_profile_count(struct aw_device *aw_dev);
+int aw88xx_dev_get_profile_name(struct aw_device *aw_dev, char *name, int index);
+int aw882xx_dev_check_profile_index(struct aw_device *aw_dev, int index);
+int aw882xx_dev_get_profile_index(struct aw_device *aw_dev);
+int aw882xx_dev_set_profile_index(struct aw_device *aw_dev, int index);
+char *aw882xx_dev_get_prof_name(struct aw_device *aw_dev, int index);
+struct aw_sec_data_desc *aw882xx_dev_get_prof_data(struct aw_device *aw_dev, int index, int data_type);
+
+
+#endif

sound/soc/codecs/aw882xx/aw882xx_calib.h

@@ -0,0 +1,193 @@
+/* SPDX-License-Identifier: GPL-2.0
+ * aw882xx_calib.h
+ *
+ * Copyright (c) 2020 AWINIC Technology CO., LTD
+ *
+ * Author: Nick Li <liweilei@awinic.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __AW882XX_CALIBRATION_H__
+#define __AW882XX_CALIBRATION_H__
+
+#define AW_CALI_READ_RE_TIMES (8)
+#define AW_CALI_READ_F0_Q_TIMES (5)
+#define AW_ERRO_CALI_VALUE (0)
+#define AW_CALI_RE_DEFAULT_TIMER	(3000)
+
+#define AW_CALI_RE_MAX     (15000)
+#define AW_CALI_RE_MIN     (4000)
+
+#define AW_CALI_CFG_NUM (3)
+#define AW_CALI_DATA_NUM (6)
+#define AW_PARAMS_NUM (600)
+#define AW_KILO_PARAMS_NUM (1000)
+
+#define AW_CALI_RE_DEFAULT_MAX		(50000)
+#define AW_CALI_RE_DEFAULT_MIN		(1000)
+
+#define AW_DEV_RE_RANGE	(RE_RANGE_NUM * AW_DEV_CH_MAX)
+
+struct aw_device;
+
+enum afe_module_type {
+	AW_RX_MODULE = 0,
+	AW_TX_MODULE = 1,
+};
+
+enum {
+	MSG_CALI_DISABLE_DATA = 0,
+	MSG_CALI_RE_ENABLE_DATA,
+	MSG_CALI_F0_ENABLE_DATA,
+};
+
+struct cali_cfg {
+	int32_t data[AW_CALI_CFG_NUM];
+};
+
+struct cali_data {
+	int32_t data[AW_CALI_DATA_NUM];
+};
+
+struct params_data {
+	int32_t data[AW_PARAMS_NUM];
+};
+
+struct ptr_params_data {
+	int len;
+	int32_t *data;
+};
+
+struct f0_q_data {
+	int32_t data[4];
+};
+
+enum {
+	AW_IOCTL_MSG_IOCTL = 0,
+	AW_IOCTL_MSG_RD_DSP,
+	AW_IOCTL_MSG_WR_DSP
+};
+
+enum {
+	CALI_CHECK_DISABLE = 0,
+	CALI_CHECK_ENABLE = 1,
+};
+
+enum {
+	CALI_RESULT_NONE = 0,
+	CALI_RESULT_NORMAL = 1,
+	CALI_RESULT_ERROR = -1,
+};
+
+enum {
+	RE_MIN_FLAG = 0,
+	RE_MAX_FLAG = 1,
+	RE_RANGE_NUM = 2,
+};
+
+enum {
+	CALI_DATA_RE = 0,
+	CALI_DATA_F0,
+	CALI_DATA_F0_Q,
+};
+
+struct re_data {
+	uint32_t re_range[2];
+};
+
+#define AW_IOCTL_MSG_VERSION (0)
+typedef struct {
+	int32_t type;
+	int32_t opcode_id;
+	int32_t version;
+	int32_t data_len;
+	char *data_buf;
+	int32_t reseriver[2];
+} aw_ioctl_msg_t;
+
+#define AW_IOCTL_MAGIC				'a'
+#define AW_IOCTL_SET_CALI_CFG			_IOWR(AW_IOCTL_MAGIC, 1, struct cali_cfg)
+#define AW_IOCTL_GET_CALI_CFG			_IOWR(AW_IOCTL_MAGIC, 2, struct cali_cfg)
+#define AW_IOCTL_GET_CALI_DATA			_IOWR(AW_IOCTL_MAGIC, 3, struct cali_data)
+#define AW_IOCTL_SET_NOISE			_IOWR(AW_IOCTL_MAGIC, 4, int32_t)
+#define AW_IOCTL_GET_F0				_IOWR(AW_IOCTL_MAGIC, 5, int32_t)
+#define AW_IOCTL_SET_CALI_RE			_IOWR(AW_IOCTL_MAGIC, 6, int32_t)
+#define AW_IOCTL_GET_CALI_RE			_IOWR(AW_IOCTL_MAGIC, 7, int32_t)
+#define AW_IOCTL_SET_VMAX			_IOWR(AW_IOCTL_MAGIC, 8, int32_t)
+#define AW_IOCTL_GET_VMAX			_IOWR(AW_IOCTL_MAGIC, 9, int32_t)
+#define AW_IOCTL_SET_PARAM			_IOWR(AW_IOCTL_MAGIC, 10, struct params_data)
+#define AW_IOCTL_ENABLE_CALI			_IOWR(AW_IOCTL_MAGIC, 11, int8_t)
+#define AW_IOCTL_SET_PTR_PARAM_NUM		_IOWR(AW_IOCTL_MAGIC, 12, struct ptr_params_data)
+#define AW_IOCTL_GET_F0_Q			_IOWR(AW_IOCTL_MAGIC, 13, struct f0_q_data)
+#define AW_IOCTL_SET_DSP_HMUTE			_IOWR(AW_IOCTL_MAGIC, 14, int32_t)
+#define AW_IOCTL_SET_CALI_CFG_FLAG		_IOWR(AW_IOCTL_MAGIC, 15, int32_t)
+#define AW_IOCTL_MSG				_IOWR(AW_IOCTL_MAGIC, 16, aw_ioctl_msg_t)
+#define AW_IOCTL_GET_RE_RANGE			_IOWR(AW_IOCTL_MAGIC, 17, struct re_data)
+
+enum{
+	AW_CALI_MODE_NONE = 0,
+	AW_CALI_MODE_ALL,
+	AW_CALI_MODE_MAX,
+};
+
+enum {
+	AW_CALI_CMD_RE = 0,
+	AW_CALI_CMD_F0,
+	AW_CALI_CMD_RE_F0,
+	AW_CALI_CMD_F0_Q,
+	AW_CALI_CMD_RE_F0_Q,
+};
+
+enum {
+	CALI_OPS_HMUTE = 0X0001,
+	CALI_OPS_NOISE = 0X0002,
+};
+
+enum {
+	CALI_TYPE_RE = 0,
+	CALI_TYPE_F0,
+};
+
+enum {
+	CALI_STR_NONE = 0,
+	CALI_STR_CALI_RE_F0,
+	CALI_STR_CALI_RE,
+	CALI_STR_CALI_F0,
+	CALI_STR_SET_RE,
+	CALI_STR_SHOW_RE,		/*show cali_re*/
+	CALI_STR_SHOW_R0,		/*show real r0*/
+	CALI_STR_SHOW_CALI_F0,		/*GET DEV CALI_F0*/
+	CALI_STR_SHOW_F0,		/*SHOW REAL F0*/
+	CALI_STR_SHOW_TE,
+	CALI_STR_SHOW_ST,
+	CALI_STR_DEV_SEL,		/*switch device*/
+	CALI_STR_VER,
+	CALI_STR_DEV_NUM,
+	CALI_STR_CALI_F0_Q,
+	CALI_STR_SHOW_F0_Q,
+	CALI_STR_SHOW_RE_RANGE,
+	CALI_STR_MAX,
+};
+
+struct aw_cali_desc {
+	unsigned char status;
+	unsigned char mode;		/*0:NONE 1:ATTR 2:CLASS 3:MISC */
+	int32_t cali_re;		/*set cali_re*/
+	int32_t cali_f0;		/*store cali_f0*/
+	int32_t cali_q;			/*store cali q*/
+	int8_t cali_result;
+	uint8_t cali_check_st;
+};
+
+int aw882xx_cali_init(struct aw_cali_desc *cali_desc);
+void aw882xx_cali_deinit(struct aw_cali_desc *cali_desc);
+int aw882xx_cali_svc_get_cali_status(void);
+int aw882xx_cali_read_re_from_nvram(int32_t *cali_re, int32_t ch_index);
+bool aw882xx_cali_check_result(struct aw_cali_desc *cali_desc);
+
+
+#endif

sound/soc/codecs/aw882xx/aw882xx_data_type.h

@@ -0,0 +1,165 @@
+/* SPDX-License-Identifier: GPL-2.0
+ * aw882xx_data_type.h
+ *
+ * Copyright (c) 2020 AWINIC Technology CO., LTD
+ *
+ * Author: Nick Li <liweilei@awinic.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __AW882XX_DATA_TYPE_H__
+#define __AW882XX_DATA_TYPE_H__
+
+#define AW_NAME_BUF_MAX (50)
+
+struct aw_msg_hdr {
+	int32_t type;
+	int32_t opcode_id;
+	int32_t version;
+	int32_t reseriver[3];
+};
+
+
+/******************************************************************
+ * aw profile
+ *******************************************************************/
+#define PROJECT_NAME_MAX (24)
+#define CUSTOMER_NAME_MAX (16)
+#define CFG_VERSION_MAX (4)
+#define DEV_NAME_MAX (16)
+#define PROFILE_STR_MAX (32)
+#define AW_INIT_PROFILE (0)
+
+#define ACF_FILE_ID (0xa15f908)
+
+
+enum aw_cfg_hdr_version {
+	AW_CFG_HDR_VER_0_0_0_1 = 0x00000001,
+	AW_CFG_HDR_VER_1_0_0_0 = 0x01000000,
+};
+
+enum aw_cfg_dde_type {
+	AW_DEV_TYPE_ID = 0x00000000,
+	AW_SKT_TYPE_ID = 0x00000001,
+	AW_DEV_DEFAULT_TYPE_ID = 0x00000002,
+};
+
+enum aw_sec_type {
+	ACF_SEC_TYPE_REG = 0,
+	ACF_SEC_TYPE_DSP,
+	ACF_SEC_TYPE_DSP_CFG,
+	ACF_SEC_TYPE_DSP_FW,
+	ACF_SEC_TYPE_HDR_REG,
+	ACF_SEC_TYPE_HDR_DSP_CFG,
+	ACF_SEC_TYPE_HDR_DSP_FW,
+	ACF_SEC_TYPE_MUTLBIN,
+	ACF_SEC_TYPE_SKT_PROJECT,
+	ACF_SEC_TYPE_DSP_PROJECT,
+	ACF_SEC_TYPE_MONITOR,
+	ACF_SEC_TYPE_MAX,
+};
+
+enum profile_data_type {
+	AW_PROFILE_DATA_TYPE_REG = 0,
+	AW_PROFILE_DATA_TYPE_DSP,
+	AW_PROFILE_DATA_TYPE_MAX,
+};
+
+enum aw_prof_type {
+	AW_PROFILE_MUSIC = 0,
+	AW_PROFILE_VOICE,
+	AW_PROFILE_VOIP,
+	AW_PROFILE_RINGTONE,
+	AW_PROFILE_RINGTONE_HS,
+	AW_PROFILE_LOWPOWER,
+	AW_PROFILE_BYPASS,
+	AW_PROFILE_MMI,
+	AW_PROFILE_FM,
+	AW_PROFILE_NOTIFICATION,
+	AW_PROFILE_RECEIVER,
+	AW_PROFILE_MAX,
+};
+
+enum aw_profile_status {
+	AW_PROFILE_WAIT = 0,
+	AW_PROFILE_OK,
+};
+
+struct aw_cfg_hdr {
+	uint32_t a_id;					/*acf file ID 0xa15f908*/
+	char a_project[PROJECT_NAME_MAX];		/*project name*/
+	char a_custom[CUSTOMER_NAME_MAX];		/*custom name :huawei xiaomi vivo oppo*/
+	char a_version[CFG_VERSION_MAX];		/*author update version*/
+	uint32_t a_author_id;				/*author id*/
+	uint32_t a_ddt_size;				/*sub section table entry size*/
+	uint32_t a_ddt_num;				/*sub section table entry num*/
+	uint32_t a_hdr_offset;				/*sub section table offset in file*/
+	uint32_t a_hdr_version;				/*sub section table version*/
+	uint32_t reserve[3];
+};
+
+struct aw_cfg_dde {
+	uint32_t type;					/*DDE type id*/
+	char dev_name[DEV_NAME_MAX];
+	uint16_t dev_index;				/*dev id*/
+	uint16_t dev_bus;				/*dev bus id*/
+	uint16_t dev_addr;				/*dev addr id*/
+	uint16_t dev_profile;				/*dev profile id*/
+	uint32_t data_type;				/*data type id*/
+	uint32_t data_size;
+	uint32_t data_offset;
+	uint32_t data_crc;
+	uint32_t reserve[5];
+};
+
+struct aw_cfg_dde_v_1_0_0_0 {
+	uint32_t type;					/*DDE type id*/
+	char dev_name[DEV_NAME_MAX];
+	uint16_t dev_index;				/*dev id*/
+	uint16_t dev_bus;				/*dev bus id*/
+	uint16_t dev_addr;				/*dev addr id*/
+	uint16_t dev_profile;				/*dev profile id*/
+	uint32_t data_type;				/*data type id*/
+	uint32_t data_size;
+	uint32_t data_offset;
+	uint32_t data_crc;
+	char dev_profile_str[PROFILE_STR_MAX];
+	uint32_t chip_id;
+	uint32_t reserve[4];
+};
+
+
+struct aw_container {
+	unsigned int len;
+	unsigned char data[];
+};
+
+struct aw_sec_data_desc {
+	uint32_t len;
+	char *data;
+};
+
+struct aw_prof_desc {
+	uint32_t prof_st; /*Only used in V0.0.0.1 header*/
+	uint32_t id;
+	char *prf_str;
+	struct aw_sec_data_desc sec_desc[AW_PROFILE_DATA_TYPE_MAX];
+};
+
+struct aw_all_prof_info {
+	struct aw_prof_desc prof_desc[AW_PROFILE_MAX];
+};
+
+struct aw_prof_info {
+	uint32_t count;
+	char **prof_name_list;
+	struct aw_prof_desc *prof_desc;
+};
+
+
+#endif
+

sound/soc/codecs/aw882xx/aw882xx_device.h

@@ -0,0 +1,463 @@
+/* SPDX-License-Identifier: GPL-2.0
+ * aw882xx_device.h
+ *
+ * Copyright (c) 2020 AWINIC Technology CO., LTD
+ *
+ * Author: Nick Li <liweilei@awinic.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __AW882XX_DEVICE_FILE_H__
+#define __AW882XX_DEVICE_FILE_H__
+#include "aw882xx_data_type.h"
+#include "aw882xx_calib.h"
+#include "aw882xx_monitor.h"
+#include "aw882xx_dsp.h"
+
+#define AW_VOLUME_STEP_DB	(6 * 2)
+#define AW_REG_NONE		(0xFF)
+#define AW_NAME_MAX		(50)
+#define ALGO_VERSION_MAX	(80)
+
+#define AW_GET_MIN_VALUE(value1, value2) \
+	((value1) > (value2) ? (value2) : (value1))
+
+#define AW_GET_MAX_VALUE(value1, value2)  \
+	((value1) > (value2) ? (value1) : (value2))
+
+extern int g_algo_auth_st;
+
+enum {
+	AW_1000_US = 1000,
+	AW_2000_US = 2000,
+	AW_3000_US = 3000,
+	AW_4000_US = 4000,
+	AW_5000_US = 5000,
+	AW_10000_US = 10000,
+	AW_32000_US = 32000,
+	AW_70000_US = 70000,
+	AW_100000_US = 100000,
+};
+
+struct aw_device;
+
+enum {
+	AW_DEV_TYPE_NONE = 0,
+	AW_DEV_TYPE_OK,
+};
+
+enum {
+	AW_EF_AND_CHECK = 0,
+	AW_EF_OR_CHECK,
+};
+
+enum {
+	AW_DEV_CH_PRI_L = 0,
+	AW_DEV_CH_PRI_R = 1,
+	AW_DEV_CH_SEC_L = 2,
+	AW_DEV_CH_SEC_R = 3,
+	AW_DEV_CH_TERT_L = 4,
+	AW_DEV_CH_TERT_R = 5,
+	AW_DEV_CH_QUAT_L = 6,
+	AW_DEV_CH_QUAT_R = 7,
+	AW_DEV_CH_MAX,
+};
+
+enum AW_DEV_INIT {
+	AW_DEV_INIT_ST = 0,
+	AW_DEV_INIT_OK = 1,
+	AW_DEV_INIT_NG = 2,
+};
+
+enum AW_DEV_STATUS {
+	AW_DEV_PW_OFF = 0,
+	AW_DEV_PW_ON,
+};
+
+enum AW_DEV_FW_STATUS {
+	AW_DEV_FW_FAILED = 0,
+	AW_DEV_FW_OK,
+};
+
+
+enum {
+	AW_EXT_DSP_WRITE_NONE = 0,
+	AW_EXT_DSP_WRITE,
+};
+
+enum AW_SPIN_KCONTROL_STATUS {
+	AW_SPIN_KCONTROL_DISABLE = 0,
+	AW_SPIN_KCONTROL_ENABLE,
+};
+
+enum AW_ALGO_AUTH_MODE {
+	AW_ALGO_AUTH_DISABLE = 0,
+	AW_ALGO_AUTH_MODE_MAGIC_ID,
+	AW_ALGO_AUTH_MODE_REG_CRC,
+};
+
+enum AW_ALGO_AUTH_ID {
+	AW_ALGO_AUTH_MAGIC_ID = 0x4157,
+};
+
+enum AW_ALGO_AUTH_STATUS {
+	AW_ALGO_AUTH_WAIT = 0,
+	AW_ALGO_AUTH_OK = 1,
+};
+
+struct aw_device_ops {
+	int (*aw_i2c_write)(struct aw_device *aw_dev, unsigned char reg_addr, unsigned int reg_data);
+	int (*aw_i2c_read)(struct aw_device *aw_dev, unsigned char reg_addr, unsigned int *reg_data);
+	int (*aw_i2c_write_bits)(struct aw_device *aw_dev, unsigned char reg_addr, unsigned int mask, unsigned int reg_data);
+	int (*aw_set_hw_volume)(struct aw_device *aw_dev, unsigned int value);
+	int (*aw_get_hw_volume)(struct aw_device *aw_dev, unsigned int *value);
+	unsigned int (*aw_reg_val_to_db)(unsigned int value);
+	bool (*aw_check_wr_access)(int reg);
+	bool (*aw_check_rd_access)(int reg);
+	int (*aw_get_reg_num)(void);
+	int (*aw_get_version)(char *buf, int size);
+	int (*aw_get_dev_num)(void);
+	void (*aw_set_algo)(struct aw_device *aw_dev);
+	unsigned int (*aw_get_irq_type)(struct aw_device *aw_dev, unsigned int value);
+	void (*aw_reg_force_set)(struct aw_device *aw_dev);
+	int (*aw_frcset_check)(struct aw_device *aw_dev);
+};
+
+struct aw_int_desc {
+	unsigned int mask_reg;			/*interrupt mask reg*/
+	unsigned int st_reg;			/*interrupt status reg*/
+	unsigned int mask_default;		/*default mask close all*/
+	unsigned int int_mask;			/*set mask*/
+};
+
+struct aw_work_mode {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int spk_val;
+	unsigned int rcv_val;
+};
+
+struct aw_soft_rst {
+	int reg;
+	int reg_value;
+};
+
+struct aw_pwd_desc {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int enable;
+	unsigned int disable;
+};
+
+struct aw_amppd_desc {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int enable;
+	unsigned int disable;
+};
+
+struct aw_bop_desc {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int enable;
+	unsigned int disbale;
+};
+
+struct aw_vcalb_desc {
+	unsigned int icalk_reg;
+	unsigned int icalk_reg_mask;
+	unsigned int icalk_shift;
+	unsigned int icalkl_reg;
+	unsigned int icalkl_reg_mask;
+	unsigned int icalkl_shift;
+	unsigned int icalk_sign_mask;
+	unsigned int icalk_neg_mask;
+	int icalk_value_factor;
+
+	unsigned int vcalk_reg;
+	unsigned int vcalk_reg_mask;
+	unsigned int vcalk_shift;
+	unsigned int vcalkl_reg;
+	unsigned int vcalkl_reg_mask;
+	unsigned int vcalkl_shift;
+	unsigned int vcalk_sign_mask;
+	unsigned int vcalk_neg_mask;
+	int vcalk_value_factor;
+
+	unsigned int vcalb_reg;
+	int cabl_base_value;
+	int vcal_factor;
+};
+
+struct aw_mute_desc {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int enable;
+	unsigned int disable;
+};
+
+struct aw_uls_hmute_desc {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int enable;
+	unsigned int disable;
+};
+
+struct aw_txen_desc {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int enable;
+	unsigned int disable;
+	unsigned int reserve_val;
+};
+
+struct aw_sysst_desc {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int st_check;
+	unsigned int st_sws_check;
+	unsigned int pll_check;
+};
+
+struct aw_profctrl_desc {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int spk_mode;
+	unsigned int cfg_prof_mode;
+};
+
+struct aw_bstctrl_desc {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int frc_bst;
+	unsigned int tsp_type;
+	unsigned int cfg_bst_type;
+};
+
+struct aw_cco_mux_desc {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int divided_val;
+	unsigned int bypass_val;
+};
+
+struct aw_volume_desc {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int shift;
+	int init_volume;
+	int mute_volume;
+	int ctl_volume;
+	int monitor_volume;
+};
+
+struct aw_voltage_desc {
+	unsigned int reg;
+	unsigned int vbat_range;
+	unsigned int int_bit;
+};
+
+struct aw_temperature_desc {
+	unsigned int reg;
+	unsigned int sign_mask;
+	unsigned int neg_mask;
+};
+
+struct aw_ipeak_desc {
+	unsigned int reg;
+	unsigned int mask;
+};
+
+struct aw_spin_ch {
+	uint16_t rx_val;
+};
+
+struct aw_reg_ch {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int left_val;
+	unsigned int right_val;
+};
+
+struct aw_spin_desc {
+	int aw_spin_kcontrol_st;
+	struct aw_spin_ch spin_table[AW_SPIN_MAX];
+	struct aw_reg_ch rx_desc;
+};
+
+struct aw_efcheck_desc {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int and_val;
+	unsigned int or_val;
+};
+
+struct aw_dither_desc {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int enable;
+	unsigned int disable;
+};
+
+struct aw_noise_gate_desc {
+	unsigned int reg;
+	unsigned int mask;
+};
+
+struct aw_psm_desc {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int enable;
+	unsigned int disable;
+};
+
+struct aw_mpd_desc {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int enable;
+	unsigned int disable;
+};
+
+struct aw_dsmzth_desc {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int enable;
+	unsigned int disable;
+};
+
+struct aw_auth_desc {
+	uint8_t reg_in;
+	uint8_t reg_out;
+	int32_t auth_mode;
+	int32_t reg_crc;
+	int32_t random;
+	int32_t chip_id;
+	int32_t check_result;
+};
+
+struct algo_auth_data {
+	int32_t auth_mode;  /* 0: disable  1 : chip ID  2 : reg crc */
+	int32_t reg_crc;
+	int32_t random;
+	int32_t chip_id;
+	int32_t check_result;
+};
+
+#define AW_IOCTL_MAGIC_S			'w'
+#define AW_IOCTL_GET_ALGO_AUTH			_IOWR(AW_IOCTL_MAGIC_S, 1, struct algo_auth_data)
+#define AW_IOCTL_SET_ALGO_AUTH			_IOWR(AW_IOCTL_MAGIC_S, 2, struct algo_auth_data)
+
+
+struct aw_device {
+	int status;
+	unsigned int chip_id;
+	unsigned int monitor_start;
+	int bstcfg_enable;
+	int frcset_en;
+	int bop_en;
+	int efuse_check;
+	int fade_en;
+	unsigned int mute_st;
+	unsigned int amppd_st;
+	unsigned int dither_st;
+	unsigned int txen_st;
+
+	unsigned char cur_prof;  /*current profile index*/
+	unsigned char set_prof;  /*set profile index*/
+	unsigned int channel;    /*pa channel select*/
+	unsigned int vol_step;
+	unsigned int re_max;
+	unsigned int re_min;
+
+	struct device *dev;
+	struct i2c_client *i2c;
+	char monitor_name[AW_NAME_MAX];
+	void *private_data;
+
+	struct aw_int_desc int_desc;
+	struct aw_work_mode work_mode;
+	struct aw_pwd_desc pwd_desc;
+	struct aw_amppd_desc amppd_desc;
+	struct aw_mute_desc mute_desc;
+	struct aw_uls_hmute_desc uls_hmute_desc;
+	struct aw_txen_desc txen_desc;
+	struct aw_vcalb_desc vcalb_desc;
+	struct aw_sysst_desc sysst_desc;
+	struct aw_profctrl_desc profctrl_desc;
+	struct aw_bstctrl_desc bstctrl_desc;
+	struct aw_cco_mux_desc cco_mux_desc;
+	struct aw_voltage_desc voltage_desc;
+	struct aw_temperature_desc temp_desc;
+	struct aw_ipeak_desc ipeak_desc;
+	struct aw_volume_desc volume_desc;
+	struct aw_prof_info prof_info;
+	struct aw_cali_desc cali_desc;
+	struct aw_monitor_desc monitor_desc;
+	struct aw_soft_rst soft_rst;
+	struct aw_spin_desc spin_desc;
+	struct aw_bop_desc bop_desc;
+	struct aw_efcheck_desc efcheck_desc;
+	struct aw_dither_desc dither_desc;
+	struct aw_noise_gate_desc noise_gate_desc;
+	struct aw_psm_desc psm_desc;
+	struct aw_mpd_desc mpd_desc;
+	struct aw_dsmzth_desc dsmzth_desc;
+	struct aw_auth_desc auth_desc;
+	struct aw_device_ops ops;
+	struct list_head list_node;
+};
+
+
+void aw882xx_dev_deinit(struct aw_device *aw_dev);
+int aw882xx_device_init(struct aw_device *aw_dev, struct aw_container *aw_cfg);
+int aw882xx_device_start(struct aw_device *aw_dev);
+int aw882xx_device_stop(struct aw_device *aw_dev);
+int aw882xx_dev_reg_update(struct aw_device *aw_dev, bool force);
+int aw882xx_device_irq_reinit(struct aw_device *aw_dev);
+
+struct mutex *aw882xx_dev_get_ext_dsp_prof_wr_lock(void);
+char *aw882xx_dev_get_ext_dsp_prof_write(void);
+
+/*re*/
+int aw882xx_dev_get_cali_re(struct aw_device *aw_dev, int32_t *cali_re);
+int aw882xx_dev_init_cali_re(struct aw_device *aw_dev);
+int aw882xx_dev_dc_status(struct aw_device *aw_dev);
+
+/*interrupt*/
+int aw882xx_dev_status(struct aw_device *aw_dev);
+int aw882xx_dev_get_int_status(struct aw_device *aw_dev, uint16_t *int_status);
+void aw882xx_dev_clear_int_status(struct aw_device *aw_dev);
+int aw882xx_dev_set_intmask(struct aw_device *aw_dev, bool flag);
+
+/*fade int / out*/
+void aw882xx_dev_set_fade_vol_step(struct aw_device *aw_dev, unsigned int step);
+int aw882xx_dev_get_fade_vol_step(struct aw_device *aw_dev);
+void aw882xx_dev_get_fade_time(unsigned int *time, bool fade_in);
+void aw882xx_dev_set_fade_time(unsigned int time, bool fade_in);
+
+/*dsp kcontrol*/
+int aw882xx_dev_set_afe_module_en(int type, int enable);
+int aw882xx_dev_get_afe_module_en(int type, int *status);
+int aw882xx_dev_set_copp_module_en(bool enable);
+
+int aw882xx_device_probe(struct aw_device *aw_dev);
+int aw882xx_device_remove(struct aw_device *aw_dev);
+int aw882xx_dev_get_list_head(struct list_head **head);
+
+int aw882xx_dev_set_volume(struct aw_device *aw_dev, unsigned int set_vol);
+int aw882xx_dev_get_volume(struct aw_device *aw_dev, unsigned int *get_vol);
+void aw882xx_dev_mute(struct aw_device *aw_dev, bool mute);
+
+
+void aw882xx_dev_monitor_hal_get_time(struct aw_device *aw_dev, uint32_t *time);
+void aw882xx_dev_monitor_hal_work(struct aw_device *aw_dev, uint32_t *vmax);
+
+int aw882xx_dev_algo_auth_mode(struct aw_device *aw_dev, struct algo_auth_data *algo_data);
+void aw882xx_dev_iv_forbidden_output(struct aw_device *aw_dev, bool power_waste);
+
+#endif
+

sound/soc/codecs/aw882xx/aw882xx_dsp.h

@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0
+ * aw882xx_dsp.h
+ *
+ * Copyright (c) 2020 AWINIC Technology CO., LTD
+ *
+ * Author: Nick Li <liweilei@awinic.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __AW882XX_DSP_H__
+#define __AW882XX_DSP_H__
+
+//#define AW_MTK_PLATFORM_WITH_DSP
+
+//#define AW_QCOM_ADM_MSG
+/*#define AW_ALGO_AUTH_DSP*/
+/*factor form 12bit(4096) to 1000*/
+#define AW_DSP_RE_TO_SHOW_RE(re)	(((re) * (1000)) >> (12))
+#define AW_SHOW_RE_TO_DSP_RE(re)	(((re) << 12) / (1000))
+
+#define AW_DSP_SLEEP_TIME	(10)
+
+#define AW_TX_DEFAULT_TOPO_ID		(0x1000FF00)
+#define AW_RX_DEFAULT_TOPO_ID		(0x1000FF01)
+#define AW_TX_DEFAULT_PORT_ID		(0x1007)
+#define AW_RX_DEFAULT_PORT_ID		(0x1006)
+
+#define AW_DSP_MSG_VER			(0x10000000)
+#define AW_DSP_CHANNEL_DEFAULT_NUM	(1)
+
+enum aw_dsp_msg_type {
+	AW_DSP_MSG_TYPE_DATA = 0,
+	AW_DSP_MSG_TYPE_CMD = 1,
+};
+
+enum {
+	AW_SPIN_0 = 0,
+	AW_SPIN_90,
+	AW_SPIN_180,
+	AW_SPIN_270,
+	AW_SPIN_MAX,
+};
+
+
+enum {
+	AW_AUDIO_MIX_DSIABLE = 0,
+	AW_AUDIO_MIX_ENABLE,
+};
+
+#define AW_DSP_MSG_HDR_VER (1)
+typedef struct aw_msg_hdr aw_dsp_msg_t;
+
+enum {
+	DSP_MSG_TYPE_WRITE_CMD = 0,
+	DSP_MSG_TYPE_WRITE_DATA,
+	DSP_MSG_TYPE_READ_DATA,
+};
+
+typedef struct aw_msg_hdr_v_1_0_0_0 {
+	int32_t checksum;
+	int32_t version;
+	int32_t type;
+	int32_t params_id;
+	int32_t channel;
+	int32_t num;
+	int32_t data_size;
+	int32_t reseriver[3];
+} aw_msg_hdr_t;
+
+int aw882xx_dsp_read_dsp_msg(struct aw_device *aw_dev, uint32_t msg_id, char *data_ptr, unsigned int size);
+int aw882xx_dsp_write_dsp_msg(struct aw_device *aw_dev, uint32_t msg_id, char *data_ptr, unsigned int size);
+int aw882xx_dsp_write_cali_cfg(struct aw_device *aw_dev, char *data, unsigned int data_len);
+int aw882xx_dsp_read_cali_cfg(struct aw_device *aw_dev, char *data, unsigned int data_len);
+int aw882xx_dsp_noise_en(struct aw_device *aw_dev, bool is_noise);
+int aw882xx_dsp_write_vmax(struct aw_device *aw_dev, char *data, unsigned int data_len);
+int aw882xx_dsp_read_vmax(struct aw_device *aw_dev, char *data, unsigned int data_len);
+int aw882xx_dsp_write_params(struct aw_device *aw_dev, char *data, unsigned int data_len);
+int aw882xx_dsp_write_cali_re(struct aw_device *aw_dev, int32_t cali_re);
+int aw882xx_dsp_read_cali_re(struct aw_device *aw_dev, int32_t *cali_re);
+int aw882xx_dsp_read_r0(struct aw_device *aw_dev, int32_t *r0);
+int aw882xx_dsp_read_st(struct aw_device *aw_dev, int32_t *r0, int32_t *te);
+int aw882xx_dsp_read_te(struct aw_device *aw_dev, int32_t *te);
+int aw882xx_dsp_get_dc_status(struct aw_device *aw_dev);
+int aw882xx_dsp_hmute_en(struct aw_device *aw_dev, bool is_hmute);
+int aw882xx_dsp_cali_en(struct aw_device *aw_dev, int32_t cali_msg_data);
+int aw882xx_dsp_read_f0(struct aw_device *aw_dev, int32_t *f0);
+int aw882xx_dsp_read_f0_q(struct aw_device *aw_dev, int32_t *f0, int32_t *q);
+int aw882xx_dsp_read_cali_data(struct aw_device *aw_dev, char *data, unsigned int data_len);
+int aw882xx_dsp_set_afe_module_en(int type, int enable);
+int aw882xx_dsp_get_afe_module_en(int type, int *status);
+int aw882xx_dsp_set_copp_module_en(bool enable);
+int aw882xx_dsp_write_spin(int spin_mode);
+int aw882xx_dsp_read_spin(int *spin_mode);
+int aw882xx_get_algo_version(struct aw_device *aw_dev, char *algo_ver_buf);
+void aw882xx_device_parse_topo_id_dt(struct aw_device *aw_dev);
+void aw882xx_device_parse_port_id_dt(struct aw_device *aw_dev);
+int aw882xx_dsp_set_mixer_en(struct aw_device *aw_dev, uint32_t mixer_en);
+#ifdef AW_ALGO_AUTH_DSP
+int aw882xx_dsp_read_algo_auth_data(struct aw_device *aw_dev,
+		char *data, unsigned int data_len);
+int aw882xx_dsp_write_algo_auth_data(struct aw_device *aw_dev,
+		char *data, unsigned int data_len);
+#endif
+#endif
+

sound/soc/codecs/aw882xx/aw882xx_log.h

@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0
+ * aw882xx_log.h
+ *
+ * Copyright (c) 2020 AWINIC Technology CO., LTD
+ *
+ * Author: Nick Li <liweilei@awinic.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __AW882XX_LOG_H__
+#define __AW882XX_LOG_H__
+
+/********************************************
+ * print information control
+ *******************************************/
+#define aw_dev_err(dev, format, ...) \
+		pr_err("[Awinic][%s]%s: " format "\n", dev_name(dev), __func__, ##__VA_ARGS__)
+#define aw_dev_info(dev, format, ...) \
+		pr_info("[Awinic][%s]%s: " format "\n", dev_name(dev), __func__, ##__VA_ARGS__)
+#define aw_dev_dbg(dev, format, ...) \
+		pr_debug("[Awinic][%s]%s: " format "\n", dev_name(dev), __func__, ##__VA_ARGS__)
+
+#define aw_pr_err(format, ...) \
+		pr_err("[Awinic]%s: " format "\n", __func__, ##__VA_ARGS__)
+#define aw_pr_info(format, ...) \
+		pr_info("[Awinic]%s: " format "\n", __func__, ##__VA_ARGS__)
+#define aw_pr_dbg(format, ...) \
+		pr_debug("[Awinic]%s: " format "\n", __func__, ##__VA_ARGS__)
+
+#endif
+

sound/soc/codecs/aw882xx/aw882xx_monitor.h

@@ -0,0 +1,234 @@
+/* SPDX-License-Identifier: GPL-2.0
+ * aw882xx_monitor.h
+ *
+ * Copyright (c) 2020 AWINIC Technology CO., LTD
+ *
+ * Author: Nick Li <liweilei@awinic.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __AW882XX_MONITOR_H__
+#define __AW882XX_MONITOR_H__
+
+/*#define AW_DEBUG*/
+
+struct aw_table;
+
+#define AW_TABLE_SIZE	sizeof(struct aw_table)
+#define AW_MONITOR_DEFAULT_FLAG (0)
+
+#define IPEAK_NONE	(0xFF)
+#define GAIN_NONE	(0xFF)
+#define VMAX_NONE	(0xFFFFFFFF)
+
+
+#define AW_GET_32_DATA(w, x, y, z) \
+		((uint32_t)((((uint8_t)w) << 24) | (((uint8_t)x) << 16) | (((uint8_t)y) << 8) | ((uint8_t)z)))
+#define AW_GET_16_DATA(x, y) \
+		((uint16_t)((((uint8_t)x) << 8) | (uint8_t)y))
+
+enum {
+	AW_MON_LOGIC_OR = 0,
+	AW_MON_LOGIC_AND = 1,
+};
+
+enum {
+	AW_FIRST_ENTRY = 0,
+	AW_NOT_FIRST_ENTRY = 1,
+};
+
+enum aw_monitor_hdr_ver {
+	AW_MONITOR_HDR_VER_0_1_0 = 0x00010000,
+	AW_MONITOR_HDR_VER_0_1_1 = 0x00010100,
+	AW_MONITOR_HDR_VER_0_1_2 = 0x00010200,
+};
+
+enum aw_monitor_init {
+	AW_MON_CFG_ST = 0,
+	AW_MON_CFG_OK = 1,
+};
+
+struct aw_monitor_hdr {
+	uint32_t check_sum;
+	uint32_t monitor_ver;
+	char chip_type[8];
+	uint32_t ui_ver;
+	uint32_t monitor_switch;
+	uint32_t monitor_time;
+	uint32_t monitor_count;
+	uint32_t ipeak_switch;
+	uint32_t gain_switch;
+	uint32_t vmax_switch;
+	uint32_t temp_switch;
+	uint32_t temp_aplha;
+	uint32_t temp_num;
+	uint32_t single_temp_size;
+	uint32_t temp_offset;
+	uint32_t vol_switch;
+	uint32_t vol_aplha;
+	uint32_t vol_num;
+	uint32_t single_vol_size;
+	uint32_t vol_offset;
+};
+
+#define MONITOR_EN_MASK		(0x01)
+
+enum {
+	MONITOR_EN_BIT = 0,
+	MONITOR_LOGIC_BIT = 1,
+	MONITOR_IPEAK_EN_BIT = 2,
+	MONITOR_GAIN_EN_BIT = 3,
+	MONITOR_VMAX_EN_BIT = 4,
+	MONITOR_TEMP_EN_BIT = 5,
+	MONITOR_VOL_EN_BIT = 6,
+	MONITOR_TEMPERATURE_SOURCE_BIT = 7,
+	MONITOR_VOLTAGE_SOURCE_BIT = 8,
+	MONITOR_VOLTAGE_MODE_BIT = 9,
+};
+
+struct aw_monitor_hdr_v_0_1_1 {
+	uint32_t check_sum;
+	uint32_t monitor_ver;
+	char chip_type[16];
+	uint32_t ui_ver;
+	uint32_t monitor_time;
+	uint32_t monitor_count;
+	uint32_t enable_flag;
+		/* [bit 31:7] */
+		/* [bit 6: vol en] */
+		/* [bit 5: temp en] */
+		/* [bit 4: vmax en] */
+		/* [bit 3: gain en] */
+		/* [bit 2: ipeak en] */
+		/* [bit 1: & or | flag] */
+		/* [bit 0: monitor en] */
+	uint32_t temp_aplha;
+	uint32_t temp_num;
+	uint32_t single_temp_size;
+	uint32_t temp_offset;
+	uint32_t vol_aplha;
+	uint32_t vol_num;
+	uint32_t single_vol_size;
+	uint32_t vol_offset;
+	uint32_t reserver[3];
+};
+
+/* v0.1.2 */
+struct aw_monitor_hdr_v_0_1_2 {
+	uint32_t check_sum;
+	uint32_t monitor_ver;
+	char chip_type[16];
+	uint32_t ui_ver;
+	uint32_t monitor_time;
+	uint32_t monitor_count;
+	uint32_t enable_flag;
+		/* [bit 31:7]*/
+		/* [bit 9: voltage mode]*/
+		/* [bit 8: voltage source]*/
+		/* [bit 7: temperature source]*/
+		/* [bit 6: vol en]*/
+		/* [bit 5: temp en]*/
+		/* [bit 4: vmax en]*/
+		/* [bit 3: gain en]*/
+		/* [bit 2: ipeak en]*/
+		/* [bit 1: & or | flag]*/
+		/* [bit 0: monitor en]*/
+	uint32_t temp_aplha;
+	uint32_t temp_num;
+	uint32_t single_temp_size;
+	uint32_t temp_offset;
+	uint32_t vol_aplha;
+	uint32_t vol_num;
+	uint32_t single_vol_size;
+	uint32_t vol_offset;
+	uint32_t reserver[3];
+};
+
+struct aw_table {
+	int16_t min_val;
+	int16_t max_val;
+	uint16_t ipeak;
+	uint16_t gain;
+	uint32_t vmax;
+};
+
+struct aw_table_info {
+	uint8_t table_num;
+	struct aw_table *aw_table;
+};
+
+struct aw_monitor_cfg {
+	uint8_t monitor_status;
+	uint32_t monitor_switch;
+	uint32_t monitor_time;
+	uint32_t monitor_count;
+	uint32_t logic_switch;
+	uint32_t temp_switch;
+	uint32_t temp_aplha;
+	uint32_t vol_switch;
+	uint32_t vol_aplha;
+	uint32_t ipeak_switch;
+	uint32_t gain_switch;
+	uint32_t vmax_switch;
+	uint32_t temp_source;
+	uint32_t vol_source;
+	uint32_t vol_mode;
+	struct aw_table_info temp_info;
+	struct aw_table_info vol_info;
+};
+
+struct aw_monitor_trace {
+	int32_t pre_val;
+	int32_t sum_val;
+	struct aw_table aw_table;
+};
+
+enum aw_monitor_mode {
+	AW_MON_KERNEL_MODE = 0,
+	AW_MON_HAL_MODE,
+};
+
+/******************************************************************
+ * struct aw882xx monitor
+ *******************************************************************/
+struct aw_monitor_desc {
+	struct delayed_work delay_work;
+	struct aw_monitor_cfg monitor_cfg;
+
+	bool mon_start_flag;
+	uint8_t first_entry;
+	uint8_t samp_count;
+	uint8_t db_offset;
+	uint8_t monitor_mode;
+
+	uint32_t pre_vmax;
+	struct aw_monitor_trace temp_trace;
+	struct aw_monitor_trace vol_trace;
+
+
+#ifdef AW_DEBUG
+	uint16_t test_vol;
+	int16_t test_temp;
+#endif
+};
+
+/******************************************************************
+ * aw882xx monitor functions
+ *******************************************************************/
+void aw882xx_monitor_start(struct aw_monitor_desc *monitor_desc);
+int aw882xx_monitor_stop(struct aw_monitor_desc *monitor_desc);
+void aw882xx_monitor_init(struct aw_monitor_desc *monitor_desc);
+void aw882xx_monitor_deinit(struct aw_monitor_desc *monitor_desc);
+int aw882xx_monitor_parse_fw(struct aw_monitor_desc *monitor_desc,
+				uint8_t *data, uint32_t data_len);
+
+void aw882xx_monitor_hal_work(struct aw_monitor_desc *monitor_desc, uint32_t *vmax);
+void aw882xx_monitor_hal_get_time(struct aw_monitor_desc *monitor_desc, uint32_t *time);
+
+
+#endif
+