drm/panthor: use firmware path from mainline kernel

Signed-off-by: nyanmisaka <nst799610810@gmail.com>
Co-authored-by: nyanmisaka <nst799610810@gmail.com>

Documentation/devicetree/bindings/arm/cix.yaml

@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/cix.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cixcomputing SoC series device tree bindings
+
+maintainers:
+  - fugang.duan <fugang.duan@cixcomputing.com>
+
+properties:
+  $nodename:
+    const: "/"
+  compatible:
+    oneOf:
+      - description: sky1 based Boards
+        items:
+          - enum:
+              - cix,sky1-evk       # sky1 EVK Board
+              - cix,sky1-batura    # sky1 BATURA Board
+          - const: cix,sky1
+
+additionalProperties: true
+
+...

Documentation/devicetree/bindings/clock/cix,sky1-audss-clock.yaml

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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/cix,sky1-audss-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cixtech Sky1 SoC Audio SubSystem Clock Controller Driver
+
+maintainers:
+  - Joakim Zhang <joakim.zhang@cixtech.com>
+
+description: |
+  All available clocks are defined as preprocessor macros in
+  include/dt-bindings/clock/sky1-audss.h header.
+
+properties:
+  compatible:
+    const: cix,sky1-audss-clock
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    description:
+      - audio_pll0 (FRAC) provides "audio_clk0" and "audio_clk1" that generates
+        I2S function clock, such as 8KHz, 16KHz etc, "audio_clk0" is also the clock
+        source of MCLK.
+      - audio_pll1 (FRAC) provides "audio_clk2" and "audio_clk3" that generates
+        I2S function clock, such as 11.025KHz, 22.5KHz etc, "audio_clk2" is also the clock
+        source of MCLK.
+      - mmsys_pll provides "audio_clk4" that generates AXI or APB clock for most devices
+        in audio subsystem (DSP, NOC, SRAM, HDA, DMAC, I2S, Timer and Mailbox).
+      - mmsys_pll provides "audio_clk5" that generates a fixed 48MHz clock for HDA, Timer
+        and Watchdog.
+
+  clock-names:
+    minItems: 6
+    items:
+      - const: audio_clk0
+      - const: audio_clk1
+      - const: audio_clk2
+      - const: audio_clk3
+      - const: audio_clk4
+      - const: audio_clk5
+
+  "#clock-cells":
+    const: 1
+
+  resets:
+    description: signal to reset all modules in audio subsystem except HIFI5 DSP.
+
+  reset-names:
+    const: noc
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - "#clock-cells"
+  - resets
+  - reset-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/sky1-audss.h>
+
+    clock-controller@07100000 {
+        compatible = "cix,sky1-audss-clock";
+        reg = <0x0 0x07100000 0x0 0x1000>;
+        clock-names = "audio_clk0", "audio_clk1",
+                      "audio_clk2", "audio_clk3",
+                      "audio_clk4", "audio_clk5";
+        clocks = <&clocks CLK_AUDIO_CLK0>, <&clocks CLK_AUDIO_CLK1>,
+                 <&clocks CLK_AUDIO_CLK2>, <&clocks CLK_AUDIO_CLK3>,
+                 <&clocks CLK_AUDIO_CLK4>, <&clocks CLK_AUDIO_CLK5>;
+        #clock-cells = <1>;
+    };

Documentation/devicetree/bindings/dma/arm_dma350.txt

@@ -0,0 +1,45 @@
+* ARM DMA350 Controller
+
+The ARM DMA350 controller can move blocks of memory contents
+between memory and peripherals or memory to memory.
+
+Required properties:
+  - compatible: should include both "arm,dma350" .
+  - reg: physical base address of the controller and length of memory mapped
+    region.
+  - interrupts: interrupt number to the cpu.
+
+Optional properties:
+  - dma-coherent      : Present if dma operations are coherent
+  - #dma-cells: must be <2>. used to represent the number of integer
+    cells in the dmas property of client device.
+  - dma-channels: contains the total number of DMA channels supported by the DMAC
+  - dma-requests: contains the total number of DMA requests supported by the DMAC
+
+
+Example:
+
+	pdma0: pdma@12680000 {
+		compatible = "arm,dma350";
+		reg = <0x12680000 0x1000>;
+		interrupts = <99>;
+		#dma-cells = <2>;
+		#dma-channels = <8>;
+		#dma-requests = <32>;
+	};
+
+Client drivers (device nodes requiring dma transfers from dev-to-mem or
+mem-to-dev) should specify the DMA channel numbers and dma channel names
+as shown below.
+
+  [property name]  = <[phandle of the dma controller] [dma channel id] [dma request id]>;
+  [property name]  = <[dma channel name]>
+
+      where 'dma request id' is the dma request number which is connected
+      to the client controller. The 'property name' 'dmas' and 'dma-names'
+      as required by the generic dma device tree binding helpers. The dma
+      names correspond 1:1 with the dma request ids in the dmas property.
+
+  Example:  dmas = <&pdma0 1 12
+		    &pdma1 2 11>;
+	    dma-names = "tx", "rx";

Documentation/devicetree/bindings/hwlock/sky1-hwspinlock.yaml

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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwlock/sky1-hwspinlock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sky1 Hardware Mutex Block
+
+maintainers:
+  - Jerry.Zhu <jerry.zhu@cixtech.com>
+
+description:
+  The hardware block provides mutexes utilized between different processors on
+  the SoC as part of the communication protocol used by these processors.
+
+properties:
+  compatible:
+    oneOf:
+      - enum:
+          - sky1,hwspinlock
+  reg:
+    maxItems: 1
+
+  '#hwlock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#hwlock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    hwclock: hwspinlock@06510000 {
+    	compatible = "sky1,hwspinlock";
+    	reg = <0x0 0x06510000 0x0 0x1000>;
+    	#hwlock-cells = <1>;
+    };
+...

Documentation/devicetree/bindings/mailbox/cix-mailbox.yaml

@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/mailbox/cix-mailbox.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Cix mailbox controller bindings
+
+maintainers:
+  - Lihua Liu <Lihua.Liu@cixcomputing.com>
+
+description:
+  CIX mailbox controller is used to exchange message within
+  multiple processors, such as AP, AUDIO DSP, SensorHub MCU,
+  etc. It supports 10 mailbox channels with different operating
+  mode and every channel is unidirectional.
+
+properties:
+  compatible:
+    const: cix,sky1-mbox
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  "#mbox-cells":
+    description: |
+      <&phandle channel>
+      phandle   : Label name of controller
+      channel   : Channel number
+
+      This controller supports three types of unidirectional channels, they are
+      1 register based channel, 1 fifo based channel and 8 fast channels.
+      A total of 10 channels for each controller. Following types are
+      supported:
+      channel 0_7 - Fast channel with 32bit transmit register and IRQ support.
+      channel 8   - Reg based channel with 32*32bit transsmit register and
+                    Doorbell+transmit acknowledgment IRQ support
+      channel 9   - Fifo based channel with 32*32bit depth fifo and IRQ support.
+    const: 1
+
+  cix,mbox_dir:
+    description: Direction of the mailbox (0:TX or 1:RX)
+    enum: [0, 1]
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - "#mbox-cells"
+  - cix,mbox_dir
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    mbox0: mailbox@30000000 {
+        compatible = "cix,sky1-mbox";
+        reg = <0x0 0x30000000 0x0 0x10000>;
+        interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+        #mbox-cells = <1>;
+        cix,mbox_dir = <0>;
+        status = "okay";
+    };

Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml

@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/cix,sky1-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cix Sky1 IOMUX Controller
+
+maintainers:
+  - Jerry Zhu <Jerry.Zhu@cixtech.com>
+
+
+properties:
+  compatible:
+    const: cix,sky1-iomuxc
+
+  reg:
+    maxItems: 1
+
+# Client device subnode's properties
+patternProperties:
+  'grp$':
+    type: object
+    description:
+      Pinctrl node's client devices use subnodes for desired pin configuration.
+      Client device subnodes use below standard properties.
+
+    properties:
+      sky1,pins:
+        description:
+          each entry consists of 1 short represents for mux&conf reg and 1 integer
+        items:
+          items:
+            - description: |
+                "mux&conf_reg" indicates the offset of mux&conf register.
+            - description: |
+                "mux&conf_val" indicates the mux&conf value to be applied.
+
+    required:
+      - sky1,pins
+
+    additionalProperties: false
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  # Pinmux controller node
+  - |
+    iomuxc: pinctrl@04160000 {
+        compatible = "cix,sky1-iomuxc";
+	reg = <0x0 0x04160000 0x0 0x10000>;
+
+        pinctrl_uart2: uart2grp {
+            sky1,pins =<
+                0x14c 0x1b
+                0x150 0x1b
+            >;
+        };
+    };
+
+...

Documentation/devicetree/bindings/pwm/sky1-pwm.yaml

@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/sky1-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cix Sky1 PWM controller
+
+maintainers:
+  - Jerry Zhu <jerry.zhu@cixtech.com>
+
+properties:
+  "#pwm-cells":
+    description: |
+      Should 3 for sky1 SoCs. See pwm.yaml in this directory for
+      a description of the cells format.
+    enum:
+      - 3
+
+  compatible:
+    oneOf:
+      - enum:
+          - cix,sky1-pwm
+      - items:
+          - const: cix,sky1-pwm
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: SoC PWM clock
+
+  clock-names:
+    items:
+      - const: clk
+
+required:
+  - "#pwm-cells"
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/sky1-clock.h>
+pwm: pwm@16001000 {
+	compatible = "cix,sky1-pwm";
+	reg = <0x0 0x16001000 0x0 0x10000>;
+	clock-names = "pclk", "iclk";
+	status = "disabled";
+};

Documentation/devicetree/bindings/remoteproc/cix_dsp_rproc.yaml

@@ -0,0 +1,113 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/remoteproc/cix_dsp_rproc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Cix DSP Remoteproc Driver bindings
+
+maintainers:
+  - Lihua Liu <Lihua.Liu@cixcomputing.com>
+
+description:
+  CIX DSP remoteproc driver is used to control audio dsp core,
+  such as start, stop and boot dsp. Mailbox will be
+  used for msg exchange between AP and dsp. In additional,
+  crash dump and recovery are supported with this driver when remote
+  processor crash happen.
+
+properties:
+  compatible:
+    const: cix,sky1-hifi5
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    description: Should contain the watchdog reset interrupt
+    maxItems: 1
+
+  clocks:
+    maxItems: 6
+
+  clock-names:
+    items:
+      - const: clk
+      - const: bclk
+      - const: pbclk
+      - const: sramclk
+      - const: mb0clk
+      - const: mb1clk
+
+  "#mbox-cells":
+    description: |
+      <&phandle channel>
+      phandle   : Label name of controller
+      channel   : Channel index
+
+      channel 0_7 - Fast channel with 32bit transmit register and IRQ support.
+      channel 8   - Reg based channel with 32*32bit transsmit register and
+                    Doorbell+transmit acknowledgment IRQ support
+      channel 9   - Fifo based channel with 32*32bit depth fifo and IRQ support.
+    const: 1
+
+  firmware-name:
+    description: Default name of the firmware to load to the remote processor.
+
+  memory-region:
+    description:
+      List of phandles to the reserved memory regions associated with the
+      remoteproc device. It describes the memories shared with
+      the remote processor (e.g. remoteproc firmware and carveouts, rpmsg
+      vrings, ...).
+
+  wakeup-source: true
+
+  resets:
+    maxItems: 1
+    description: signal to reset HIFI5 DSP.
+
+  reset-names:
+    maxItems: 1
+      - const: dsp
+
+  cix,dsp-ctrl:
+    description: Phandle to syscon block which provide access to Control Register Unit.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - "#mbox-cells"
+  - "firmware-name"
+  - "memroy-region"
+  - resets
+  - reset-names
+  - cix,dsp-ctrl
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+  audio-dsp {
+    compatible = "cix,sky1-hifi5";
+    reg = <0x0 0x30000000 0x0 0x100000>; /* TBD */
+    interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;/* TBD.IRQ? */
+    firmware-name = "cix/hifi5.bin";
+    mbox-names = "tx0", "rx0";
+    mboxes = <&mbox0 9>,	/* index=9: fifo base channel */
+        <&mbox1 9>;
+    memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>,
+        <&dsp_vdev0vring1>;
+  };
+
+    /* Reserve memory node */
+    dsp_vdev0buffer: vdev0buffer@82008000 {	/* 1M for tx/rx buffer */
+      compatible = "shared-dma-pool";
+      reg = <0x0 0x82008000 0x0 0x100000>;
+      no-map;
+    };

Documentation/devicetree/bindings/remoteproc/cix_sfh_rproc.yaml

@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/remoteproc/cix_sfh_rproc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Cix SFH Remoteproc Driver bindings
+
+maintainers:
+  - Lihua Liu <Lihua.Liu@cixcomputing.com>
+
+description:
+  CIX Sensor Fusion Hub remoteproc driver is used to control sensorHub
+  M33 core, such as start, stop and boot sensorhub mcu. Mailbox will be
+  used for msg exchange between AP and sensorhub mcu. In additional,
+  crash dump and recovery are supported with this driver when remote
+  processor crash happen.
+
+properties:
+  compatible:
+    const: cix,sky1-sfh
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    description: Should contain the watchdog reset interrupt
+    maxItems: 1
+
+  "#mbox-cells":
+    description: |
+      <&phandle channel>
+      phandle   : Label name of controller
+      channel   : Channel index
+
+      channel 0_7 - Fast channel with 32bit transmit register and IRQ support.
+      channel 8   - Reg based channel with 32*32bit transsmit register and
+                    Doorbell+transmit acknowledgment IRQ support
+      channel 9   - Fifo based channel with 32*32bit depth fifo and IRQ support.
+    const: 1
+
+  firmware-name:
+    description: Default name of the firmware to load to the remote processor.
+
+  memory-region:
+    description:
+      List of phandles to the reserved memory regions associated with the
+      remoteproc device. It describes the memories shared with
+      the remote processor (e.g. remoteproc firmware and carveouts, rpmsg
+      vrings, ...).
+
+  wakeup-source: true
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - "#mbox-cells"
+  - "firmware-name"
+  - "memroy-region"
+  - "wakeup-source"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    sensor-mcu {
+      compatible = "cix,sky1-sfh";
+      reg = <0x0 0x30000000 0x0 0x100000>;
+      interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+      firmware-name = "cix/sfh_fw.bin";
+      mbox-names = "tx1", "rx1";
+      mboxes = <&mbox2 0>,	/* index=0: Fast channel */
+        <&mbox3 0>;
+      memory-region = <&mcu_vdev0buffer>, <&mcu_vdev0vring0>,
+          <&mcu_vdev0vring1>, <&mcu_ram>;
+      wakeup-source;
+    };
+
+    /* Reserve memory node */
+    mcu_vdev0buffer: vdev0buffer@40008000 {	/* 1M for tx/rx buffer */
+      compatible = "shared-dma-pool";
+      reg = <0x0 0x40008000 0x0 0x100000>;
+      no-map;
+    };

Documentation/devicetree/bindings/reset/cix,sky1-src.yaml

@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/cix,sky1-src.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cix Sky1 System Reset Controller
+
+maintainers:
+  - Jerry Zhu <jerry.zhu@cixtech.com>
+
+description: |
+  The system reset controller can be used to reset various set of
+  peripherals. Device nodes that need access to reset lines should
+  specify them as a reset phandle in their corresponding node as
+  specified in reset.txt.
+
+  For list of all valid reset indices see
+    <dt-bindings/reset/sky1-reset.h> for Sky1
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - cix,sky1-src
+          - const: syscon
+      - items:
+          - enum:
+              - cix,sky1-src
+          - const: cix,sky1-src
+          - const: syscon
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  '#reset-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    reset-controller@30390000 {
+        compatible = "cix,sky1-src", "syscon";
+	reg = <0x0 0x16000000 0x0 0x10000>;
+        interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+        #reset-cells = <1>;
+    };

Documentation/devicetree/bindings/soc/cix/cix,ddr_exception.yaml

@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright 2025 Cix Technology Group Co., Ltd.
+%YAML 1.2
+---
+$id: ""
+$schema: ""
+
+title: Cix ddr exception driver.
+
+description: |
+  When a DDR exception occurs, it informs the AP through an interrupt, and the AP will parse the interrupt information.
+
+maintainers:
+  - Vincent Wu <vincent.wu@cixtech.com>
+  - Vimoon Zheng <vimoon.zheng@cixtech.com>
+
+properties:
+  compatible:
+    enum:
+      - cadence,ddr_ctrl
+
+  reg:
+    description: DDR interrupt information reg and DDR information reg
+    maxItems: 2
+
+  interrupts:
+    description: DDR interrupt number
+
+  channel_id:
+    description: DDR channel id
+
+  mbox-names:
+    description: mailbox name
+
+  mboxes:
+    description: Mailbox in use
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - channel_id
+  - mbox-names
+  - mboxes
+
+additionalProperties: false
+
+examples:
+  - |
+		ddr_ctrl1: ddr_ctrl@0C030000 {
+      compatible = "cadence,ddr_ctrl";
+      reg = <0x0 0x0C030000 0x0 0x20000>,
+        <0x0 0x83c00000 0x0 0x1000>;
+      interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
+      channel_id = <0x1>;
+      mbox-names = "tx4";
+      mboxes = <&mbox_ap2se 10>; /* index=9: fifo base channel */
+      status = "disabled";
+	  };

Documentation/devicetree/bindings/soc/cix/cix,se_pm_execption.yaml

@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright 2025 Cix Technology Group Co., Ltd.
+%YAML 1.2
+---
+$id: ""
+$schema: ""
+
+title: Cix SE & PM Exception Driver
+
+description: |
+  When an Exception occurs for SE or PM, AP will be notified to log this exception event.
+
+maintainers:
+  - Vincent Wu <vincent.wu@cixtech.com>
+  - Vimoon Zheng <vimoon.zheng@cixtech.com>
+
+properties:
+  compatible:
+    enum:
+      - cix,se_pm_crash
+
+  mbox-names:
+    description: mailbox name
+    maxItems: 4
+
+  mboxes:
+    description: Mailbox in use
+    maxItems: 1
+
+required:
+  - compatible
+  - mbox-names
+  - mboxes
+
+additionalProperties: false
+
+examples:
+  - |
+		crash: cix_se_pm_crash {
+			compatible = "cix,se_pm_crash";
+			mbox-names = "rx4";
+			mboxes = <&mbox_se2ap 9>;  /* index=9: fifo base channel */
+			status = "disabled";
+		};

Documentation/devicetree/bindings/sound/alc256.txt

@@ -0,0 +1,14 @@
+Alc256 ADC/DAC
+
+Required properties:
+
+  - compatible : "realtek,alc256"
+
+  - "#sound-dai-cells" :
+    const: 0
+
+Example:
+
+alc256_codec {
+        compatible = "realtek,alc256";
+};

Documentation/devicetree/bindings/sound/alc257.txt

@@ -0,0 +1,14 @@
+Alc256 ADC/DAC
+
+Required properties:
+
+  - compatible : "realtek,alc257"
+
+  - "#sound-dai-cells" :
+    const: 0
+
+Example:
+
+alc257_codec {
+        compatible = "realtek,alc257";
+};

Documentation/devicetree/bindings/sound/alc269.txt

@@ -0,0 +1,14 @@
+Alc256 ADC/DAC
+
+Required properties:
+
+  - compatible : "realtek,alc269"
+
+  - "#sound-dai-cells" :
+    const: 0
+
+Example:
+
+alc269_codec {
+        compatible = "realtek,alc269";
+};

Documentation/devicetree/bindings/sound/alc3287.txt

@@ -0,0 +1,14 @@
+Alc256 ADC/DAC
+
+Required properties:
+
+  - compatible : "realtek,alc3287"
+
+  - "#sound-dai-cells" :
+    const: 0
+
+Example:
+
+alc3287_codec {
+        compatible = "realtek,alc3287";
+};

Documentation/devicetree/bindings/sound/cdns,i2s-mc.yaml

@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/cdns,i2s-mc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title:
+  Cadence I2S-MC (MultiChannel) Controller Driver
+
+maintainers:
+  - Joakim Zhang <joakim.zhang@cixtech.com>
+
+properties:
+  compatible:
+    enum:
+      - cdns,sky1-i2s-mc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    minItems: 2
+    maxItems: 3
+    items:
+      - description: APB clock is used to provide synchronization of the design’s APB slave
+                     interface with external APB master (at the SoC level).
+                     The following modules are clocked by hst clock:
+                             - U_CDNSI2SSC_APB_SLAVE
+                             - U_CDNSI2SSC_SFR
+                             - U_CDNSI2SSC_FIFO_RX_APB
+                             - U_CDNSI2SSC_FIFO_TX_APB
+      - description: The main clock for synchronous logic in I2S transceiver.
+                     The following modules are clocked by i2s clock:
+                             - U_CDNSI2SMC_TRX_CHNx
+                             - U_CDNSI2SMC_RX_CTRL
+                             - U_CDNSI2SMC_TX_CTRL
+                             - U_CDNSI2SMC_RX_FIFO_I2S
+                             - U_CDNSI2SMC_TX_FIFO_I2S
+      - description: master clock feeding external codec
+
+  clock-names:
+    minItems: 2
+    maxItems: 3
+    items:
+      - const: hst
+      - const: i2s
+      - const: mclk
+
+  dmas:
+    items:
+      - description: audio playback dma
+      - description: audio capture dma
+
+  dma-names:
+    items:
+      - const: tx
+      - const: rx
+
+  cdns,pin-out-num:
+    description: The number of pins brought out by the SoC.
+      $ref: /schemas/types.yaml#/definitions/uint8
+      minimum: 1
+      maximum: 8
+
+  cdns,pin-tx-mask:
+    description: |
+      Transmit direction pin mask, if a bit is set the corresponding pin masked
+      as transmitter.
+    $ref: /schemas/types.yaml#/definitions/uint8
+
+  cdns,pin-rx-mask:
+    description: |
+      Receive direction pin mask, if a bit is set the corresponding pin masked
+      as receiver.
+    $ref: /schemas/types.yaml#/definitions/uint8
+
+  cdns,cru-ctrl:
+    description: Phandle to syscon block which provide access to Clock Reset Unit.
+
+  cdns,mclk-idx:
+    description: The index of mclk if mclk is present.
+
+  "#sound-dai-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - dmas
+  - dma-names
+  - cdns,pin-out-num
+  - cdns,pin-tx-mask
+  - cdns,pin-rx-mask
+  - cdns,mclk-idx
+  - "#sound-dai-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    i2s_mc0: i2s@03040000 {
+      compatible = "cdns,sky1-i2s-mc";
+      reg = <0x0 0x03040000 0x0 0x10000>;
+      interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+      clocks = <&clks 1>, <&clks 2>, <&clks 3>;
+      clock-names = "hst", "i2s", "mclk";
+      dmas = <&dma>, <&dma>;
+      dma-names = "tx", "rx";
+      cdns,pin-out-num = /bits/ 8 <8>;
+      cdns,pin-tx-mask = /bits/ 8 <15>; /* 0x0f, pin0-pin3 works as transmitter */
+      cdns,pin-rx-mask = /bits/ 8 <240>; /* 0xf0, pin4-pin7 works as receiver */
+      #sound-dai-cells = <1>;
+    }

Documentation/devicetree/bindings/sound/cdns,i2s-sc.yaml

@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/cdns,i2s-sc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title:
+  Cadence I2S-SC (SingleChannel) Controller Driver
+
+maintainers:
+  - Joakim Zhang <joakim.zhang@cixtech.com>
+
+properties:
+  compatible:
+    enum:
+      - cdns,sky1-i2s-sc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    minItems: 2
+    maxItems: 3
+    items:
+      - description: APB clock is used to provide synchronization of the design’s APB slave
+                     interface with external APB master (at the SoC level).
+                     The following modules are clocked by hst clock:
+                             - U_CDNSI2SSC_APB_SLAVE
+                             - U_CDNSI2SSC_SFR
+                             - U_CDNSI2SSC_FIFO_RX_APB
+                             - U_CDNSI2SSC_FIFO_TX_APB
+      - description: The main clock for synchronous logic in I2S transceiver.
+                     The following modules are clocked by i2s clock:
+                             - U_CDNSI2SSC_TRX_CTRL
+                             - U_CDNSI2SSC_RX_DATA
+                             - U_CDNSI2SSC_TX_DATA
+                             - U_CDNSI2SSC_FIFO_RX_I2S
+                             - U_CDNSI2SSC_FIFO_TX_I2S
+      - description: master clock feeding external codec
+
+  clock-names:
+    minItems: 2
+    maxItems: 3
+    items:
+      - const: hst
+      - const: i2s
+      - const: mclk
+
+  dmas:
+    items:
+      - description: audio playback dma
+      - description: audio capture dma
+
+  dma-names:
+    items:
+      - const: tx
+      - const: rx
+
+  cdns,cru-ctrl:
+    description: Phandle to syscon block which provide access to Clock Reset Unit.
+
+  cdns,mclk-idx:
+    description: The index of mclk if mclk is present.
+
+  "#sound-dai-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - dmas
+  - dma-names
+  - cdns,mclk-idx
+  - "#sound-dai-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    i2s_sc0: i2s@03010000 {
+      compatible = "cdns,sky1-i2s-sc";
+      reg = <0x0 0x03010000 0x0 0x10000>;
+      interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+      clocks = <&clks 1>, <&clks 2>, <&clks 3>;
+      clock-names = "hst", "i2s", "mclk";
+      dmas = <&dma>, <&dma>;
+      dma-names = "tx", "rx";
+      #sound-dai-cells = <0>;
+    }

Documentation/devicetree/bindings/sound/cix,sky1-card.yaml

@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/cux,sky1-card.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: CIX, sky1 sound card
+
+maintainers:
+  - Xing Wang <xing.wang@cixtech.com>
+
+properties:
+  compatible:
+    items:
+      - const: cix,sky1-sound-card
+
+  model:
+    $ref: /schemas/types.yaml#/definitions/string
+    description: User specified audio sound card name
+
+patternProperties:
+  "dai link name":
+    type: object
+    description: |-
+      dai-link child nodes, for i2s sc0~3, i2s mc , hda
+        Container for dai-link properties, cpu and codec sub-nodes.
+        There should be at least one (and probably more) subnode of this type
+
+    patternProperties:
+      "cpu":
+        type: object
+        description: |-
+          cpus:
+          cpu dai node
+
+        properties:
+          sound-dai:
+            $ref: /schemas/types.yaml#/definitions/phandle-array
+            description: phandle of the CPU DAI
+
+        required:
+          - sound-dai
+
+    patternProperties:
+      "codec":
+        type: object
+        description: |-
+          codec:
+          codec dai node
+
+        properties:
+          sound-dai:
+            $ref: /schemas/types.yaml#/definitions/phandle-array
+            description: phandle of the Codec DAI
+
+        required:
+          - sound-dai
+
+required:
+  - model
+  - dai link name
+
+examples:
+  - |
+    sound {
+            compatible = "cix,sky1-sound-card";
+            model = "cix,sky1";
+            status = "okay";
+
+            i2s-sc0 {
+                    cpu {
+                            sound-dai = <&i2s_sc0>;
+                    };
+                    codec {
+                            sound-dai = <&codec>;
+                    };
+            };
+    }

Documentation/devicetree/bindings/sound/ipbloq,hda.yaml

@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/ipbloq,hda.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title:
+  IPBloq HDA Controller Driver
+
+maintainers:
+  - Xing Wang <xing.wang@cixtech.com>
+
+properties:
+  compatible:
+    enum:
+      - ipbloq,hda
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    minItems: 3
+    maxItems: 3
+    items:
+      - description: sysclk for APB clock
+      - description: The 48m clock for synchronous logic.
+      - description: reset clock
+
+  clock-names:
+    minItems: 3
+    maxItems: 3
+    items:
+      - const: sysclk
+      - const: clk48m
+      - const: clkrst
+
+  "#sound-dai-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - "#sound-dai-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    ipb_hda: ipb-hda@70b0000 {
+      compatible = "ipbloq, hda";
+      reg = <0x0 0x700b0000 0x0 0x10000>;
+      #sound-dai-cells = <0>;
+      status = "disabled";
+    };