mirror of
https://github.com/armbian/linux-cix.git
synced 2026-01-06 12:30:45 -08:00
Merge tag 'net-next-for-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next
Pull networking updates from Jakub Kicinski:
"Core:
- Remove socket skb caches
- Add a SO_RESERVE_MEM socket op to forward allocate buffer space and
avoid memory accounting overhead on each message sent
- Introduce managed neighbor entries - added by control plane and
resolved by the kernel for use in acceleration paths (BPF / XDP
right now, HW offload users will benefit as well)
- Make neighbor eviction on link down controllable by userspace to
work around WiFi networks with bad roaming implementations
- vrf: Rework interaction with netfilter/conntrack
- fq_codel: implement L4S style ce_threshold_ect1 marking
- sch: Eliminate unnecessary RCU waits in mini_qdisc_pair_swap()
BPF:
- Add support for new btf kind BTF_KIND_TAG, arbitrary type tagging
as implemented in LLVM14
- Introduce bpf_get_branch_snapshot() to capture Last Branch Records
- Implement variadic trace_printk helper
- Add a new Bloomfilter map type
- Track <8-byte scalar spill and refill
- Access hw timestamp through BPF's __sk_buff
- Disallow unprivileged BPF by default
- Document BPF licensing
Netfilter:
- Introduce egress hook for looking at raw outgoing packets
- Allow matching on and modifying inner headers / payload data
- Add NFT_META_IFTYPE to match on the interface type either from
ingress or egress
Protocols:
- Multi-Path TCP:
- increase default max additional subflows to 2
- rework forward memory allocation
- add getsockopts: MPTCP_INFO, MPTCP_TCPINFO, MPTCP_SUBFLOW_ADDRS
- MCTP flow support allowing lower layer drivers to configure msg
muxing as needed
- Automatic Multicast Tunneling (AMT) driver based on RFC7450
- HSR support the redbox supervision frames (IEC-62439-3:2018)
- Support for the ip6ip6 encapsulation of IOAM
- Netlink interface for CAN-FD's Transmitter Delay Compensation
- Support SMC-Rv2 eliminating the current same-subnet restriction, by
exploiting the UDP encapsulation feature of RoCE adapters
- TLS: add SM4 GCM/CCM crypto support
- Bluetooth: initial support for link quality and audio/codec offload
Driver APIs:
- Add a batched interface for RX buffer allocation in AF_XDP buffer
pool
- ethtool: Add ability to control transceiver modules' power mode
- phy: Introduce supported interfaces bitmap to express MAC
capabilities and simplify PHY code
- Drop rtnl_lock from DSA .port_fdb_{add,del} callbacks
New drivers:
- WiFi driver for Realtek 8852AE 802.11ax devices (rtw89)
- Ethernet driver for ASIX AX88796C SPI device (x88796c)
Drivers:
- Broadcom PHYs
- support 72165, 7712 16nm PHYs
- support IDDQ-SR for additional power savings
- PHY support for QCA8081, QCA9561 PHYs
- NXP DPAA2: support for IRQ coalescing
- NXP Ethernet (enetc): support for software TCP segmentation
- Renesas Ethernet (ravb) - support DMAC and EMAC blocks of
Gigabit-capable IP found on RZ/G2L SoC
- Intel 100G Ethernet
- support for eswitch offload of TC/OvS flow API, including
offload of GRE, VxLAN, Geneve tunneling
- support application device queues - ability to assign Rx and Tx
queues to application threads
- PTP and PPS (pulse-per-second) extensions
- Broadcom Ethernet (bnxt)
- devlink health reporting and device reload extensions
- Mellanox Ethernet (mlx5)
- offload macvlan interfaces
- support HW offload of TC rules involving OVS internal ports
- support HW-GRO and header/data split
- support application device queues
- Marvell OcteonTx2:
- add XDP support for PF
- add PTP support for VF
- Qualcomm Ethernet switch (qca8k): support for QCA8328
- Realtek Ethernet DSA switch (rtl8366rb)
- support bridge offload
- support STP, fast aging, disabling address learning
- support for Realtek RTL8365MB-VC, a 4+1 port 10M/100M/1GE switch
- Mellanox Ethernet/IB switch (mlxsw)
- multi-level qdisc hierarchy offload (e.g. RED, prio and shaping)
- offload root TBF qdisc as port shaper
- support multiple routing interface MAC address prefixes
- support for IP-in-IP with IPv6 underlay
- MediaTek WiFi (mt76)
- mt7921 - ASPM, 6GHz, SDIO and testmode support
- mt7915 - LED and TWT support
- Qualcomm WiFi (ath11k)
- include channel rx and tx time in survey dump statistics
- support for 80P80 and 160 MHz bandwidths
- support channel 2 in 6 GHz band
- spectral scan support for QCN9074
- support for rx decapsulation offload (data frames in 802.3
format)
- Qualcomm phone SoC WiFi (wcn36xx)
- enable Idle Mode Power Save (IMPS) to reduce power consumption
during idle
- Bluetooth driver support for MediaTek MT7922 and MT7921
- Enable support for AOSP Bluetooth extension in Qualcomm WCN399x and
Realtek 8822C/8852A
- Microsoft vNIC driver (mana)
- support hibernation and kexec
- Google vNIC driver (gve)
- support for jumbo frames
- implement Rx page reuse
Refactor:
- Make all writes to netdev->dev_addr go thru helpers, so that we can
add this address to the address rbtree and handle the updates
- Various TCP cleanups and optimizations including improvements to
CPU cache use
- Simplify the gnet_stats, Qdisc stats' handling and remove
qdisc->running sequence counter
- Driver changes and API updates to address devlink locking
deficiencies"
* tag 'net-next-for-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (2122 commits)
Revert "net: avoid double accounting for pure zerocopy skbs"
selftests: net: add arp_ndisc_evict_nocarrier
net: ndisc: introduce ndisc_evict_nocarrier sysctl parameter
net: arp: introduce arp_evict_nocarrier sysctl parameter
libbpf: Deprecate AF_XDP support
kbuild: Unify options for BTF generation for vmlinux and modules
selftests/bpf: Add a testcase for 64-bit bounds propagation issue.
bpf: Fix propagation of signed bounds from 64-bit min/max into 32-bit.
bpf: Fix propagation of bounds from 64-bit min/max into 32-bit and var_off.
net: vmxnet3: remove multiple false checks in vmxnet3_ethtool.c
net: avoid double accounting for pure zerocopy skbs
tcp: rename sk_wmem_free_skb
netdevsim: fix uninit value in nsim_drv_configure_vfs()
selftests/bpf: Fix also no-alu32 strobemeta selftest
bpf: Add missing map_delete_elem method to bloom filter map
selftests/bpf: Add bloom map success test for userspace calls
bpf: Add alignment padding for "map_extra" + consolidate holes
bpf: Bloom filter map naming fixups
selftests/bpf: Add test cases for struct_ops prog
bpf: Add dummy BPF STRUCT_OPS for test purpose
...
This commit is contained in:
Linus Torvalds
174
Documentation/ABI/testing/sysfs-timecard
Normal file
174
Documentation/ABI/testing/sysfs-timecard
Normal file
@@ -0,0 +1,174 @@
|
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What: /sys/class/timecard/
|
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Date: September 2021
|
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Contact: Jonathan Lemon <jonathan.lemon@gmail.com>
|
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Description: This directory contains files and directories
|
||||
providing a standardized interface to the ancillary
|
||||
features of the OpenCompute timecard.
|
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|
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What: /sys/class/timecard/ocpN/
|
||||
Date: September 2021
|
||||
Contact: Jonathan Lemon <jonathan.lemon@gmail.com>
|
||||
Description: This directory contains the attributes of the Nth timecard
|
||||
registered.
|
||||
|
||||
What: /sys/class/timecard/ocpN/available_clock_sources
|
||||
Date: September 2021
|
||||
Contact: Jonathan Lemon <jonathan.lemon@gmail.com>
|
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Description: (RO) The list of available time sources that the PHC
|
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uses for clock adjustments.
|
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|
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==== =================================================
|
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NONE no adjustments
|
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PPS adjustments come from the PPS1 selector (default)
|
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TOD adjustments from the GNSS/TOD module
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IRIG adjustments from external IRIG-B signal
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DCF adjustments from external DCF signal
|
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==== =================================================
|
||||
|
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What: /sys/class/timecard/ocpN/available_sma_inputs
|
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Date: September 2021
|
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Contact: Jonathan Lemon <jonathan.lemon@gmail.com>
|
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Description: (RO) Set of available destinations (sinks) for a SMA
|
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input signal.
|
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|
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===== ================================================
|
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10Mhz signal is used as the 10Mhz reference clock
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PPS1 signal is sent to the PPS1 selector
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PPS2 signal is sent to the PPS2 selector
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TS1 signal is sent to timestamper 1
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TS2 signal is sent to timestamper 2
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IRIG signal is sent to the IRIG-B module
|
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DCF signal is sent to the DCF module
|
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===== ================================================
|
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|
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What: /sys/class/timecard/ocpN/available_sma_outputs
|
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Date: May 2021
|
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Contact: Jonathan Lemon <jonathan.lemon@gmail.com>
|
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Description: (RO) Set of available sources for a SMA output signal.
|
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|
||||
===== ================================================
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10Mhz output is from the 10Mhz reference clock
|
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PHC output PPS is from the PHC clock
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MAC output PPS is from the Miniature Atomic Clock
|
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GNSS output PPS is from the GNSS module
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GNSS2 output PPS is from the second GNSS module
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IRIG output is from the PHC, in IRIG-B format
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DCF output is from the PHC, in DCF format
|
||||
===== ================================================
|
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|
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What: /sys/class/timecard/ocpN/clock_source
|
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Date: September 2021
|
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Contact: Jonathan Lemon <jonathan.lemon@gmail.com>
|
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Description: (RW) Contains the current synchronization source used by
|
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the PHC. May be changed by writing one of the listed
|
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values from the available_clock_sources attribute set.
|
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|
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What: /sys/class/timecard/ocpN/gnss_sync
|
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Date: September 2021
|
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Contact: Jonathan Lemon <jonathan.lemon@gmail.com>
|
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Description: (RO) Indicates whether a valid GNSS signal is received,
|
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or when the signal was lost.
|
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|
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What: /sys/class/timecard/ocpN/i2c
|
||||
Date: September 2021
|
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Contact: Jonathan Lemon <jonathan.lemon@gmail.com>
|
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Description: This optional attribute links to the associated i2c device.
|
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|
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What: /sys/class/timecard/ocpN/irig_b_mode
|
||||
Date: September 2021
|
||||
Contact: Jonathan Lemon <jonathan.lemon@gmail.com>
|
||||
Description: (RW) An integer from 0-7 indicating the timecode format
|
||||
of the IRIG-B output signal: B00<n>
|
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|
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What: /sys/class/timecard/ocpN/pps
|
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Date: September 2021
|
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Contact: Jonathan Lemon <jonathan.lemon@gmail.com>
|
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Description: This optional attribute links to the associated PPS device.
|
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|
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What: /sys/class/timecard/ocpN/ptp
|
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Date: September 2021
|
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Contact: Jonathan Lemon <jonathan.lemon@gmail.com>
|
||||
Description: This attribute links to the associated PTP device.
|
||||
|
||||
What: /sys/class/timecard/ocpN/serialnum
|
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Date: September 2021
|
||||
Contact: Jonathan Lemon <jonathan.lemon@gmail.com>
|
||||
Description: (RO) Provides the serial number of the timecard.
|
||||
|
||||
What: /sys/class/timecard/ocpN/sma1
|
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What: /sys/class/timecard/ocpN/sma2
|
||||
What: /sys/class/timecard/ocpN/sma3
|
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What: /sys/class/timecard/ocpN/sma4
|
||||
Date: September 2021
|
||||
Contact: Jonathan Lemon <jonathan.lemon@gmail.com>
|
||||
Description: (RW) These attributes specify the direction of the signal
|
||||
on the associated SMA connectors, and also the signal sink
|
||||
or source.
|
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|
||||
The display format of the attribute is a space separated
|
||||
list of signals, prefixed by the input/output direction.
|
||||
|
||||
The signal direction may be changed (if supported) by
|
||||
prefixing the signal list with either "in:" or "out:".
|
||||
If neither prefix is present, then the direction is unchanged.
|
||||
|
||||
The output signal may be changed by writing one of the listed
|
||||
values from the available_sma_outputs attribute set.
|
||||
|
||||
The input destinations may be changed by writing multiple
|
||||
values from the available_sma_inputs attribute set,
|
||||
separated by spaces. If there are duplicated input
|
||||
destinations between connectors, the lowest numbered SMA
|
||||
connector is given priority.
|
||||
|
||||
Note that not all input combinations may make sense.
|
||||
|
||||
The 10Mhz reference clock input is currently only valid
|
||||
on SMA1 and may not be combined with other destination sinks.
|
||||
|
||||
What: /sys/class/timecard/ocpN/ts_window_adjust
|
||||
Date: September 2021
|
||||
Contact: Jonathan Lemon <jonathan.lemon@gmail.com>
|
||||
Description: (RW) When retrieving the PHC with the PTP SYS_OFFSET_EXTENDED
|
||||
ioctl, a system timestamp is made before and after the PHC
|
||||
time is retrieved. The midpoint between the two system
|
||||
timestamps is usually taken to be the SYS time associated
|
||||
with the PHC time. This estimate may be wrong, as it depends
|
||||
on PCI latencies, and when the PHC time was latched
|
||||
|
||||
The attribute value reduces the end timestamp by the given
|
||||
number of nanoseconds, so the computed midpoint matches the
|
||||
retrieved PHC time.
|
||||
|
||||
The initial value is set based on measured PCI latency and
|
||||
the estimated point where the FPGA latches the PHC time. This
|
||||
value may be changed by writing an unsigned integer.
|
||||
|
||||
What: /sys/class/timecard/ocpN/ttyGNSS
|
||||
What: /sys/class/timecard/ocpN/ttyGNSS2
|
||||
Date: September 2021
|
||||
Contact: Jonathan Lemon <jonathan.lemon@gmail.com>
|
||||
Description: These optional attributes link to the TTY serial ports
|
||||
associated with the GNSS devices.
|
||||
|
||||
What: /sys/class/timecard/ocpN/ttyMAC
|
||||
Date: September 2021
|
||||
Contact: Jonathan Lemon <jonathan.lemon@gmail.com>
|
||||
Description: This optional attribute links to the TTY serial port
|
||||
associated with the Miniature Atomic Clock.
|
||||
|
||||
What: /sys/class/timecard/ocpN/ttyNMEA
|
||||
Date: September 2021
|
||||
Contact: Jonathan Lemon <jonathan.lemon@gmail.com>
|
||||
Description: This optional attribute links to the TTY serial port
|
||||
which outputs the PHC time in NMEA ZDA format.
|
||||
|
||||
What: /sys/class/timecard/ocpN/utc_tai_offset
|
||||
Date: September 2021
|
||||
Contact: Jonathan Lemon <jonathan.lemon@gmail.com>
|
||||
Description: (RW) The DCF and IRIG output signals are in UTC, while the
|
||||
TimeCard operates on TAI. This attribute allows setting the
|
||||
offset in seconds, which is added to the TAI timebase for
|
||||
these formats.
|
||||
|
||||
The offset may be changed by writing an unsigned integer.
|
||||
92
Documentation/bpf/bpf_licensing.rst
Normal file
92
Documentation/bpf/bpf_licensing.rst
Normal file
@@ -0,0 +1,92 @@
|
||||
=============
|
||||
BPF licensing
|
||||
=============
|
||||
|
||||
Background
|
||||
==========
|
||||
|
||||
* Classic BPF was BSD licensed
|
||||
|
||||
"BPF" was originally introduced as BSD Packet Filter in
|
||||
http://www.tcpdump.org/papers/bpf-usenix93.pdf. The corresponding instruction
|
||||
set and its implementation came from BSD with BSD license. That original
|
||||
instruction set is now known as "classic BPF".
|
||||
|
||||
However an instruction set is a specification for machine-language interaction,
|
||||
similar to a programming language. It is not a code. Therefore, the
|
||||
application of a BSD license may be misleading in a certain context, as the
|
||||
instruction set may enjoy no copyright protection.
|
||||
|
||||
* eBPF (extended BPF) instruction set continues to be BSD
|
||||
|
||||
In 2014, the classic BPF instruction set was significantly extended. We
|
||||
typically refer to this instruction set as eBPF to disambiguate it from cBPF.
|
||||
The eBPF instruction set is still BSD licensed.
|
||||
|
||||
Implementations of eBPF
|
||||
=======================
|
||||
|
||||
Using the eBPF instruction set requires implementing code in both kernel space
|
||||
and user space.
|
||||
|
||||
In Linux Kernel
|
||||
---------------
|
||||
|
||||
The reference implementations of the eBPF interpreter and various just-in-time
|
||||
compilers are part of Linux and are GPLv2 licensed. The implementation of
|
||||
eBPF helper functions is also GPLv2 licensed. Interpreters, JITs, helpers,
|
||||
and verifiers are called eBPF runtime.
|
||||
|
||||
In User Space
|
||||
-------------
|
||||
|
||||
There are also implementations of eBPF runtime (interpreter, JITs, helper
|
||||
functions) under
|
||||
Apache2 (https://github.com/iovisor/ubpf),
|
||||
MIT (https://github.com/qmonnet/rbpf), and
|
||||
BSD (https://github.com/DPDK/dpdk/blob/main/lib/librte_bpf).
|
||||
|
||||
In HW
|
||||
-----
|
||||
|
||||
The HW can choose to execute eBPF instruction natively and provide eBPF runtime
|
||||
in HW or via the use of implementing firmware with a proprietary license.
|
||||
|
||||
In other operating systems
|
||||
--------------------------
|
||||
|
||||
Other kernels or user space implementations of eBPF instruction set and runtime
|
||||
can have proprietary licenses.
|
||||
|
||||
Using BPF programs in the Linux kernel
|
||||
======================================
|
||||
|
||||
Linux Kernel (while being GPLv2) allows linking of proprietary kernel modules
|
||||
under these rules:
|
||||
Documentation/process/license-rules.rst
|
||||
|
||||
When a kernel module is loaded, the linux kernel checks which functions it
|
||||
intends to use. If any function is marked as "GPL only," the corresponding
|
||||
module or program has to have GPL compatible license.
|
||||
|
||||
Loading BPF program into the Linux kernel is similar to loading a kernel
|
||||
module. BPF is loaded at run time and not statically linked to the Linux
|
||||
kernel. BPF program loading follows the same license checking rules as kernel
|
||||
modules. BPF programs can be proprietary if they don't use "GPL only" BPF
|
||||
helper functions.
|
||||
|
||||
Further, some BPF program types - Linux Security Modules (LSM) and TCP
|
||||
Congestion Control (struct_ops), as of Aug 2021 - are required to be GPL
|
||||
compatible even if they don't use "GPL only" helper functions directly. The
|
||||
registration step of LSM and TCP congestion control modules of the Linux
|
||||
kernel is done through EXPORT_SYMBOL_GPL kernel functions. In that sense LSM
|
||||
and struct_ops BPF programs are implicitly calling "GPL only" functions.
|
||||
The same restriction applies to BPF programs that call kernel functions
|
||||
directly via unstable interface also known as "kfunc".
|
||||
|
||||
Packaging BPF programs with user space applications
|
||||
====================================================
|
||||
|
||||
Generally, proprietary-licensed applications and GPL licensed BPF programs
|
||||
written for the Linux kernel in the same package can co-exist because they are
|
||||
separate executable processes. This applies to both cBPF and eBPF programs.
|
||||
@@ -85,6 +85,7 @@ sequentially and type id is assigned to each recognized type starting from id
|
||||
#define BTF_KIND_VAR 14 /* Variable */
|
||||
#define BTF_KIND_DATASEC 15 /* Section */
|
||||
#define BTF_KIND_FLOAT 16 /* Floating point */
|
||||
#define BTF_KIND_DECL_TAG 17 /* Decl Tag */
|
||||
|
||||
Note that the type section encodes debug info, not just pure types.
|
||||
``BTF_KIND_FUNC`` is not a type, and it represents a defined subprogram.
|
||||
@@ -106,7 +107,7 @@ Each type contains the following common data::
|
||||
* "size" tells the size of the type it is describing.
|
||||
*
|
||||
* "type" is used by PTR, TYPEDEF, VOLATILE, CONST, RESTRICT,
|
||||
* FUNC and FUNC_PROTO.
|
||||
* FUNC, FUNC_PROTO and DECL_TAG.
|
||||
* "type" is a type_id referring to another type.
|
||||
*/
|
||||
union {
|
||||
@@ -465,6 +466,32 @@ map definition.
|
||||
|
||||
No additional type data follow ``btf_type``.
|
||||
|
||||
2.2.17 BTF_KIND_DECL_TAG
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
``struct btf_type`` encoding requirement:
|
||||
* ``name_off``: offset to a non-empty string
|
||||
* ``info.kind_flag``: 0
|
||||
* ``info.kind``: BTF_KIND_DECL_TAG
|
||||
* ``info.vlen``: 0
|
||||
* ``type``: ``struct``, ``union``, ``func``, ``var`` or ``typedef``
|
||||
|
||||
``btf_type`` is followed by ``struct btf_decl_tag``.::
|
||||
|
||||
struct btf_decl_tag {
|
||||
__u32 component_idx;
|
||||
};
|
||||
|
||||
The ``name_off`` encodes btf_decl_tag attribute string.
|
||||
The ``type`` should be ``struct``, ``union``, ``func``, ``var`` or ``typedef``.
|
||||
For ``var`` or ``typedef`` type, ``btf_decl_tag.component_idx`` must be ``-1``.
|
||||
For the other three types, if the btf_decl_tag attribute is
|
||||
applied to the ``struct``, ``union`` or ``func`` itself,
|
||||
``btf_decl_tag.component_idx`` must be ``-1``. Otherwise,
|
||||
the attribute is applied to a ``struct``/``union`` member or
|
||||
a ``func`` argument, and ``btf_decl_tag.component_idx`` should be a
|
||||
valid index (starting from 0) pointing to a member or an argument.
|
||||
|
||||
3. BTF Kernel API
|
||||
*****************
|
||||
|
||||
|
||||
@@ -82,6 +82,15 @@ Testing and debugging BPF
|
||||
s390
|
||||
|
||||
|
||||
Licensing
|
||||
=========
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
|
||||
bpf_licensing
|
||||
|
||||
|
||||
Other
|
||||
=====
|
||||
|
||||
|
||||
@@ -150,6 +150,46 @@ mirror of the mainline's version of libbpf for a stand-alone build.
|
||||
However, all changes to libbpf's code base must be upstreamed through
|
||||
the mainline kernel tree.
|
||||
|
||||
|
||||
API documentation convention
|
||||
============================
|
||||
|
||||
The libbpf API is documented via comments above definitions in
|
||||
header files. These comments can be rendered by doxygen and sphinx
|
||||
for well organized html output. This section describes the
|
||||
convention in which these comments should be formated.
|
||||
|
||||
Here is an example from btf.h:
|
||||
|
||||
.. code-block:: c
|
||||
|
||||
/**
|
||||
* @brief **btf__new()** creates a new instance of a BTF object from the raw
|
||||
* bytes of an ELF's BTF section
|
||||
* @param data raw bytes
|
||||
* @param size number of bytes passed in `data`
|
||||
* @return new BTF object instance which has to be eventually freed with
|
||||
* **btf__free()**
|
||||
*
|
||||
* On error, error-code-encoded-as-pointer is returned, not a NULL. To extract
|
||||
* error code from such a pointer `libbpf_get_error()` should be used. If
|
||||
* `libbpf_set_strict_mode(LIBBPF_STRICT_CLEAN_PTRS)` is enabled, NULL is
|
||||
* returned on error instead. In both cases thread-local `errno` variable is
|
||||
* always set to error code as well.
|
||||
*/
|
||||
|
||||
The comment must start with a block comment of the form '/\*\*'.
|
||||
|
||||
The documentation always starts with a @brief directive. This line is a short
|
||||
description about this API. It starts with the name of the API, denoted in bold
|
||||
like so: **api_name**. Please include an open and close parenthesis if this is a
|
||||
function. Follow with the short description of the API. A longer form description
|
||||
can be added below the last directive, at the bottom of the comment.
|
||||
|
||||
Parameters are denoted with the @param directive, there should be one for each
|
||||
parameter. If this is a function with a non-void return, use the @return directive
|
||||
to document it.
|
||||
|
||||
License
|
||||
-------------------
|
||||
|
||||
|
||||
73
Documentation/devicetree/bindings/net/asix,ax88796c.yaml
Normal file
73
Documentation/devicetree/bindings/net/asix,ax88796c.yaml
Normal file
@@ -0,0 +1,73 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/net/asix,ax88796c.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ASIX AX88796C SPI Ethernet Adapter
|
||||
|
||||
maintainers:
|
||||
- Łukasz Stelmach <l.stelmach@samsung.com>
|
||||
|
||||
description: |
|
||||
ASIX AX88796C is an Ethernet controller with a built in PHY. This
|
||||
describes SPI mode of the chip.
|
||||
|
||||
The node for this driver must be a child node of an SPI controller,
|
||||
hence all mandatory properties described in
|
||||
../spi/spi-controller.yaml must be specified.
|
||||
|
||||
allOf:
|
||||
- $ref: ethernet-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: asix,ax88796c
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
spi-max-frequency:
|
||||
maximum: 40000000
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
reset-gpios:
|
||||
description:
|
||||
A GPIO line handling reset of the chip. As the line is active low,
|
||||
it should be marked GPIO_ACTIVE_LOW.
|
||||
maxItems: 1
|
||||
|
||||
local-mac-address: true
|
||||
|
||||
mac-address: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- spi-max-frequency
|
||||
- interrupts
|
||||
- reset-gpios
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Artik5 eval board
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
spi0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethernet@0 {
|
||||
compatible = "asix,ax88796c";
|
||||
reg = <0x0>;
|
||||
local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */
|
||||
interrupt-parent = <&gpx2>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
spi-max-frequency = <40000000>;
|
||||
reset-gpios = <&gpe0 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
@@ -2,7 +2,8 @@
|
||||
|
||||
Required properties:
|
||||
- compatible: should contain one of "brcm,genet-v1", "brcm,genet-v2",
|
||||
"brcm,genet-v3", "brcm,genet-v4", "brcm,genet-v5", "brcm,bcm2711-genet-v5".
|
||||
"brcm,genet-v3", "brcm,genet-v4", "brcm,genet-v5", "brcm,bcm2711-genet-v5" or
|
||||
"brcm,bcm7712-genet-v5".
|
||||
- reg: address and length of the register set for the device
|
||||
- interrupts and/or interrupts-extended: must be two cells, the first cell
|
||||
is the general purpose interrupt line, while the second cell is the
|
||||
|
||||
@@ -46,6 +46,9 @@ patternProperties:
|
||||
type: object
|
||||
description: Ethernet switch ports
|
||||
|
||||
allOf:
|
||||
- $ref: "http://devicetree.org/schemas/net/ethernet-controller.yaml#"
|
||||
|
||||
properties:
|
||||
reg:
|
||||
description: Port number
|
||||
@@ -73,11 +76,14 @@ patternProperties:
|
||||
dsa-tag-protocol:
|
||||
description:
|
||||
Instead of the default, the switch will use this tag protocol if
|
||||
possible. Useful when a device supports multiple protcols and
|
||||
possible. Useful when a device supports multiple protocols and
|
||||
the default is incompatible with the Ethernet device.
|
||||
enum:
|
||||
- dsa
|
||||
- edsa
|
||||
- ocelot
|
||||
- ocelot-8021q
|
||||
- seville
|
||||
|
||||
phy-handle: true
|
||||
|
||||
@@ -91,6 +97,10 @@ patternProperties:
|
||||
|
||||
managed: true
|
||||
|
||||
rx-internal-delay-ps: true
|
||||
|
||||
tx-internal-delay-ps: true
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
|
||||
@@ -74,10 +74,42 @@ properties:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
patternProperties:
|
||||
"^(ethernet-)?ports$":
|
||||
patternProperties:
|
||||
"^(ethernet-)?port@[0-9]+$":
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
phy-mode:
|
||||
contains:
|
||||
enum:
|
||||
- rgmii
|
||||
- rgmii-rxid
|
||||
- rgmii-txid
|
||||
- rgmii-id
|
||||
then:
|
||||
properties:
|
||||
rx-internal-delay-ps:
|
||||
$ref: "#/$defs/internal-delay-ps"
|
||||
tx-internal-delay-ps:
|
||||
$ref: "#/$defs/internal-delay-ps"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
$defs:
|
||||
internal-delay-ps:
|
||||
description:
|
||||
Disable tunable delay lines using 0 ps, or enable them and select
|
||||
the phase between 1640 ps (73.8 degree shift at 1Gbps) and 2260 ps
|
||||
(101.7 degree shift) in increments of 0.9 degrees (20 ps).
|
||||
enum:
|
||||
[0, 1640, 1660, 1680, 1700, 1720, 1740, 1760, 1780, 1800, 1820, 1840,
|
||||
1860, 1880, 1900, 1920, 1940, 1960, 1980, 2000, 2020, 2040, 2060, 2080,
|
||||
2100, 2120, 2140, 2160, 2180, 2200, 2220, 2240, 2260]
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
@@ -97,29 +129,40 @@ examples:
|
||||
port@0 {
|
||||
phy-handle = <&rgmii_phy6>;
|
||||
phy-mode = "rgmii-id";
|
||||
rx-internal-delay-ps = <0>;
|
||||
tx-internal-delay-ps = <0>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
phy-handle = <&rgmii_phy3>;
|
||||
phy-mode = "rgmii-id";
|
||||
rx-internal-delay-ps = <0>;
|
||||
tx-internal-delay-ps = <0>;
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
phy-handle = <&rgmii_phy4>;
|
||||
phy-mode = "rgmii-id";
|
||||
rx-internal-delay-ps = <0>;
|
||||
tx-internal-delay-ps = <0>;
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
phy-handle = <&rgmii_phy4>;
|
||||
phy-mode = "rgmii-id";
|
||||
rx-internal-delay-ps = <0>;
|
||||
tx-internal-delay-ps = <0>;
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet = <&enet2>;
|
||||
phy-mode = "rgmii";
|
||||
rx-internal-delay-ps = <0>;
|
||||
tx-internal-delay-ps = <0>;
|
||||
reg = <4>;
|
||||
|
||||
fixed-link {
|
||||
|
||||
@@ -1,215 +0,0 @@
|
||||
* Qualcomm Atheros QCA8xxx switch family
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be one of:
|
||||
"qca,qca8327"
|
||||
"qca,qca8334"
|
||||
"qca,qca8337"
|
||||
|
||||
- #size-cells: must be 0
|
||||
- #address-cells: must be 1
|
||||
|
||||
Optional properties:
|
||||
|
||||
- reset-gpios: GPIO to be used to reset the whole device
|
||||
|
||||
Subnodes:
|
||||
|
||||
The integrated switch subnode should be specified according to the binding
|
||||
described in dsa/dsa.txt. If the QCA8K switch is connect to a SoC's external
|
||||
mdio-bus each subnode describing a port needs to have a valid phandle
|
||||
referencing the internal PHY it is connected to. This is because there's no
|
||||
N:N mapping of port and PHY id.
|
||||
To declare the internal mdio-bus configuration, declare a mdio node in the
|
||||
switch node and declare the phandle for the port referencing the internal
|
||||
PHY is connected to. In this config a internal mdio-bus is registered and
|
||||
the mdio MASTER is used as communication.
|
||||
|
||||
Don't use mixed external and internal mdio-bus configurations, as this is
|
||||
not supported by the hardware.
|
||||
|
||||
The CPU port of this switch is always port 0.
|
||||
|
||||
A CPU port node has the following optional node:
|
||||
|
||||
- fixed-link : Fixed-link subnode describing a link to a non-MDIO
|
||||
managed entity. See
|
||||
Documentation/devicetree/bindings/net/fixed-link.txt
|
||||
for details.
|
||||
|
||||
For QCA8K the 'fixed-link' sub-node supports only the following properties:
|
||||
|
||||
- 'speed' (integer, mandatory), to indicate the link speed. Accepted
|
||||
values are 10, 100 and 1000
|
||||
- 'full-duplex' (boolean, optional), to indicate that full duplex is
|
||||
used. When absent, half duplex is assumed.
|
||||
|
||||
Examples:
|
||||
|
||||
for the external mdio-bus configuration:
|
||||
|
||||
&mdio0 {
|
||||
phy_port1: phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
phy_port2: phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
phy_port3: phy@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
phy_port4: phy@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
phy_port5: phy@4 {
|
||||
reg = <4>;
|
||||
};
|
||||
|
||||
switch@10 {
|
||||
compatible = "qca,qca8337";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
|
||||
reg = <0x10>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "cpu";
|
||||
ethernet = <&gmac1>;
|
||||
phy-mode = "rgmii";
|
||||
fixed-link {
|
||||
speed = 1000;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan1";
|
||||
phy-handle = <&phy_port1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
phy-handle = <&phy_port2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan3";
|
||||
phy-handle = <&phy_port3>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan4";
|
||||
phy-handle = <&phy_port4>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
label = "wan";
|
||||
phy-handle = <&phy_port5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
for the internal master mdio-bus configuration:
|
||||
|
||||
&mdio0 {
|
||||
switch@10 {
|
||||
compatible = "qca,qca8337";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
|
||||
reg = <0x10>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "cpu";
|
||||
ethernet = <&gmac1>;
|
||||
phy-mode = "rgmii";
|
||||
fixed-link {
|
||||
speed = 1000;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan1";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy_port1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy_port2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan3";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy_port3>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan4";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy_port4>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
label = "wan";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy_port5>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
phy_port1: phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
phy_port2: phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
phy_port3: phy@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
phy_port4: phy@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
phy_port5: phy@4 {
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
362
Documentation/devicetree/bindings/net/dsa/qca8k.yaml
Normal file
362
Documentation/devicetree/bindings/net/dsa/qca8k.yaml
Normal file
@@ -0,0 +1,362 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/net/dsa/qca8k.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Atheros QCA83xx switch family
|
||||
|
||||
maintainers:
|
||||
- John Crispin <john@phrozen.org>
|
||||
|
||||
description:
|
||||
If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
|
||||
describing a port needs to have a valid phandle referencing the internal PHY
|
||||
it is connected to. This is because there is no N:N mapping of port and PHY
|
||||
ID. To declare the internal mdio-bus configuration, declare an MDIO node in
|
||||
the switch node and declare the phandle for the port, referencing the internal
|
||||
PHY it is connected to. In this config, an internal mdio-bus is registered and
|
||||
the MDIO master is used for communication. Mixed external and internal
|
||||
mdio-bus configurations are not supported by the hardware.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- qca,qca8327
|
||||
- qca,qca8328
|
||||
- qca,qca8334
|
||||
- qca,qca8337
|
||||
description: |
|
||||
qca,qca8328: referenced as AR8328(N)-AK1(A/B) QFN 176 pin package
|
||||
qca,qca8327: referenced as AR8327(N)-AL1A DR-QFN 148 pin package
|
||||
qca,qca8334: referenced as QCA8334-AL3C QFN 88 pin package
|
||||
qca,qca8337: referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reset-gpios:
|
||||
description:
|
||||
GPIO to be used to reset the whole device
|
||||
maxItems: 1
|
||||
|
||||
qca,ignore-power-on-sel:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Ignore power-on pin strapping to configure LED open-drain or EEPROM
|
||||
presence. This is needed for devices with incorrect configuration or when
|
||||
the OEM has decided not to use pin strapping and falls back to SW regs.
|
||||
|
||||
qca,led-open-drain:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Set LEDs to open-drain mode. This requires the qca,ignore-power-on-sel to
|
||||
be set, otherwise the driver will fail at probe. This is required if the
|
||||
OEM does not use pin strapping to set this mode and prefers to set it
|
||||
using SW regs. The pin strappings related to LED open-drain mode are
|
||||
B68 on the QCA832x and B49 on the QCA833x.
|
||||
|
||||
mdio:
|
||||
type: object
|
||||
description: Qca8k switch have an internal mdio to access switch port.
|
||||
If this is not present, the legacy mapping is used and the
|
||||
internal mdio access is used.
|
||||
With the legacy mapping the reg corresponding to the internal
|
||||
mdio is the switch reg with an offset of -1.
|
||||
|
||||
properties:
|
||||
'#address-cells':
|
||||
const: 1
|
||||
'#size-cells':
|
||||
const: 0
|
||||
|
||||
patternProperties:
|
||||
"^(ethernet-)?phy@[0-4]$":
|
||||
type: object
|
||||
|
||||
allOf:
|
||||
- $ref: "http://devicetree.org/schemas/net/mdio.yaml#"
|
||||
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
patternProperties:
|
||||
"^(ethernet-)?ports$":
|
||||
type: object
|
||||
properties:
|
||||
'#address-cells':
|
||||
const: 1
|
||||
'#size-cells':
|
||||
const: 0
|
||||
|
||||
patternProperties:
|
||||
"^(ethernet-)?port@[0-6]$":
|
||||
type: object
|
||||
description: Ethernet switch ports
|
||||
|
||||
properties:
|
||||
reg:
|
||||
description: Port number
|
||||
|
||||
label:
|
||||
description:
|
||||
Describes the label associated with this port, which will become
|
||||
the netdev name
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
|
||||
link:
|
||||
description:
|
||||
Should be a list of phandles to other switch's DSA port. This
|
||||
port is used as the outgoing port towards the phandle ports. The
|
||||
full routing information must be given, not just the one hop
|
||||
routes to neighbouring switches
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
|
||||
ethernet:
|
||||
description:
|
||||
Should be a phandle to a valid Ethernet device node. This host
|
||||
device is what the switch port is connected to
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
phy-handle: true
|
||||
|
||||
phy-mode: true
|
||||
|
||||
fixed-link: true
|
||||
|
||||
mac-address: true
|
||||
|
||||
sfp: true
|
||||
|
||||
qca,sgmii-rxclk-falling-edge:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Set the receive clock phase to falling edge. Mostly commonly used on
|
||||
the QCA8327 with CPU port 0 set to SGMII.
|
||||
|
||||
qca,sgmii-txclk-falling-edge:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Set the transmit clock phase to falling edge.
|
||||
|
||||
qca,sgmii-enable-pll:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
For SGMII CPU port, explicitly enable PLL, TX and RX chain along with
|
||||
Signal Detection. On the QCA8327 this should not be enabled, otherwise
|
||||
the SGMII port will not initialize. When used on the QCA8337, revision 3
|
||||
or greater, a warning will be displayed. When the CPU port is set to
|
||||
SGMII on the QCA8337, it is advised to set this unless a communication
|
||||
issue is observed.
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
oneOf:
|
||||
- required:
|
||||
- ports
|
||||
- required:
|
||||
- ethernet-ports
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
external_phy_port1: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
external_phy_port2: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
external_phy_port3: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
external_phy_port4: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
external_phy_port5: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
};
|
||||
|
||||
switch@10 {
|
||||
compatible = "qca,qca8337";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
|
||||
reg = <0x10>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "cpu";
|
||||
ethernet = <&gmac1>;
|
||||
phy-mode = "rgmii";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan1";
|
||||
phy-handle = <&external_phy_port1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
phy-handle = <&external_phy_port2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan3";
|
||||
phy-handle = <&external_phy_port3>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan4";
|
||||
phy-handle = <&external_phy_port4>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
label = "wan";
|
||||
phy-handle = <&external_phy_port5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch@10 {
|
||||
compatible = "qca,qca8337";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
|
||||
reg = <0x10>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "cpu";
|
||||
ethernet = <&gmac1>;
|
||||
phy-mode = "rgmii";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan1";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&internal_phy_port1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&internal_phy_port2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan3";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&internal_phy_port3>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan4";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&internal_phy_port4>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
label = "wan";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&internal_phy_port5>;
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <0>;
|
||||
label = "cpu";
|
||||
ethernet = <&gmac1>;
|
||||
phy-mode = "sgmii";
|
||||
|
||||
qca,sgmii-rxclk-falling-edge;
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
internal_phy_port1: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
internal_phy_port2: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
internal_phy_port3: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
internal_phy_port4: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
internal_phy_port5: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -9,6 +9,7 @@ SMI-based Realtek devices.
|
||||
Required properties:
|
||||
|
||||
- compatible: must be exactly one of:
|
||||
"realtek,rtl8365mb" (4+1 ports)
|
||||
"realtek,rtl8366"
|
||||
"realtek,rtl8366rb" (4+1 ports)
|
||||
"realtek,rtl8366s" (4+1 ports)
|
||||
@@ -62,6 +63,8 @@ and subnodes of DSA switches.
|
||||
|
||||
Examples:
|
||||
|
||||
An example for the RTL8366RB:
|
||||
|
||||
switch {
|
||||
compatible = "realtek,rtl8366rb";
|
||||
/* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */
|
||||
@@ -151,3 +154,87 @@ switch {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
An example for the RTL8365MB-VC:
|
||||
|
||||
switch {
|
||||
compatible = "realtek,rtl8365mb";
|
||||
mdc-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
|
||||
mdio-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
|
||||
|
||||
switch_intc: interrupt-controller {
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "swp0";
|
||||
phy-handle = <ðphy0>;
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "swp1";
|
||||
phy-handle = <ðphy1>;
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "swp2";
|
||||
phy-handle = <ðphy2>;
|
||||
};
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "swp3";
|
||||
phy-handle = <ðphy3>;
|
||||
};
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
label = "cpu";
|
||||
ethernet = <&fec1>;
|
||||
phy-mode = "rgmii";
|
||||
tx-internal-delay-ps = <2000>;
|
||||
rx-internal-delay-ps = <2000>;
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
compatible = "realtek,smi-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: phy@0 {
|
||||
reg = <0>;
|
||||
interrupt-parent = <&switch_intc>;
|
||||
interrupts = <0>;
|
||||
};
|
||||
ethphy1: phy@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&switch_intc>;
|
||||
interrupts = <1>;
|
||||
};
|
||||
ethphy2: phy@2 {
|
||||
reg = <2>;
|
||||
interrupt-parent = <&switch_intc>;
|
||||
interrupts = <2>;
|
||||
};
|
||||
ethphy3: phy@3 {
|
||||
reg = <3>;
|
||||
interrupt-parent = <&switch_intc>;
|
||||
interrupts = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
69
Documentation/devicetree/bindings/net/lantiq,etop-xway.yaml
Normal file
69
Documentation/devicetree/bindings/net/lantiq,etop-xway.yaml
Normal file
@@ -0,0 +1,69 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/net/lantiq,etop-xway.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Lantiq Xway ETOP Ethernet driver
|
||||
|
||||
maintainers:
|
||||
- John Crispin <john@phrozen.org>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^ethernet@[0-9a-f]+$"
|
||||
|
||||
compatible:
|
||||
const: lantiq,etop-xway
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: TX interrupt
|
||||
- description: RX interrupt
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: tx
|
||||
- const: rx
|
||||
|
||||
lantiq,tx-burst-length:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
TX programmable burst length.
|
||||
enum: [2, 4, 8]
|
||||
|
||||
lantiq,rx-burst-length:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
RX programmable burst length.
|
||||
enum: [2, 4, 8]
|
||||
|
||||
phy-mode: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupt-parent
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- lantiq,tx-burst-length
|
||||
- lantiq,rx-burst-length
|
||||
- phy-mode
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
ethernet@e180000 {
|
||||
compatible = "lantiq,etop-xway";
|
||||
reg = <0xe180000 0x40000>;
|
||||
interrupt-parent = <&icu0>;
|
||||
interrupts = <73>, <78>;
|
||||
interrupt-names = "tx", "rx";
|
||||
lantiq,tx-burst-length = <8>;
|
||||
lantiq,rx-burst-length = <8>;
|
||||
phy-mode = "rmii";
|
||||
};
|
||||
@@ -1,21 +0,0 @@
|
||||
Lantiq xRX200 GSWIP PMAC Ethernet driver
|
||||
==================================
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : "lantiq,xrx200-net" for the PMAC of the embedded
|
||||
: GSWIP in the xXR200
|
||||
- reg : memory range of the PMAC core inside of the GSWIP core
|
||||
- interrupts : TX and RX DMA interrupts. Use interrupt-names "tx" for
|
||||
: the TX interrupt and "rx" for the RX interrupt.
|
||||
|
||||
Example:
|
||||
|
||||
ethernet@e10b308 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "lantiq,xrx200-net";
|
||||
reg = <0xe10b308 0xcf8>;
|
||||
interrupts = <73>, <72>;
|
||||
interrupt-names = "tx", "rx";
|
||||
};
|
||||
59
Documentation/devicetree/bindings/net/lantiq,xrx200-net.yaml
Normal file
59
Documentation/devicetree/bindings/net/lantiq,xrx200-net.yaml
Normal file
@@ -0,0 +1,59 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/net/lantiq,xrx200-net.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Lantiq xRX200 GSWIP PMAC Ethernet driver
|
||||
|
||||
maintainers:
|
||||
- Hauke Mehrtens <hauke@hauke-m.de>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^ethernet@[0-9a-f]+$"
|
||||
|
||||
compatible:
|
||||
const: lantiq,xrx200-net
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: TX interrupt
|
||||
- description: RX interrupt
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: tx
|
||||
- const: rx
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupt-parent
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
ethernet@e10b308 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "lantiq,xrx200-net";
|
||||
reg = <0xe10b308 0xcf8>;
|
||||
interrupt-parent = <&icu0>;
|
||||
interrupts = <73>, <72>;
|
||||
interrupt-names = "tx", "rx";
|
||||
};
|
||||
@@ -30,6 +30,10 @@ Required properties:
|
||||
Optional elements: 'tsu_clk'
|
||||
- clocks: Phandles to input clocks.
|
||||
|
||||
Optional properties:
|
||||
- mdio: node containing PHY children. If this node is not present, then PHYs
|
||||
will be direct children.
|
||||
|
||||
The MAC address will be determined using the optional properties
|
||||
defined in ethernet.txt.
|
||||
|
||||
|
||||
@@ -51,6 +51,9 @@ examples:
|
||||
switch@10 {
|
||||
compatible = "qca,qca8337";
|
||||
reg = <0x10>;
|
||||
/* ... */
|
||||
|
||||
ports {
|
||||
/* ... */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -100,15 +100,18 @@ additionalProperties: false
|
||||
examples:
|
||||
# Lager board
|
||||
- |
|
||||
#include <dt-bindings/clock/r8a7790-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/r8a7790-sysc.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
ethernet@ee700000 {
|
||||
compatible = "renesas,ether-r8a7790", "renesas,rcar-gen2-ether";
|
||||
reg = <0xee700000 0x400>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
|
||||
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 813>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 813>;
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <&phy1>;
|
||||
renesas,ether-link-active-low;
|
||||
@@ -116,8 +119,12 @@ examples:
|
||||
#size-cells = <0>;
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-id0022.1537",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
micrel,led-mode = <1>;
|
||||
reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -287,6 +287,7 @@ examples:
|
||||
"ch13", "ch14", "ch15", "ch16", "ch17", "ch18",
|
||||
"ch19", "ch20", "ch21", "ch22", "ch23", "ch24";
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
clock-names = "fck";
|
||||
iommus = <&ipmmu_ds0 16>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
@@ -298,6 +299,8 @@ examples:
|
||||
#size-cells = <0>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id0022.1622",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
rxc-skew-ps = <1500>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
|
||||
@@ -24,6 +24,7 @@ properties:
|
||||
- socionext,uniphier-ld11-ave4
|
||||
- socionext,uniphier-ld20-ave4
|
||||
- socionext,uniphier-pxs3-ave4
|
||||
- socionext,uniphier-nx1-ave4
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user