mirror of
https://github.com/armbian/linux-cix.git
synced 2026-01-06 12:30:45 -08:00
Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC driver updates from Olof Johansson:
"Various driver updates for platforms:
- A larger set of work on Tegra 2/3 around memory controller and
regulator features, some fuse cleanups, etc..
- MMP platform drivers, in particular for USB PHY, and other smaller
additions.
- Samsung Exynos 5422 driver for DMC (dynamic memory configuration),
and ASV (adaptive voltage), allowing the platform to run at more
optimal operating points.
- Misc refactorings and support for RZ/G2N and R8A774B1 from Renesas
- Clock/reset control driver for TI/OMAP
- Meson-A1 reset controller support
- Qualcomm sdm845 and sda845 SoC IDs for socinfo"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (150 commits)
firmware: arm_scmi: Fix doorbell ring logic for !CONFIG_64BIT
soc: fsl: add RCPM driver
dt-bindings: fsl: rcpm: Add 'little-endian' and update Chassis definition
memory: tegra: Consolidate registers definition into common header
memory: tegra: Ensure timing control debug features are disabled
memory: tegra: Introduce Tegra30 EMC driver
memory: tegra: Do not handle error from wait_for_completion_timeout()
memory: tegra: Increase handshake timeout on Tegra20
memory: tegra: Print a brief info message about EMC timings
memory: tegra: Pre-configure debug register on Tegra20
memory: tegra: Include io.h instead of iopoll.h
memory: tegra: Adapt for Tegra20 clock driver changes
memory: tegra: Don't set EMC rate to maximum on probe for Tegra20
memory: tegra: Add gr2d and gr3d to DRM IOMMU group
memory: tegra: Set DMA mask based on supported address bits
soc: at91: Add Atmel SFR SN (Serial Number) support
memory: atmel-ebi: switch to SPDX license identifiers
memory: atmel-ebi: move NUM_CS definition inside EBI driver
soc: mediatek: Refactor bus protection control
soc: mediatek: Refactor sram control
...
This commit is contained in:
Linus Torvalds
@@ -103,7 +103,7 @@ the Microchip website: http://www.microchip.com.
|
||||
|
||||
* Datasheet
|
||||
|
||||
http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11121-32-bit-Cortex-A5-Microcontroller-SAMA5D3_Datasheet.pdf
|
||||
http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11121-32-bit-Cortex-A5-Microcontroller-SAMA5D3_Datasheet_B.pdf
|
||||
|
||||
* ARM Cortex-A5 + NEON based SoCs
|
||||
- sama5d4 family
|
||||
@@ -167,7 +167,7 @@ the Microchip website: http://www.microchip.com.
|
||||
|
||||
* Datasheet
|
||||
|
||||
http://ww1.microchip.com/downloads/en/DeviceDoc/60001527A.pdf
|
||||
http://ww1.microchip.com/downloads/en/DeviceDoc/SAM-E70-S70-V70-V71-Family-Data-Sheet-DS60001527D.pdf
|
||||
|
||||
|
||||
Linux kernel information
|
||||
|
||||
@@ -1,41 +0,0 @@
|
||||
== Introduction==
|
||||
|
||||
LLCC (Last Level Cache Controller) provides last level of cache memory in SOC,
|
||||
that can be shared by multiple clients. Clients here are different cores in the
|
||||
SOC, the idea is to minimize the local caches at the clients and migrate to
|
||||
common pool of memory. Cache memory is divided into partitions called slices
|
||||
which are assigned to clients. Clients can query the slice details, activate
|
||||
and deactivate them.
|
||||
|
||||
Properties:
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be "qcom,sdm845-llcc"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value Type: <prop-encoded-array>
|
||||
Definition: The first element specifies the llcc base start address and
|
||||
the size of the register region. The second element specifies
|
||||
the llcc broadcast base address and size of the register region.
|
||||
|
||||
- reg-names:
|
||||
Usage: required
|
||||
Value Type: <stringlist>
|
||||
Definition: Register region names. Must be "llcc_base", "llcc_broadcast_base".
|
||||
|
||||
- interrupts:
|
||||
Usage: required
|
||||
Definition: The interrupt is associated with the llcc edac device.
|
||||
It's used for llcc cache single and double bit error detection
|
||||
and reporting.
|
||||
|
||||
Example:
|
||||
|
||||
cache-controller@1100000 {
|
||||
compatible = "qcom,sdm845-llcc";
|
||||
reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
|
||||
reg-names = "llcc_base", "llcc_broadcast_base";
|
||||
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
55
Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
Normal file
55
Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
Normal file
@@ -0,0 +1,55 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Last Level Cache Controller
|
||||
|
||||
maintainers:
|
||||
- Rishabh Bhatnagar <rishabhb@codeaurora.org>
|
||||
- Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
|
||||
|
||||
description: |
|
||||
LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
|
||||
that can be shared by multiple clients. Clients here are different cores in the
|
||||
SoC, the idea is to minimize the local caches at the clients and migrate to
|
||||
common pool of memory. Cache memory is divided into partitions called slices
|
||||
which are assigned to clients. Clients can query the slice details, activate
|
||||
and deactivate them.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc7180-llcc
|
||||
- qcom,sdm845-llcc
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: LLCC base register region
|
||||
- description: LLCC broadcast base register region
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: llcc_base
|
||||
- const: llcc_broadcast_base
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
cache-controller@1100000 {
|
||||
compatible = "qcom,sdm845-llcc";
|
||||
reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
|
||||
reg-names = "llcc_base", "llcc_broadcast_base";
|
||||
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
29
Documentation/devicetree/bindings/arm/omap/prm-inst.txt
Normal file
29
Documentation/devicetree/bindings/arm/omap/prm-inst.txt
Normal file
@@ -0,0 +1,29 @@
|
||||
OMAP PRM instance bindings
|
||||
|
||||
Power and Reset Manager is an IP block on OMAP family of devices which
|
||||
handle the power domains and their current state, and provide reset
|
||||
handling for the domains and/or separate IP blocks under the power domain
|
||||
hierarchy.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must contain one of the following:
|
||||
"ti,am3-prm-inst"
|
||||
"ti,am4-prm-inst"
|
||||
"ti,omap4-prm-inst"
|
||||
"ti,omap5-prm-inst"
|
||||
"ti,dra7-prm-inst"
|
||||
and additionally must contain:
|
||||
"ti,omap-prm-inst"
|
||||
- reg: Contains PRM instance register address range
|
||||
(base address and length)
|
||||
|
||||
Optional properties:
|
||||
- #reset-cells: Should be 1 if the PRM instance in question supports resets.
|
||||
|
||||
Example:
|
||||
|
||||
prm_dsp2: prm@1b00 {
|
||||
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1b00 0x40>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@@ -11,7 +11,9 @@ power management service, FPGA service and other platform management
|
||||
services.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must contain: "xlnx,zynqmp-firmware"
|
||||
- compatible: Must contain any of below:
|
||||
"xlnx,zynqmp-firmware" for Zynq Ultrascale+ MPSoC
|
||||
"xlnx,versal-firmware" for Versal
|
||||
- method: The method of calling the PM-API firmware layer.
|
||||
Permitted values are:
|
||||
- "smc" : SMC #0, following the SMCCC
|
||||
@@ -21,6 +23,8 @@ Required properties:
|
||||
Example
|
||||
-------
|
||||
|
||||
Zynq Ultrascale+ MPSoC
|
||||
----------------------
|
||||
firmware {
|
||||
zynqmp_firmware: zynqmp-firmware {
|
||||
compatible = "xlnx,zynqmp-firmware";
|
||||
@@ -28,3 +32,13 @@ firmware {
|
||||
...
|
||||
};
|
||||
};
|
||||
|
||||
Versal
|
||||
------
|
||||
firmware {
|
||||
versal_firmware: versal-firmware {
|
||||
compatible = "xlnx,versal-firmware";
|
||||
method = "smc";
|
||||
...
|
||||
};
|
||||
};
|
||||
|
||||
@@ -4,6 +4,7 @@ Required properties:
|
||||
- compatible: should be "amlogic,meson-gxbb-efuse"
|
||||
- clocks: phandle to the efuse peripheral clock provided by the
|
||||
clock controller.
|
||||
- secure-monitor: phandle to the secure-monitor node
|
||||
|
||||
= Data cells =
|
||||
Are child nodes of eFuse, bindings of which as described in
|
||||
@@ -16,6 +17,7 @@ Example:
|
||||
clocks = <&clkc CLKID_EFUSE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
secure-monitor = <&sm>;
|
||||
|
||||
sn: sn@14 {
|
||||
reg = <0x14 0x10>;
|
||||
@@ -30,6 +32,10 @@ Example:
|
||||
};
|
||||
};
|
||||
|
||||
sm: secure-monitor {
|
||||
compatible = "amlogic,meson-gxbb-sm";
|
||||
};
|
||||
|
||||
= Data consumers =
|
||||
Are device nodes which consume nvmem data cells.
|
||||
|
||||
|
||||
@@ -5,6 +5,7 @@ which then translates it into a corresponding voltage on a rail
|
||||
|
||||
Required Properties:
|
||||
- compatible: Should be one of the following
|
||||
* qcom,msm8976-rpmpd: RPM Power domain for the msm8976 family of SoC
|
||||
* qcom,msm8996-rpmpd: RPM Power domain for the msm8996 family of SoC
|
||||
* qcom,msm8998-rpmpd: RPM Power domain for the msm8998 family of SoC
|
||||
* qcom,qcs404-rpmpd: RPM Power domain for the qcs404 family of SoC
|
||||
|
||||
@@ -4,7 +4,8 @@ The Amlogic Audio ARB is a simple device which enables or
|
||||
disables the access of Audio FIFOs to DDR on AXG based SoC.
|
||||
|
||||
Required properties:
|
||||
- compatible: 'amlogic,meson-axg-audio-arb'
|
||||
- compatible: 'amlogic,meson-axg-audio-arb' or
|
||||
'amlogic,meson-sm1-audio-arb'
|
||||
- reg: physical base address of the controller and length of memory
|
||||
mapped region.
|
||||
- clocks: phandle to the fifo peripheral clock provided by the audio
|
||||
|
||||
@@ -16,6 +16,7 @@ properties:
|
||||
- amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs
|
||||
- amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs
|
||||
- amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
|
||||
- amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@@ -1,52 +0,0 @@
|
||||
Qualcomm AOSS Reset Controller
|
||||
======================================
|
||||
|
||||
This binding describes a reset-controller found on AOSS-CC (always on subsystem)
|
||||
for Qualcomm SDM845 SoCs.
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be:
|
||||
"qcom,sdm845-aoss-cc"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: must specify the base address and size of the register
|
||||
space.
|
||||
|
||||
- #reset-cells:
|
||||
Usage: required
|
||||
Value type: <uint>
|
||||
Definition: must be 1; cell entry represents the reset index.
|
||||
|
||||
Example:
|
||||
|
||||
aoss_reset: reset-controller@c2a0000 {
|
||||
compatible = "qcom,sdm845-aoss-cc";
|
||||
reg = <0xc2a0000 0x31000>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Specifying reset lines connected to IP modules
|
||||
==============================================
|
||||
|
||||
Device nodes that need access to reset lines should
|
||||
specify them as a reset phandle in their corresponding node as
|
||||
specified in reset.txt.
|
||||
|
||||
For list of all valid reset indicies see
|
||||
<dt-bindings/reset/qcom,sdm845-aoss.h>
|
||||
|
||||
Example:
|
||||
|
||||
modem-pil@4080000 {
|
||||
...
|
||||
|
||||
resets = <&aoss_reset AOSS_CC_MSS_RESTART>;
|
||||
reset-names = "mss_restart";
|
||||
|
||||
...
|
||||
};
|
||||
47
Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml
Normal file
47
Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml
Normal file
@@ -0,0 +1,47 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/reset/qcom,aoss-reset.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm AOSS Reset Controller
|
||||
|
||||
maintainers:
|
||||
- Sibi Sankar <sibis@codeaurora.org>
|
||||
|
||||
description:
|
||||
The bindings describe the reset-controller found on AOSS-CC (always on
|
||||
subsystem) for Qualcomm Technologies Inc SoCs.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: on SC7180 SoCs the following compatibles must be specified
|
||||
items:
|
||||
- const: "qcom,sc7180-aoss-cc"
|
||||
- const: "qcom,sdm845-aoss-cc"
|
||||
|
||||
- description: on SDM845 SoCs the following compatibles must be specified
|
||||
items:
|
||||
- const: "qcom,sdm845-aoss-cc"
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
aoss_reset: reset-controller@c2a0000 {
|
||||
compatible = "qcom,sdm845-aoss-cc";
|
||||
reg = <0xc2a0000 0x31000>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@@ -1,52 +0,0 @@
|
||||
PDC Global
|
||||
======================================
|
||||
|
||||
This binding describes a reset-controller found on PDC-Global (Power Domain
|
||||
Controller) block for Qualcomm Technologies Inc SDM845 SoCs.
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be:
|
||||
"qcom,sdm845-pdc-global"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: must specify the base address and size of the register
|
||||
space.
|
||||
|
||||
- #reset-cells:
|
||||
Usage: required
|
||||
Value type: <uint>
|
||||
Definition: must be 1; cell entry represents the reset index.
|
||||
|
||||
Example:
|
||||
|
||||
pdc_reset: reset-controller@b2e0000 {
|
||||
compatible = "qcom,sdm845-pdc-global";
|
||||
reg = <0xb2e0000 0x20000>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
PDC reset clients
|
||||
======================================
|
||||
|
||||
Device nodes that need access to reset lines should
|
||||
specify them as a reset phandle in their corresponding node as
|
||||
specified in reset.txt.
|
||||
|
||||
For a list of all valid reset indices see
|
||||
<dt-bindings/reset/qcom,sdm845-pdc.h>
|
||||
|
||||
Example:
|
||||
|
||||
modem-pil@4080000 {
|
||||
...
|
||||
|
||||
resets = <&pdc_reset PDC_MODEM_SYNC_RESET>;
|
||||
reset-names = "pdc_reset";
|
||||
|
||||
...
|
||||
};
|
||||
47
Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml
Normal file
47
Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml
Normal file
@@ -0,0 +1,47 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/reset/qcom,pdc-global.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm PDC Global
|
||||
|
||||
maintainers:
|
||||
- Sibi Sankar <sibis@codeaurora.org>
|
||||
|
||||
description:
|
||||
The bindings describes the reset-controller found on PDC-Global (Power Domain
|
||||
Controller) block for Qualcomm Technologies Inc SoCs.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: on SC7180 SoCs the following compatibles must be specified
|
||||
items:
|
||||
- const: "qcom,sc7180-pdc-global"
|
||||
- const: "qcom,sdm845-pdc-global"
|
||||
|
||||
- description: on SDM845 SoCs the following compatibles must be specified
|
||||
items:
|
||||
- const: "qcom,sdm845-pdc-global"
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pdc_reset: reset-controller@b2e0000 {
|
||||
compatible = "qcom,sdm845-pdc-global";
|
||||
reg = <0xb2e0000 0x20000>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@@ -130,6 +130,7 @@ this layer. These clocks and resets should be described in each property.
|
||||
Required properties:
|
||||
- compatible: Should be
|
||||
"socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3
|
||||
"socionext,uniphier-pro5-usb3-reset" - for Pro5 SoC USB3
|
||||
"socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3
|
||||
"socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3
|
||||
"socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3
|
||||
@@ -141,12 +142,12 @@ Required properties:
|
||||
- clocks: A list of phandles to the clock gate for the glue layer.
|
||||
According to the clock-names, appropriate clocks are required.
|
||||
- clock-names: Should contain
|
||||
"gio", "link" - for Pro4 SoC
|
||||
"gio", "link" - for Pro4 and Pro5 SoCs
|
||||
"link" - for others
|
||||
- resets: A list of phandles to the reset control for the glue layer.
|
||||
According to the reset-names, appropriate resets are required.
|
||||
- reset-names: Should contain
|
||||
"gio", "link" - for Pro4 SoC
|
||||
"gio", "link" - for Pro4 and Pro5 SoCs
|
||||
"link" - for others
|
||||
|
||||
Example:
|
||||
|
||||
@@ -5,7 +5,7 @@ and power management.
|
||||
|
||||
Required properites:
|
||||
- reg : Offset and length of the register set of the RCPM block.
|
||||
- fsl,#rcpm-wakeup-cells : The number of IPPDEXPCR register cells in the
|
||||
- #fsl,rcpm-wakeup-cells : The number of IPPDEXPCR register cells in the
|
||||
fsl,rcpm-wakeup property.
|
||||
- compatible : Must contain a chip-specific RCPM block compatible string
|
||||
and (if applicable) may contain a chassis-version RCPM compatible
|
||||
@@ -20,6 +20,7 @@ Required properites:
|
||||
* "fsl,qoriq-rcpm-1.0": for chassis 1.0 rcpm
|
||||
* "fsl,qoriq-rcpm-2.0": for chassis 2.0 rcpm
|
||||
* "fsl,qoriq-rcpm-2.1": for chassis 2.1 rcpm
|
||||
* "fsl,qoriq-rcpm-2.1+": for chassis 2.1+ rcpm
|
||||
|
||||
All references to "1.0" and "2.0" refer to the QorIQ chassis version to
|
||||
which the chip complies.
|
||||
@@ -27,14 +28,19 @@ Chassis Version Example Chips
|
||||
--------------- -------------------------------
|
||||
1.0 p4080, p5020, p5040, p2041, p3041
|
||||
2.0 t4240, b4860, b4420
|
||||
2.1 t1040, ls1021
|
||||
2.1 t1040,
|
||||
2.1+ ls1021a, ls1012a, ls1043a, ls1046a
|
||||
|
||||
Optional properties:
|
||||
- little-endian : RCPM register block is Little Endian. Without it RCPM
|
||||
will be Big Endian (default case).
|
||||
|
||||
Example:
|
||||
The RCPM node for T4240:
|
||||
rcpm: global-utilities@e2000 {
|
||||
compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0";
|
||||
reg = <0xe2000 0x1000>;
|
||||
fsl,#rcpm-wakeup-cells = <2>;
|
||||
#fsl,rcpm-wakeup-cells = <2>;
|
||||
};
|
||||
|
||||
* Freescale RCPM Wakeup Source Device Tree Bindings
|
||||
@@ -44,7 +50,7 @@ can be used as a wakeup source.
|
||||
|
||||
- fsl,rcpm-wakeup: Consists of a phandle to the rcpm node and the IPPDEXPCR
|
||||
register cells. The number of IPPDEXPCR register cells is defined in
|
||||
"fsl,#rcpm-wakeup-cells" in the rcpm node. The first register cell is
|
||||
"#fsl,rcpm-wakeup-cells" in the rcpm node. The first register cell is
|
||||
the bit mask that should be set in IPPDEXPCR0, and the second register
|
||||
cell is for IPPDEXPCR1, and so on.
|
||||
|
||||
|
||||
@@ -22,6 +22,7 @@ resources.
|
||||
"qcom,rpm-apq8084"
|
||||
"qcom,rpm-msm8916"
|
||||
"qcom,rpm-msm8974"
|
||||
"qcom,rpm-msm8976"
|
||||
"qcom,rpm-msm8998"
|
||||
"qcom,rpm-sdm660"
|
||||
"qcom,rpm-qcs404"
|
||||
|
||||
17
MAINTAINERS
17
MAINTAINERS
@@ -2140,6 +2140,7 @@ S: Maintained
|
||||
|
||||
ARM/QUALCOMM SUPPORT
|
||||
M: Andy Gross <agross@kernel.org>
|
||||
M: Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
L: linux-arm-msm@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/soc/qcom/
|
||||
@@ -5001,6 +5002,14 @@ F: include/linux/dma-direct.h
|
||||
F: include/linux/dma-mapping.h
|
||||
F: include/linux/dma-noncoherent.h
|
||||
|
||||
DMC FREQUENCY DRIVER FOR SAMSUNG EXYNOS5422
|
||||
M: Lukasz Luba <l.luba@partner.samsung.com>
|
||||
L: linux-pm@vger.kernel.org
|
||||
L: linux-samsung-soc@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/memory/samsung/exynos5422-dmc.c
|
||||
F: Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
|
||||
|
||||
DME1737 HARDWARE MONITOR DRIVER
|
||||
M: Juerg Haefliger <juergh@gmail.com>
|
||||
L: linux-hwmon@vger.kernel.org
|
||||
@@ -11066,6 +11075,13 @@ F: arch/arm/boot/dts/mmp*
|
||||
F: arch/arm/mach-mmp/
|
||||
F: linux/soc/mmp/
|
||||
|
||||
MMP USB PHY DRIVERS
|
||||
R: Lubomir Rintel <lkundrak@v3.sk>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: drivers/phy/marvell/phy-mmp3-usb.c
|
||||
F: drivers/phy/marvell/phy-pxa-usb.c
|
||||
|
||||
MMU GATHER AND TLB INVALIDATION
|
||||
M: Will Deacon <will@kernel.org>
|
||||
M: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
|
||||
@@ -14033,6 +14049,7 @@ F: include/dt-bindings/reset/
|
||||
F: include/linux/reset.h
|
||||
F: include/linux/reset/
|
||||
F: include/linux/reset-controller.h
|
||||
K: \b(?:devm_|of_)?reset_control(?:ler_[a-z]+|_[a-z_]+)?\b
|
||||
|
||||
RESTARTABLE SEQUENCES SUPPORT
|
||||
M: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
|
||||
|
||||
@@ -109,6 +109,7 @@ config ARCH_OMAP2PLUS
|
||||
select TI_SYSC
|
||||
select OMAP_IRQCHIP
|
||||
select CLKSRC_TI_32K
|
||||
select ARCH_HAS_RESET_CONTROLLER
|
||||
help
|
||||
Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
|
||||
|
||||
|
||||
@@ -247,6 +247,60 @@ void wakeup_source_unregister(struct wakeup_source *ws)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(wakeup_source_unregister);
|
||||
|
||||
/**
|
||||
* wakeup_sources_read_lock - Lock wakeup source list for read.
|
||||
*
|
||||
* Returns an index of srcu lock for struct wakeup_srcu.
|
||||
* This index must be passed to the matching wakeup_sources_read_unlock().
|
||||
*/
|
||||
int wakeup_sources_read_lock(void)
|
||||
{
|
||||
return srcu_read_lock(&wakeup_srcu);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(wakeup_sources_read_lock);
|
||||
|
||||
/**
|
||||
* wakeup_sources_read_unlock - Unlock wakeup source list.
|
||||
* @idx: return value from corresponding wakeup_sources_read_lock()
|
||||
*/
|
||||
void wakeup_sources_read_unlock(int idx)
|
||||
{
|
||||
srcu_read_unlock(&wakeup_srcu, idx);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(wakeup_sources_read_unlock);
|
||||
|
||||
/**
|
||||
* wakeup_sources_walk_start - Begin a walk on wakeup source list
|
||||
*
|
||||
* Returns first object of the list of wakeup sources.
|
||||
*
|
||||
* Note that to be safe, wakeup sources list needs to be locked by calling
|
||||
* wakeup_source_read_lock() for this.
|
||||
*/
|
||||
struct wakeup_source *wakeup_sources_walk_start(void)
|
||||
{
|
||||
struct list_head *ws_head = &wakeup_sources;
|
||||
|
||||
return list_entry_rcu(ws_head->next, struct wakeup_source, entry);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(wakeup_sources_walk_start);
|
||||
|
||||
/**
|
||||
* wakeup_sources_walk_next - Get next wakeup source from the list
|
||||
* @ws: Previous wakeup source object
|
||||
*
|
||||
* Note that to be safe, wakeup sources list needs to be locked by calling
|
||||
* wakeup_source_read_lock() for this.
|
||||
*/
|
||||
struct wakeup_source *wakeup_sources_walk_next(struct wakeup_source *ws)
|
||||
{
|
||||
struct list_head *ws_head = &wakeup_sources;
|
||||
|
||||
return list_next_or_null_rcu(ws_head, &ws->entry,
|
||||
struct wakeup_source, entry);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(wakeup_sources_walk_next);
|
||||
|
||||
/**
|
||||
* device_wakeup_attach - Attach a wakeup source object to a device object.
|
||||
* @dev: Device to handle.
|
||||
|
||||
@@ -41,8 +41,9 @@ config MOXTET
|
||||
|
||||
config HISILICON_LPC
|
||||
bool "Support for ISA I/O space on HiSilicon Hip06/7"
|
||||
depends on ARM64 && (ARCH_HISI || COMPILE_TEST)
|
||||
select INDIRECT_PIO
|
||||
depends on (ARM64 && ARCH_HISI) || (COMPILE_TEST && !ALPHA && !HEXAGON && !PARISC && !C6X)
|
||||
depends on HAS_IOMEM
|
||||
select INDIRECT_PIO if ARM64
|
||||
help
|
||||
Driver to enable I/O access to devices attached to the Low Pin
|
||||
Count bus on the HiSilicon Hip06/7 SoC.
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user