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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Browse Source 
Pull MIPS updates from Ralf Baechle:
 "These are the highlists of the main MIPS pull request for 4.4:

   - Add latencytop support
   - Support appended DTBs
   - VDSO support and initially use it for gettimeofday.
   - Drop the .MIPS.abiflags and ELF NOTE sections from vmlinux
   - Support for the 5KE, an internal test core.
   - Switch all MIPS platfroms to libata drivers.
   - Improved support, cleanups for ralink and Lantiq platforms.
   - Support for the new xilfpga platform.
   - A number of DTB improvments for BMIPS.
   - Improved support for CM and CPS.
   - Minor JZ4740 and BCM47xx enhancements"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (120 commits)
  MIPS: idle: add case for CPU_5KE
  MIPS: Octeon: Support APPENDED_DTB
  MIPS: vmlinux: create a section for appended DTB
  MIPS: Clean up compat_siginfo_t
  MIPS: Fix PAGE_MASK definition
  MIPS: BMIPS: Enable GZIP ramdisk and timed printks
  MIPS: Add xilfpga defconfig
  MIPS: xilfpga: Add mipsfpga platform code
  MIPS: xilfpga: Add xilfpga device tree files.
  dt-bindings: MIPS: Document xilfpga bindings and boot style
  MIPS: Make MIPS_CMDLINE_DTB default
  MIPS: Make the kernel arguments from dtb available
  MIPS: Use USE_OF as the guard for appended dtb
  MIPS: BCM63XX: Use pr_* instead of printk
  MIPS: Loongson: Cleanup CONFIG_LOONGSON_SUSPEND.
  MIPS: lantiq: Disable xbar fpi burst mode
  MIPS: lantiq: Force the crossbar to big endian
  MIPS: lantiq: Initialize the USB core on boot
  MIPS: lantiq: Return correct value for fpi clock on ar9
  MIPS: ralink: Add missing clock on rt305x
  ...
This commit is contained in:
Linus Torvalds
2015-11-15 09:10:53 -08:00
parent 12b76f3bf3 da34232641
commit b84da9fa47
151 changed files with 4596 additions and 755 deletions
Download Patch File Download Diff File Expand all files Collapse all files

83
Documentation/devicetree/bindings/mips/img/xilfpga.txt Normal file
View File

@@ -0,0 +1,83 @@
Imagination University Program MIPSfpga
=======================================
Under the Imagination University Program, a microAptiv UP core has been
released for academic usage.
As we are dealing with a MIPS core instantiated on an FPGA, specifications
are fluid and can be varied in RTL.
This binding document is provided as baseline guidance for the example
project provided by IMG.
The example project runs on the Nexys4DDR board by Digilent powered by
the ARTIX-7 FPGA by Xilinx.
Relevant details about the example project and the Nexys4DDR board:
- microAptiv UP core m14Kc
- 50MHz clock speed
- 128Mbyte DDR RAM at 0x0000_0000
- 8Kbyte RAM at 0x1000_0000
- axi_intc at 0x1020_0000
- axi_uart16550 at 0x1040_0000
- axi_gpio at 0x1060_0000
- axi_i2c at 0x10A0_0000
- custom_gpio at 0x10C0_0000
- axi_ethernetlite at 0x10E0_0000
- 8Kbyte BootRAM at 0x1FC0_0000
Required properties:
--------------------
- compatible: Must include "digilent,nexys4ddr","img,xilfpga".
CPU nodes:
----------
A "cpus" node is required. Required properties:
- #address-cells: Must be 1.
- #size-cells: Must be 0.
A CPU sub-node is also required for at least CPU 0. Required properties:
- device_type: Must be "cpu".
- compatible: Must be "mips,m14Kc".
- reg: Must be <0>.
- clocks: phandle to ext clock for fixed-clock received by MIPS core.
Example:
compatible = "img,xilfpga","digilent,nexys4ddr";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "mips,m14Kc";
reg = <0>;
clocks = <&ext>;
};
};
ext: ext {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
};
Boot protocol:
--------------
The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000.
This is for easy reprogrammibility via JTAG.
The BootRAM initializes the cache and the axi_uart peripheral.
DDR initialization is already handled by a HW IP block.
When the example project bitstream is loaded, the cpu_reset button
needs to be pressed.
The bootram initializes the cache and axi_uart.
Then outputs MIPSFPGA\n\r on the serial port on the Nexys4DDR board.
At this point, the board is ready to load the Linux kernel
vmlinux file via JTAG.

1
arch/mips/Kbuild
View File

@@ -17,6 +17,7 @@ obj- := $(platform-)
obj-y += kernel/
obj-y += mm/
obj-y += net/
obj-y += vdso/
ifdef CONFIG_KVM
obj-y += kvm/

1
arch/mips/Kbuild.platforms
View File

@@ -33,6 +33,7 @@ platforms += sibyte
platforms += sni
platforms += txx9
platforms += vr41xx
platforms += xilfpga
# include the platform specific files
include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms))

88
arch/mips/Kconfig
View File

@@ -5,6 +5,7 @@ config MIPS
select ARCH_MIGHT_HAVE_PC_PARPORT
select ARCH_MIGHT_HAVE_PC_SERIO
select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
select ARCH_USE_BUILTIN_BSWAP
select HAVE_CONTEXT_TRACKING
select HAVE_GENERIC_DMA_COHERENT
select HAVE_IDE
@@ -60,6 +61,8 @@ config MIPS
select SYSCTL_EXCEPTION_TRACE
select HAVE_VIRT_CPU_ACCOUNTING_GEN
select HAVE_IRQ_TIME_ACCOUNTING
select GENERIC_TIME_VSYSCALL
select ARCH_CLOCKSOURCE_DATA
menu "Machine selection"
@@ -401,6 +404,28 @@ config MACH_PISTACHIO
help
This enables support for the IMG Pistachio SoC platform.
config MACH_XILFPGA
bool "MIPSfpga Xilinx based boards"
select ARCH_REQUIRE_GPIOLIB
select BOOT_ELF32
select BOOT_RAW
select BUILTIN_DTB
select CEVT_R4K
select COMMON_CLK
select CSRC_R4K
select IRQ_MIPS_CPU
select LIBFDT
select MIPS_CPU_SCACHE
select SYS_HAS_EARLY_PRINTK
select SYS_HAS_CPU_MIPS32_R2
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_ZBOOT_UART16550
select USE_OF
select USE_GENERIC_EARLY_PRINTK_8250
help
This enables support for the IMG University Program MIPSfpga platform.
config MIPS_MALTA
bool "MIPS Malta board"
select ARCH_MAY_HAVE_PC_FDC
@@ -424,6 +449,7 @@ config MIPS_MALTA
select MIPS_L1_CACHE_SHIFT_6
select PCI_GT64XXX_PCI0
select MIPS_MSC
select SMP_UP if SMP
select SWAP_IO_SPACE
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS32_R2
@@ -449,6 +475,8 @@ config MIPS_MALTA
select SYS_SUPPORTS_ZBOOT
select USE_OF
select ZONE_DMA32 if 64BIT
select BUILTIN_DTB
select LIBFDT
help
This enables support for the MIPS Technologies Malta evaluation
board.
@@ -964,6 +992,7 @@ source "arch/mips/loongson32/Kconfig"
source "arch/mips/loongson64/Kconfig"
source "arch/mips/netlogic/Kconfig"
source "arch/mips/paravirt/Kconfig"
source "arch/mips/xilfpga/Kconfig"
endmenu
@@ -1036,6 +1065,9 @@ config CSRC_R4K
config CSRC_SB1250
bool
config MIPS_CLOCK_VSYSCALL
def_bool CSRC_R4K || CLKSRC_MIPS_GIC
config GPIO_TXX9
select ARCH_REQUIRE_GPIOLIB
bool
@@ -2529,6 +2561,9 @@ choice
help
Allows the configuration of the timer frequency.
config HZ_24
bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
config HZ_48
bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
@@ -2552,6 +2587,9 @@ choice
endchoice
config SYS_SUPPORTS_24HZ
bool
config SYS_SUPPORTS_48HZ
bool
@@ -2575,13 +2613,18 @@ config SYS_SUPPORTS_1024HZ
config SYS_SUPPORTS_ARBIT_HZ
bool
default y if !SYS_SUPPORTS_48HZ && !SYS_SUPPORTS_100HZ && \
!SYS_SUPPORTS_128HZ && !SYS_SUPPORTS_250HZ && \
!SYS_SUPPORTS_256HZ && !SYS_SUPPORTS_1000HZ && \
default y if !SYS_SUPPORTS_24HZ && \
!SYS_SUPPORTS_48HZ && \
!SYS_SUPPORTS_100HZ && \
!SYS_SUPPORTS_128HZ && \
!SYS_SUPPORTS_250HZ && \
!SYS_SUPPORTS_256HZ && \
!SYS_SUPPORTS_1000HZ && \
!SYS_SUPPORTS_1024HZ
config HZ
int
default 24 if HZ_24
default 48 if HZ_48
default 100 if HZ_100
default 128 if HZ_128
@@ -2685,7 +2728,7 @@ config BUILTIN_DTB
bool
choice
prompt "Kernel appended dtb support" if OF
prompt "Kernel appended dtb support" if USE_OF
default MIPS_NO_APPENDED_DTB
config MIPS_NO_APPENDED_DTB
@@ -2693,6 +2736,20 @@ choice
help
Do not enable appended dtb support.
config MIPS_ELF_APPENDED_DTB
bool "vmlinux"
help
With this option, the boot code will look for a device tree binary
DTB) included in the vmlinux ELF section .appended_dtb. By default
it is empty and the DTB can be appended using binutils command
objcopy:
objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
This is meant as a backward compatiblity convenience for those
systems with a bootloader that can't be upgraded to accommodate
the documented boot protocol using a device tree.
config MIPS_RAW_APPENDED_DTB
bool "vmlinux.bin"
help
@@ -2729,6 +2786,25 @@ choice
if you don't intend to always append a DTB.
endchoice
choice
prompt "Kernel command line type" if !CMDLINE_OVERRIDE
default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
!MIPS_MALTA && !MIPS_SEAD3 && \
!CAVIUM_OCTEON_SOC
default MIPS_CMDLINE_FROM_BOOTLOADER
config MIPS_CMDLINE_FROM_DTB
depends on USE_OF
bool "Dtb kernel arguments if available"
config MIPS_CMDLINE_DTB_EXTEND
depends on USE_OF
bool "Extend dtb kernel arguments with bootloader arguments"
config MIPS_CMDLINE_FROM_BOOTLOADER
bool "Bootloader kernel arguments if available"
endchoice
endmenu
config LOCKDEP_SUPPORT
@@ -2739,6 +2815,10 @@ config STACKTRACE_SUPPORT
bool
default y
config HAVE_LATENCYTOP_SUPPORT
bool
default y
config PGTABLE_LEVELS
int
default 3 if 64BIT && !PAGE_SIZE_64KB

72
arch/mips/Kconfig.debug
View File

@@ -113,4 +113,76 @@ config SPINLOCK_TEST
help
Add several files to the debugfs to test spinlock speed.
if CPU_MIPSR6
choice
prompt "Compact branch policy"
default MIPS_COMPACT_BRANCHES_OPTIMAL
config MIPS_COMPACT_BRANCHES_NEVER
bool "Never (force delay slot branches)"
help
Pass the -mcompact-branches=never flag to the compiler in order to
force it to always emit branches with delay slots, and make no use
of the compact branch instructions introduced by MIPSr6. This is
useful if you suspect there may be an issue with compact branches in
either the compiler or the CPU.
config MIPS_COMPACT_BRANCHES_OPTIMAL
bool "Optimal (use where beneficial)"
help
Pass the -mcompact-branches=optimal flag to the compiler in order for
it to make use of compact branch instructions where it deems them
beneficial, and use branches with delay slots elsewhere. This is the
default compiler behaviour, and should be used unless you have a
reason to choose otherwise.
config MIPS_COMPACT_BRANCHES_ALWAYS
bool "Always (force compact branches)"
help
Pass the -mcompact-branches=always flag to the compiler in order to
force it to always emit compact branches, making no use of branch
instructions with delay slots. This can result in more compact code
which may be beneficial in some scenarios.
endchoice
endif # CPU_MIPSR6
config SCACHE_DEBUGFS
bool "L2 cache debugfs entries"
depends on DEBUG_FS
help
Enable this to allow parts of the L2 cache configuration, such as
whether or not prefetching is enabled, to be exposed to userland
via debugfs.
If unsure, say N.
menuconfig MIPS_CPS_NS16550
bool "CPS SMP NS16550 UART output"
depends on MIPS_CPS
help
Output debug information via an ns16550 compatible UART if exceptions
occur early in the boot process of a secondary core.
if MIPS_CPS_NS16550
config MIPS_CPS_NS16550_BASE
hex "UART Base Address"
default 0x1b0003f8 if MIPS_MALTA
help
The base address of the ns16550 compatible UART on which to output
debug information from the early stages of core startup.
config MIPS_CPS_NS16550_SHIFT
int "UART Register Shift"
default 0 if MIPS_MALTA
help
The number of bits to shift ns16550 register indices by in order to
form their addresses. That is, log base 2 of the span between
adjacent ns16550 registers in the system.
endif # MIPS_CPS_NS16550
endmenu

4
arch/mips/Makefile
View File

@@ -204,6 +204,10 @@ toolchain-msa := $(call cc-option-yn,$(mips-cflags) -mhard-float -mfp64 -Wa$(
cflags-$(toolchain-msa) += -DTOOLCHAIN_SUPPORTS_MSA
endif
cflags-$(CONFIG_MIPS_COMPACT_BRANCHES_NEVER) += -mcompact-branches=never
cflags-$(CONFIG_MIPS_COMPACT_BRANCHES_OPTIMAL) += -mcompact-branches=optimal
cflags-$(CONFIG_MIPS_COMPACT_BRANCHES_ALWAYS) += -mcompact-branches=always
#
# Firmware support
#

19
arch/mips/bcm47xx/setup.c
View File

@@ -105,11 +105,28 @@ static int bcm47xx_get_invariants(struct ssb_bus *bus,
struct ssb_init_invariants *iv)
{
char buf[20];
int len, err;
/* Fill boardinfo structure */
memset(&iv->boardinfo, 0 , sizeof(struct ssb_boardinfo));
bcm47xx_fill_ssb_boardinfo(&iv->boardinfo, NULL);
len = bcm47xx_nvram_getenv("boardvendor", buf, sizeof(buf));
if (len > 0) {
err = kstrtou16(strim(buf), 0, &iv->boardinfo.vendor);
if (err)
pr_warn("Couldn't parse nvram board vendor entry with value \"%s\"\n",
buf);
}
if (!iv->boardinfo.vendor)
iv->boardinfo.vendor = SSB_BOARDVENDOR_BCM;
len = bcm47xx_nvram_getenv("boardtype", buf, sizeof(buf));
if (len > 0) {
err = kstrtou16(strim(buf), 0, &iv->boardinfo.type);
if (err)
pr_warn("Couldn't parse nvram board type entry with value \"%s\"\n",
buf);
}
memset(&iv->sprom, 0, sizeof(struct ssb_sprom));
bcm47xx_fill_sprom(&iv->sprom, NULL, false);

46
arch/mips/bcm47xx/sprom.c
View File

@@ -60,9 +60,9 @@ static int get_nvram_var(const char *prefix, const char *postfix,
}
#define NVRAM_READ_VAL(type) \
static void nvram_read_ ## type (const char *prefix, \
const char *postfix, const char *name, \
type *val, type allset, bool fallback) \
static void nvram_read_ ## type(const char *prefix, \
const char *postfix, const char *name, \
type *val, type allset, bool fallback) \
{ \
char buf[100]; \
int err; \
@@ -422,7 +422,10 @@ static void bcm47xx_fill_sprom_path_r4589(struct ssb_sprom *sprom,
int i;
for (i = 0; i < ARRAY_SIZE(sprom->core_pwr_info); i++) {
struct ssb_sprom_core_pwr_info *pwr_info = &sprom->core_pwr_info[i];
struct ssb_sprom_core_pwr_info *pwr_info;
pwr_info = &sprom->core_pwr_info[i];
snprintf(postfix, sizeof(postfix), "%i", i);
nvram_read_u8(prefix, postfix, "maxp2ga",
&pwr_info->maxpwr_2g, 0, fallback);
@@ -470,7 +473,10 @@ static void bcm47xx_fill_sprom_path_r45(struct ssb_sprom *sprom,
int i;
for (i = 0; i < ARRAY_SIZE(sprom->core_pwr_info); i++) {
struct ssb_sprom_core_pwr_info *pwr_info = &sprom->core_pwr_info[i];
struct ssb_sprom_core_pwr_info *pwr_info;
pwr_info = &sprom->core_pwr_info[i];
snprintf(postfix, sizeof(postfix), "%i", i);
nvram_read_u16(prefix, postfix, "pa2gw3a",
&pwr_info->pa_2g[3], 0, fallback);
@@ -535,10 +541,11 @@ static void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom,
nvram_read_macaddr(prefix, "il0macaddr", sprom->il0mac, fallback);
/* The address prefix 00:90:4C is used by Broadcom in their initial
configuration. When a mac address with the prefix 00:90:4C is used
all devices from the same series are sharing the same mac address.
To prevent mac address collisions we replace them with a mac address
based on the base address. */
* configuration. When a mac address with the prefix 00:90:4C is used
* all devices from the same series are sharing the same mac address.
* To prevent mac address collisions we replace them with a mac address
* based on the base address.
*/
if (!bcm47xx_is_valid_mac(sprom->il0mac)) {
u8 mac[6];
@@ -592,32 +599,23 @@ void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix,
bcm47xx_sprom_fill_auto(sprom, prefix, fallback);
}
#ifdef CONFIG_BCM47XX_SSB
void bcm47xx_fill_ssb_boardinfo(struct ssb_boardinfo *boardinfo,
const char *prefix)
{
nvram_read_u16(prefix, NULL, "boardvendor", &boardinfo->vendor, 0,
true);
if (!boardinfo->vendor)
boardinfo->vendor = SSB_BOARDVENDOR_BCM;
nvram_read_u16(prefix, NULL, "boardtype", &boardinfo->type, 0, true);
}
#endif
#if defined(CONFIG_BCM47XX_SSB)
static int bcm47xx_get_sprom_ssb(struct ssb_bus *bus, struct ssb_sprom *out)
{
char prefix[10];
if (bus->bustype == SSB_BUSTYPE_PCI) {
switch (bus->bustype) {
case SSB_BUSTYPE_SSB:
bcm47xx_fill_sprom(out, NULL, false);
return 0;
case SSB_BUSTYPE_PCI:
memset(out, 0, sizeof(struct ssb_sprom));
snprintf(prefix, sizeof(prefix), "pci/%u/%u/",
bus->host_pci->bus->number + 1,
PCI_SLOT(bus->host_pci->devfn));
bcm47xx_fill_sprom(out, prefix, false);
return 0;
} else {
default:
pr_warn("Unable to fill SPROM for given bustype.\n");
return -EINVAL;
}

14
arch/mips/bcm63xx/boards/board_bcm963xx.c
View File

@@ -7,6 +7,8 @@
* Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/string.h>
@@ -31,7 +33,6 @@
#include <uapi/linux/bcm933xx_hcs.h>
#define PFX "board_bcm963xx: "
#define HCS_OFFSET_128K 0x20000
@@ -740,7 +741,7 @@ int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out)
memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom));
return 0;
} else {
printk(KERN_ERR PFX "unable to fill SPROM for given bustype.\n");
pr_err("unable to fill SPROM for given bustype\n");
return -EINVAL;
}
}
@@ -784,7 +785,7 @@ void __init board_prom_init(void)
cfe[5], cfe[6], cfe[7], cfe[8], cfe[9]);
else
strcpy(cfe_version, "unknown");
printk(KERN_INFO PFX "CFE version: %s\n", cfe_version);
pr_info("CFE version: %s\n", cfe_version);
bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET);
@@ -808,8 +809,7 @@ void __init board_prom_init(void)
char name[17];
memcpy(name, board_name, 16);
name[16] = 0;
printk(KERN_ERR PFX "unknown bcm963xx board: %s\n",
name);
pr_err("unknown bcm963xx board: %s\n", name);
return;
}
@@ -854,7 +854,7 @@ void __init board_setup(void)
{
if (!board.name[0])
panic("unable to detect bcm963xx board");
printk(KERN_INFO PFX "board name: %s\n", board.name);
pr_info("board name: %s\n", board.name);
/* make sure we're running on expected cpu */
if (bcm63xx_get_cpu_id() != board.expected_cpu_id)
@@ -910,7 +910,7 @@ int __init board_register_devices(void)
memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);
if (ssb_arch_register_fallback_sprom(
&bcm63xx_get_fallback_sprom) < 0)
pr_err(PFX "failed to register fallback SPROM\n");
pr_err("failed to register fallback SPROM\n");
}
#endif

12
arch/mips/bcm63xx/cpu.c
View File

@@ -376,10 +376,10 @@ void __init bcm63xx_cpu_init(void)
bcm63xx_cpu_freq = detect_cpu_clock();
bcm63xx_memory_size = detect_memory_size();
printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n",
bcm63xx_cpu_id, bcm63xx_cpu_rev);
printk(KERN_INFO "CPU frequency is %u MHz\n",
bcm63xx_cpu_freq / 1000000);
printk(KERN_INFO "%uMB of RAM installed\n",
bcm63xx_memory_size >> 20);
pr_info("Detected Broadcom 0x%04x CPU revision %02x\n",
bcm63xx_cpu_id, bcm63xx_cpu_rev);
pr_info("CPU frequency is %u MHz\n",
bcm63xx_cpu_freq / 1000000);
pr_info("%uMB of RAM installed\n",
bcm63xx_memory_size >> 20);
}

2
arch/mips/bcm63xx/dev-pcmcia.c
View File

@@ -139,6 +139,6 @@ int __init bcm63xx_pcmcia_register(void)
return platform_device_register(&bcm63xx_pcmcia_device);
out_err:
printk(KERN_ERR "unable to set pcmcia chip select\n");
pr_err("unable to set pcmcia chip select\n");
return ret;
}

2
arch/mips/bcm63xx/irq.c
View File

@@ -311,7 +311,7 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d,
break;
default:
printk(KERN_ERR "bogus flow type combination given !\n");
pr_err("bogus flow type combination given !\n");
return -EINVAL;
}

8
arch/mips/bcm63xx/setup.c
View File

@@ -24,7 +24,7 @@
void bcm63xx_machine_halt(void)
{
printk(KERN_INFO "System halted\n");
pr_info("System halted\n");
while (1)
;
}
@@ -34,7 +34,7 @@ static void bcm6348_a1_reboot(void)
u32 reg;
/* soft reset all blocks */
printk(KERN_INFO "soft-resetting all blocks ...\n");
pr_info("soft-resetting all blocks ...\n");
reg = bcm_perf_readl(PERF_SOFTRESET_REG);
reg &= ~SOFTRESET_6348_ALL;
bcm_perf_writel(reg, PERF_SOFTRESET_REG);
@@ -46,7 +46,7 @@ static void bcm6348_a1_reboot(void)
mdelay(10);
/* Jump to the power on address. */
printk(KERN_INFO "jumping to reset vector.\n");
pr_info("jumping to reset vector.\n");
/* set high vectors (base at 0xbfc00000 */
set_c0_status(ST0_BEV | ST0_ERL);
/* run uncached in kseg0 */
@@ -110,7 +110,7 @@ void bcm63xx_machine_reboot(void)
if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() == 0xa1))
bcm6348_a1_reboot();
printk(KERN_INFO "triggering watchdog soft-reset...\n");
pr_info("triggering watchdog soft-reset...\n");
if (BCMCPU_IS_6328()) {
bcm_wdt_writel(1, WDT_SOFTRESET_REG);
} else {

2
arch/mips/bcm63xx/timer.c
View File

@@ -195,7 +195,7 @@ int bcm63xx_timer_init(void)
irq = bcm63xx_get_irq_number(IRQ_TIMER);
ret = request_irq(irq, timer_interrupt, 0, "bcm63xx_timer", NULL);
if (ret) {
printk(KERN_ERR "bcm63xx_timer: failed to register irq\n");
pr_err("%s: failed to register irq\n", __func__);
return ret;
}

1
arch/mips/bmips/setup.c
View File

@@ -157,7 +157,6 @@ void __init plat_mem_setup(void)
panic("no dtb found");
__dt_setup_arch(dtb);
strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
for (q = bmips_quirk_list; q->quirk_fn; q++) {
if (of_flat_dt_is_compatible(of_get_flat_dt_root(),

1
arch/mips/boot/dts/Makefile
View File

@@ -6,6 +6,7 @@ dts-dirs += mti
dts-dirs += netlogic
dts-dirs += qca
dts-dirs += ralink
dts-dirs += xilfpga
obj-y := $(addsuffix /, $(dts-dirs))

114
arch/mips/boot/dts/brcm/bcm7346.dtsi
View File

@@ -87,14 +87,32 @@
compatible = "brcm,bcm7120-l2-intc";
reg = <0x406780 0x8>;
brcm,int-map-mask = <0x44>;
brcm,int-map-mask = <0x44>, <0xf000000>;
brcm,int-fwd-mask = <0x70000>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <59>;
interrupts = <59>, <57>;
interrupt-names = "upg_main", "upg_bsc";
};
upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
compatible = "brcm,bcm7120-l2-intc";
reg = <0x408b80 0x8>;
brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
brcm,int-fwd-mask = <0>;
brcm,irq-can-wake;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <60>, <58>, <62>;
interrupt-names = "upg_main_aon", "upg_bsc_aon",
"upg_spi";
};
sun_top_ctrl: syscon@404000 {
@@ -144,6 +162,56 @@
status = "disabled";
};
bsca: i2c@406200 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406200 0x58>;
interrupts = <24>;
interrupt-names = "upg_bsca";
status = "disabled";
};
bscb: i2c@406280 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406280 0x58>;
interrupts = <25>;
interrupt-names = "upg_bscb";
status = "disabled";
};
bscc: i2c@406300 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406300 0x58>;
interrupts = <26>;
interrupt-names = "upg_bscc";
status = "disabled";
};
bscd: i2c@406380 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406380 0x58>;
interrupts = <27>;
interrupt-names = "upg_bscd";
status = "disabled";
};
bsce: i2c@408980 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_aon_irq0_intc>;
reg = <0x408980 0x58>;
interrupts = <27>;
interrupt-names = "upg_bsce";
status = "disabled";
};
enet0: ethernet@430000 {
phy-mode = "internal";
phy-handle = <&phy1>;
@@ -246,5 +314,47 @@
interrupts = <76>;
status = "disabled";
};
sata: sata@181000 {
compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
reg-names = "ahci", "top-ctrl";
reg = <0x181000 0xa9c>, <0x180020 0x1c>;
interrupt-parent = <&periph_intc>;
interrupts = <40>;
#address-cells = <1>;
#size-cells = <0>;
brcm,broken-ncq;
brcm,broken-phy;
status = "disabled";
sata0: sata-port@0 {
reg = <0>;
phys = <&sata_phy0>;
};
sata1: sata-port@1 {
reg = <1>;
phys = <&sata_phy1>;
};
};
sata_phy: sata-phy@1800000 {
compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
reg = <0x180100 0x0eff>;
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata_phy0: sata-phy@0 {
reg = <0>;
#phy-cells = <0>;
};
sata_phy1: sata-phy@1 {
reg = <1>;
#phy-cells = <0>;
};
};
};
};

62
arch/mips/boot/dts/brcm/bcm7358.dtsi
View File

@@ -81,14 +81,32 @@
compatible = "brcm,bcm7120-l2-intc";
reg = <0x406600 0x8>;
brcm,int-map-mask = <0x44>;
brcm,int-map-mask = <0x44>, <0x7000000>;
brcm,int-fwd-mask = <0x70000>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <56>;
interrupts = <56>, <54>;
interrupt-names = "upg_main", "upg_bsc";
};
upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
compatible = "brcm,bcm7120-l2-intc";
reg = <0x408b80 0x8>;
brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
brcm,int-fwd-mask = <0>;
brcm,irq-can-wake;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <57>, <55>, <59>;
interrupt-names = "upg_main_aon", "upg_bsc_aon",
"upg_spi";
};
sun_top_ctrl: syscon@404000 {
@@ -138,6 +156,46 @@
status = "disabled";
};
bsca: i2c@406200 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406200 0x58>;
interrupts = <24>;
interrupt-names = "upg_bsca";
status = "disabled";
};
bscb: i2c@406280 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406280 0x58>;
interrupts = <25>;
interrupt-names = "upg_bscb";
status = "disabled";
};
bscc: i2c@406300 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406300 0x58>;
interrupts = <26>;
interrupt-names = "upg_bscc";
status = "disabled";
};
bscd: i2c@408980 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_aon_irq0_intc>;
reg = <0x408980 0x58>;
interrupts = <27>;
interrupt-names = "upg_bscd";
status = "disabled";
};
enet0: ethernet@430000 {
phy-mode = "internal";
phy-handle = <&phy1>;

62
arch/mips/boot/dts/brcm/bcm7360.dtsi
View File

@@ -81,14 +81,32 @@
compatible = "brcm,bcm7120-l2-intc";
reg = <0x406600 0x8>;
brcm,int-map-mask = <0x44>;
brcm,int-map-mask = <0x44>, <0x7000000>;
brcm,int-fwd-mask = <0x70000>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <56>;
interrupts = <56>, <54>;
interrupt-names = "upg_main", "upg_bsc";
};
upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
compatible = "brcm,bcm7120-l2-intc";
reg = <0x408b80 0x8>;
brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
brcm,int-fwd-mask = <0>;
brcm,irq-can-wake;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <57>, <55>, <59>;
interrupt-names = "upg_main_aon", "upg_bsc_aon",
"upg_spi";
};
sun_top_ctrl: syscon@404000 {
@@ -138,6 +156,46 @@
status = "disabled";
};
bsca: i2c@406200 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406200 0x58>;
interrupts = <24>;
interrupt-names = "upg_bsca";
status = "disabled";
};
bscb: i2c@406280 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406280 0x58>;
interrupts = <25>;
interrupt-names = "upg_bscb";
status = "disabled";
};
bscc: i2c@406300 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406300 0x58>;
interrupts = <26>;
interrupt-names = "upg_bscc";
status = "disabled";
};
bscd: i2c@408980 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_aon_irq0_intc>;
reg = <0x408980 0x58>;
interrupts = <27>;
interrupt-names = "upg_bscd";
status = "disabled";
};
enet0: ethernet@430000 {
phy-mode = "internal";
phy-handle = <&phy1>;

94
arch/mips/boot/dts/brcm/bcm7362.dtsi
View File

@@ -87,14 +87,32 @@
compatible = "brcm,bcm7120-l2-intc";
reg = <0x406600 0x8>;
brcm,int-map-mask = <0x44>;
brcm,int-map-mask = <0x44>, <0x7000000>;
brcm,int-fwd-mask = <0x70000>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <56>;
interrupts = <56>, <54>;
interrupt-names = "upg_main", "upg_bsc";
};
upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
compatible = "brcm,bcm7120-l2-intc";
reg = <0x408b80 0x8>;
brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
brcm,int-fwd-mask = <0>;
brcm,irq-can-wake;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <57>, <55>, <59>;
interrupt-names = "upg_main_aon", "upg_bsc_aon",
"upg_spi";
};
sun_top_ctrl: syscon@404000 {
@@ -144,6 +162,36 @@
status = "disabled";
};
bsca: i2c@406200 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406200 0x58>;
interrupts = <24>;
interrupt-names = "upg_bsca";
status = "disabled";
};
bscb: i2c@406280 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406280 0x58>;
interrupts = <25>;
interrupt-names = "upg_bscb";
status = "disabled";
};
bscd: i2c@408980 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_aon_irq0_intc>;
reg = <0x408980 0x58>;
interrupts = <27>;
interrupt-names = "upg_bscd";
status = "disabled";
};
enet0: ethernet@430000 {
phy-mode = "internal";
phy-handle = <&phy1>;
@@ -189,5 +237,47 @@
interrupts = <66>;
status = "disabled";
};
sata: sata@181000 {
compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
reg-names = "ahci", "top-ctrl";
reg = <0x181000 0xa9c>, <0x180020 0x1c>;
interrupt-parent = <&periph_intc>;
interrupts = <86>;
#address-cells = <1>;
#size-cells = <0>;
brcm,broken-ncq;
brcm,broken-phy;
status = "disabled";
sata0: sata-port@0 {
reg = <0>;
phys = <&sata_phy0>;
};
sata1: sata-port@1 {
reg = <1>;
phys = <&sata_phy1>;
};
};
sata_phy: sata-phy@1800000 {
compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
reg = <0x180100 0x0eff>;
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata_phy0: sata-phy@0 {
reg = <0>;
#phy-cells = <0>;
};
sata_phy1: sata-phy@1 {
reg = <1>;
#phy-cells = <0>;
};
};
};
};

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