mirror of
https://github.com/armbian/linux-cix.git
synced 2026-01-06 12:30:45 -08:00
Merge tag 'arm-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM driver updates from Arnd Bergmann:
"There are a few separately maintained driver subsystems that we merge
through the SoC tree, notable changes are:
- Memory controller updates, mainly for Tegra and Mediatek SoCs, and
clarifications for the memory controller DT bindings
- SCMI firmware interface updates, in particular a new transport
based on OPTEE and support for atomic operations.
- Cleanups to the TEE subsystem, refactoring its memory management
For SoC specific drivers without a separate subsystem, changes include
- Smaller updates and fixes for TI, AT91/SAMA5, Qualcomm and NXP
Layerscape SoCs.
- Driver support for Microchip SAMA5D29, Tesla FSD, Renesas RZ/G2L,
and Qualcomm SM8450.
- Better power management on Mediatek MT81xx, NXP i.MX8MQ and older
NVIDIA Tegra chips"
* tag 'arm-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (154 commits)
ARM: spear: fix typos in comments
soc/microchip: fix invalid free in mpfs_sys_controller_delete
soc: s4: Add support for power domains controller
dt-bindings: power: add Amlogic s4 power domains bindings
ARM: at91: add support in soc driver for new SAMA5D29
soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data
dt-bindings: memory: renesas,rpc-if: Document RZ/V2L SoC
memory: emif: check the pointer temp in get_device_details()
memory: emif: Add check for setup_interrupts
dt-bindings: arm: mediatek: mmsys: add support for MT8186
dt-bindings: mediatek: add compatible for MT8186 pwrap
soc: mediatek: pwrap: add pwrap driver for MT8186 SoC
soc: mediatek: mmsys: add mmsys reset control for MT8186
soc: mediatek: mtk-infracfg: Disable ACP on MT8192
soc: ti: k3-socinfo: Add AM62x JTAG ID
soc: mediatek: add MTK mutex support for MT8186
soc: mediatek: mmsys: add mt8186 mmsys routing table
soc: mediatek: pm-domains: Add support for mt8186
dt-bindings: power: Add MT8186 power domains
soc: mediatek: pm-domains: Add support for mt8195
...
This commit is contained in:
Linus Torvalds
@@ -29,6 +29,7 @@ properties:
|
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- mediatek,mt8167-mmsys
|
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- mediatek,mt8173-mmsys
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- mediatek,mt8183-mmsys
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- mediatek,mt8186-mmsys
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- mediatek,mt8192-mmsys
|
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- mediatek,mt8365-mmsys
|
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- const: syscon
|
||||
|
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@@ -27,6 +27,8 @@ properties:
|
||||
- qcom,sm6350-llcc
|
||||
- qcom,sm8150-llcc
|
||||
- qcom,sm8250-llcc
|
||||
- qcom,sm8350-llcc
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- qcom,sm8450-llcc
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|
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reg:
|
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items:
|
||||
|
||||
198
Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml
Normal file
198
Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml
Normal file
@@ -0,0 +1,198 @@
|
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
|
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---
|
||||
$id: http://devicetree.org/schemas/clock/tesla,fsd-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
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title: Tesla FSD (Full Self-Driving) SoC clock controller
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|
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maintainers:
|
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- Alim Akhtar <alim.akhtar@samsung.com>
|
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- linux-fsd@tesla.com
|
||||
|
||||
description: |
|
||||
FSD clock controller consist of several clock management unit
|
||||
(CMU), which generates clocks for various inteernal SoC blocks.
|
||||
The root clock comes from external OSC clock (24 MHz).
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
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'dt-bindings/clock/fsd-clk.h' header.
|
||||
|
||||
properties:
|
||||
compatible:
|
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enum:
|
||||
- tesla,fsd-clock-cmu
|
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- tesla,fsd-clock-imem
|
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- tesla,fsd-clock-peric
|
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- tesla,fsd-clock-fsys0
|
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- tesla,fsd-clock-fsys1
|
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- tesla,fsd-clock-mfc
|
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- tesla,fsd-clock-cam_csi
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
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maxItems: 6
|
||||
|
||||
clock-names:
|
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minItems: 1
|
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maxItems: 6
|
||||
|
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"#clock-cells":
|
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const: 1
|
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|
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reg:
|
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maxItems: 1
|
||||
|
||||
allOf:
|
||||
- if:
|
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properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: tesla,fsd-clock-cmu
|
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then:
|
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properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (24 MHz)
|
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clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
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|
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- if:
|
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properties:
|
||||
compatible:
|
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contains:
|
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const: tesla,fsd-clock-imem
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
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items:
|
||||
- description: External reference clock (24 MHz)
|
||||
- description: IMEM TCU clock (from CMU_CMU)
|
||||
- description: IMEM bus clock (from CMU_CMU)
|
||||
- description: IMEM DMA clock (from CMU_CMU)
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_cmu_imem_tcuclk
|
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- const: dout_cmu_imem_aclk
|
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- const: dout_cmu_imem_dmaclk
|
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|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: tesla,fsd-clock-peric
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (24 MHz)
|
||||
- description: Shared0 PLL div4 clock (from CMU_CMU)
|
||||
- description: PERIC shared1 div36 clock (from CMU_CMU)
|
||||
- description: PERIC shared0 div3 TBU clock (from CMU_CMU)
|
||||
- description: PERIC shared0 div20 clock (from CMU_CMU)
|
||||
- description: PERIC shared1 div4 DMAclock (from CMU_CMU)
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_cmu_pll_shared0_div4
|
||||
- const: dout_cmu_peric_shared1div36
|
||||
- const: dout_cmu_peric_shared0div3_tbuclk
|
||||
- const: dout_cmu_peric_shared0div20
|
||||
- const: dout_cmu_peric_shared1div4_dmaclk
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: tesla,fsd-clock-fsys0
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (24 MHz)
|
||||
- description: Shared0 PLL div6 clock (from CMU_CMU)
|
||||
- description: FSYS0 shared1 div4 clock (from CMU_CMU)
|
||||
- description: FSYS0 shared0 div4 clock (from CMU_CMU)
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_cmu_pll_shared0_div6
|
||||
- const: dout_cmu_fsys0_shared1div4
|
||||
- const: dout_cmu_fsys0_shared0div4
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: tesla,fsd-clock-fsys1
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (24 MHz)
|
||||
- description: FSYS1 shared0 div8 clock (from CMU_CMU)
|
||||
- description: FSYS1 shared0 div4 clock (from CMU_CMU)
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_cmu_fsys1_shared0div8
|
||||
- const: dout_cmu_fsys1_shared0div4
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: tesla,fsd-clock-mfc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (24 MHz)
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: tesla,fsd-clock-cam_csi
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (24 MHz)
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock controller node for CMU_FSYS1
|
||||
- |
|
||||
#include <dt-bindings/clock/fsd-clk.h>
|
||||
|
||||
clock_fsys1: clock-controller@16810000 {
|
||||
compatible = "tesla,fsd-clock-fsys1";
|
||||
reg = <0x16810000 0x3000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&fin_pll>,
|
||||
<&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>,
|
||||
<&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>;
|
||||
clock-names = "fin_pll",
|
||||
"dout_cmu_fsys1_shared0div8",
|
||||
"dout_cmu_fsys1_shared0div4";
|
||||
};
|
||||
|
||||
...
|
||||
@@ -38,6 +38,9 @@ properties:
|
||||
The virtio transport only supports a single device.
|
||||
items:
|
||||
- const: arm,scmi-virtio
|
||||
- description: SCMI compliant firmware with OP-TEE transport
|
||||
items:
|
||||
- const: linaro,scmi-optee
|
||||
|
||||
interrupts:
|
||||
description:
|
||||
@@ -78,11 +81,24 @@ properties:
|
||||
'#size-cells':
|
||||
const: 0
|
||||
|
||||
atomic-threshold-us:
|
||||
description:
|
||||
An optional time value, expressed in microseconds, representing, on this
|
||||
platform, the threshold above which any SCMI command, advertised to have
|
||||
an higher-than-threshold execution latency, should not be considered for
|
||||
atomic mode of operation, even if requested.
|
||||
default: 0
|
||||
|
||||
arm,smc-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
SMC id required when using smc or hvc transports
|
||||
|
||||
linaro,optee-channel-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Channel specifier required when using OP-TEE transport.
|
||||
|
||||
protocol@11:
|
||||
type: object
|
||||
properties:
|
||||
@@ -195,6 +211,12 @@ patternProperties:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
linaro,optee-channel-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Channel specifier required when using OP-TEE transport and
|
||||
protocol has a dedicated communication channel.
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
@@ -226,6 +248,16 @@ else:
|
||||
- arm,smc-id
|
||||
- shmem
|
||||
|
||||
else:
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: linaro,scmi-optee
|
||||
then:
|
||||
required:
|
||||
- linaro,optee-channel-id
|
||||
|
||||
examples:
|
||||
- |
|
||||
firmware {
|
||||
@@ -240,6 +272,8 @@ examples:
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
atomic-threshold-us = <10000>;
|
||||
|
||||
scmi_devpd: protocol@11 {
|
||||
reg = <0x11>;
|
||||
#power-domain-cells = <1>;
|
||||
@@ -340,7 +374,48 @@ examples:
|
||||
reg = <0x11>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
firmware {
|
||||
scmi {
|
||||
compatible = "linaro,scmi-optee";
|
||||
linaro,optee-channel-id = <0>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
scmi_dvfs1: protocol@13 {
|
||||
reg = <0x13>;
|
||||
linaro,optee-channel-id = <1>;
|
||||
shmem = <&cpu_optee_lpri0>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
scmi_clk0: protocol@14 {
|
||||
reg = <0x14>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
sram@51000000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x0 0x51000000 0x0 0x10000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0x51000000 0x10000>;
|
||||
|
||||
cpu_optee_lpri0: optee-sram-section@0 {
|
||||
compatible = "arm,scmi-shmem";
|
||||
reg = <0x0 0x80>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -0,0 +1,135 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: jedec,lpddr2-timings
|
||||
|
||||
max-freq:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Maximum DDR clock frequency for the speed-bin, in Hz.
|
||||
|
||||
min-freq:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Minimum DDR clock frequency for the speed-bin, in Hz.
|
||||
|
||||
tCKESR:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
CKE minimum pulse width during SELF REFRESH (low pulse width during
|
||||
SELF REFRESH) in pico seconds.
|
||||
|
||||
tDQSCK-max:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
DQS output data access time from CK_t/CK_c in pico seconds.
|
||||
|
||||
tDQSCK-max-derated:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
DQS output data access time from CK_t/CK_c, temperature de-rated, in pico
|
||||
seconds.
|
||||
|
||||
tFAW:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Four-bank activate window in pico seconds.
|
||||
|
||||
tRAS-max-ns:
|
||||
description: |
|
||||
Row active time in nano seconds.
|
||||
|
||||
tRAS-min:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Row active time in pico seconds.
|
||||
|
||||
tRCD:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
RAS-to-CAS delay in pico seconds.
|
||||
|
||||
tRPab:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Row precharge time (all banks) in pico seconds.
|
||||
|
||||
tRRD:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Active bank A to active bank B in pico seconds.
|
||||
|
||||
tRTP:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Internal READ to PRECHARGE command delay in pico seconds.
|
||||
|
||||
tWR:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
WRITE recovery time in pico seconds.
|
||||
|
||||
tWTR:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Internal WRITE-to-READ command delay in pico seconds.
|
||||
|
||||
tXP:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Exit power-down to next valid command delay in pico seconds.
|
||||
|
||||
tZQCL:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Long calibration time in pico seconds.
|
||||
|
||||
tZQCS:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Short calibration time in pico seconds.
|
||||
|
||||
tZQinit:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Initialization calibration time in pico seconds.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- min-freq
|
||||
- max-freq
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
timings {
|
||||
compatible = "jedec,lpddr2-timings";
|
||||
min-freq = <10000000>;
|
||||
max-freq = <400000000>;
|
||||
tCKESR = <15000>;
|
||||
tDQSCK-max = <5500>;
|
||||
tFAW = <50000>;
|
||||
tRAS-max-ns = <70000>;
|
||||
tRAS-min = <42000>;
|
||||
tRPab = <21000>;
|
||||
tRCD = <18000>;
|
||||
tRRD = <10000>;
|
||||
tRTP = <7500>;
|
||||
tWR = <15000>;
|
||||
tWTR = <7500>;
|
||||
tXP = <7500>;
|
||||
tZQCL = <360000>;
|
||||
tZQCS = <90000>;
|
||||
tZQinit = <1000000>;
|
||||
};
|
||||
@@ -30,12 +30,26 @@ properties:
|
||||
maximum: 255
|
||||
description: |
|
||||
Revision 1 value of SDRAM chip. Obtained from device datasheet.
|
||||
Property is deprecated, use revision-id instead.
|
||||
deprecated: true
|
||||
|
||||
revision-id2:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 255
|
||||
description: |
|
||||
Revision 2 value of SDRAM chip. Obtained from device datasheet.
|
||||
Property is deprecated, use revision-id instead.
|
||||
deprecated: true
|
||||
|
||||
revision-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description: |
|
||||
Revision IDs read from Mode Register 6 and 7. One byte per uint32 cell (i.e. <MR6 MR7>).
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
|
||||
density:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
@@ -142,14 +156,12 @@ properties:
|
||||
|
||||
patternProperties:
|
||||
"^lpddr2-timings":
|
||||
type: object
|
||||
$ref: jedec,lpddr2-timings.yaml
|
||||
description: |
|
||||
The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
|
||||
"lpddr2-timings" provides AC timing parameters of the device for
|
||||
a given speed-bin. The user may provide the timings for as many
|
||||
speed-bins as is required. Please see Documentation/devicetree/
|
||||
bindings/memory-controllers/ddr/lpddr2-timings.txt for more information
|
||||
on "lpddr2-timings".
|
||||
speed-bins as is required.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
@@ -164,8 +176,7 @@ examples:
|
||||
compatible = "elpida,ECB240ABACN", "jedec,lpddr2-s4";
|
||||
density = <2048>;
|
||||
io-width = <32>;
|
||||
revision-id1 = <1>;
|
||||
revision-id2 = <0>;
|
||||
revision-id = <1 0>;
|
||||
|
||||
tRPab-min-tck = <3>;
|
||||
tRCD-min-tck = <3>;
|
||||
|
||||
@@ -0,0 +1,157 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: jedec,lpddr3-timings
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: |
|
||||
Maximum DDR clock frequency for the speed-bin, in Hz.
|
||||
Property is deprecated, use max-freq.
|
||||
deprecated: true
|
||||
|
||||
max-freq:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Maximum DDR clock frequency for the speed-bin, in Hz.
|
||||
|
||||
min-freq:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Minimum DDR clock frequency for the speed-bin, in Hz.
|
||||
|
||||
tCKE:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
CKE minimum pulse width (HIGH and LOW pulse width) in pico seconds.
|
||||
|
||||
tCKESR:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
CKE minimum pulse width during SELF REFRESH (low pulse width during
|
||||
SELF REFRESH) in pico seconds.
|
||||
|
||||
tFAW:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Four-bank activate window in pico seconds.
|
||||
|
||||
tMRD:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Mode register set command delay in pico seconds.
|
||||
|
||||
tR2R-C2C:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Additional READ-to-READ delay in chip-to-chip cases in pico seconds.
|
||||
|
||||
tRAS:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Row active time in pico seconds.
|
||||
|
||||
tRC:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
ACTIVATE-to-ACTIVATE command period in pico seconds.
|
||||
|
||||
tRCD:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
RAS-to-CAS delay in pico seconds.
|
||||
|
||||
tRFC:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Refresh Cycle time in pico seconds.
|
||||
|
||||
tRPab:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Row precharge time (all banks) in pico seconds.
|
||||
|
||||
tRPpb:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Row precharge time (single banks) in pico seconds.
|
||||
|
||||
tRRD:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Active bank A to active bank B in pico seconds.
|
||||
|
||||
tRTP:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Internal READ to PRECHARGE command delay in pico seconds.
|
||||
|
||||
tW2W-C2C:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Additional WRITE-to-WRITE delay in chip-to-chip cases in pico seconds.
|
||||
|
||||
tWR:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
WRITE recovery time in pico seconds.
|
||||
|
||||
tWTR:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Internal WRITE-to-READ command delay in pico seconds.
|
||||
|
||||
tXP:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Exit power-down to next valid command delay in pico seconds.
|
||||
|
||||
tXSR:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
SELF REFRESH exit to next valid command delay in pico seconds.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- min-freq
|
||||
- max-freq
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
lpddr3 {
|
||||
timings {
|
||||
compatible = "jedec,lpddr3-timings";
|
||||
max-freq = <800000000>;
|
||||
min-freq = <100000000>;
|
||||
tCKE = <3750>;
|
||||
tCKESR = <3750>;
|
||||
tFAW = <25000>;
|
||||
tMRD = <7000>;
|
||||
tR2R-C2C = <0>;
|
||||
tRAS = <23000>;
|
||||
tRC = <33750>;
|
||||
tRCD = <10000>;
|
||||
tRFC = <65000>;
|
||||
tRPab = <12000>;
|
||||
tRPpb = <12000>;
|
||||
tRRD = <6000>;
|
||||
tRTP = <3750>;
|
||||
tW2W-C2C = <0>;
|
||||
tWR = <7500>;
|
||||
tWTR = <3750>;
|
||||
tXP = <3750>;
|
||||
tXSR = <70000>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,263 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- samsung,K3QF2F20DB
|
||||
- const: jedec,lpddr3
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
deprecated: true
|
||||
|
||||
density:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Density in megabits of SDRAM chip.
|
||||
enum:
|
||||
- 4096
|
||||
- 8192
|
||||
- 16384
|
||||
- 32768
|
||||
|
||||
io-width:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
IO bus width in bits of SDRAM chip.
|
||||
enum:
|
||||
- 32
|
||||
- 16
|
||||
|
||||
manufacturer-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Manufacturer ID value read from Mode Register 5. The property is
|
||||
deprecated, manufacturer should be derived from the compatible.
|
||||
deprecated: true
|
||||
|
||||
revision-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
items:
|
||||
maximum: 255
|
||||
description: |
|
||||
Revision value of SDRAM chip read from Mode Registers 6 and 7.
|
||||
|
||||
'#size-cells':
|
||||
const: 0
|
||||
deprecated: true
|
||||
|
||||
tCKE-min-tck:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 15
|
||||
description: |
|
||||
CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
|
||||
of clock cycles.
|
||||
|
||||
tCKESR-min-tck:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 15
|
||||
description: |
|
||||
CKE minimum pulse width during SELF REFRESH (low pulse width during
|
||||
SELF REFRESH) in terms of number of clock cycles.
|
||||
|
||||
tDQSCK-min-tck:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 15
|
||||
description: |
|
||||
DQS output data access time from CK_t/CK_c in terms of number of clock
|
||||
cycles.
|
||||
|
||||
tFAW-min-tck:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 63
|
||||
description: |
|
||||
Four-bank activate window in terms of number of clock cycles.
|
||||
|
||||
tMRD-min-tck:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 15
|
||||
description: |
|
||||
Mode register set command delay in terms of number of clock cycles.
|
||||
|
||||
tR2R-C2C-min-tck:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
description: |
|
||||
Additional READ-to-READ delay in chip-to-chip cases in terms of number
|
||||
of clock cycles.
|
||||
|
||||
tRAS-min-tck:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 63
|
||||
description: |
|
||||
Row active time in terms of number of clock cycles.
|
||||
|
||||
tRC-min-tck:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 63
|
||||
description: |
|
||||
ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles.
|
||||
|
||||
tRCD-min-tck:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 15
|
||||
description: |
|
||||
RAS-to-CAS delay in terms of number of clock cycles.
|
||||
|
||||
tRFC-min-tck:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 255
|
||||
description: |
|
||||
Refresh Cycle time in terms of number of clock cycles.
|
||||
|
||||
tRL-min-tck:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 15
|
||||
description: |
|
||||
READ data latency in terms of number of clock cycles.
|
||||
|
||||
tRPab-min-tck:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 15
|
||||
description: |
|
||||
Row precharge time (all banks) in terms of number of clock cycles.
|
||||
|
||||
tRPpb-min-tck:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 15
|
||||
description: |
|
||||
Row precharge time (single banks) in terms of number of clock cycles.
|
||||
|
||||
tRRD-min-tck:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 15
|
||||
description: |
|
||||
Active bank A to active bank B in terms of number of clock cycles.
|
||||
|
||||
tRTP-min-tck:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 15
|
||||
description: |
|
||||
Internal READ to PRECHARGE command delay in terms of number of clock
|
||||
cycles.
|
||||
|
||||
tW2W-C2C-min-tck:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
description: |
|
||||
Additional WRITE-to-WRITE delay in chip-to-chip cases in terms of number
|
||||
of clock cycles.
|
||||
|
||||
tWL-min-tck:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 15
|
||||
description: |
|
||||
WRITE data latency in terms of number of clock cycles.
|
||||
|
||||
tWR-min-tck:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 15
|
||||
description: |
|
||||
WRITE recovery time in terms of number of clock cycles.
|
||||
|
||||
tWTR-min-tck:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 15
|
||||
description: |
|
||||
Internal WRITE-to-READ command delay in terms of number of clock cycles.
|
||||
|
||||
tXP-min-tck:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 255
|
||||
description: |
|
||||
Exit power-down to next valid command delay in terms of number of clock
|
||||
cycles.
|
||||
|
||||
tXSR-min-tck:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 1023
|
||||
description: |
|
||||
SELF REFRESH exit to next valid command delay in terms of number of clock
|
||||
cycles.
|
||||
|
||||
patternProperties:
|
||||
"^timings((-[0-9])+|(@[0-9a-f]+))?$":
|
||||
$ref: jedec,lpddr3-timings.yaml
|
||||
description: |
|
||||
The lpddr3 node may have one or more child nodes with timings.
|
||||
Each timing node provides AC timing parameters of the device for a given
|
||||
speed-bin. The user may provide the timings for as many speed-bins as is
|
||||
required.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- density
|
||||
- io-width
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
lpddr3 {
|
||||
compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
|
||||
density = <16384>;
|
||||
io-width = <32>;
|
||||
|
||||
tCKE-min-tck = <2>;
|
||||
tCKESR-min-tck = <2>;
|
||||
tDQSCK-min-tck = <5>;
|
||||
tFAW-min-tck = <5>;
|
||||
tMRD-min-tck = <5>;
|
||||
tR2R-C2C-min-tck = <0>;
|
||||
tRAS-min-tck = <5>;
|
||||
tRC-min-tck = <6>;
|
||||
tRCD-min-tck = <3>;
|
||||
tRFC-min-tck = <17>;
|
||||
tRL-min-tck = <14>;
|
||||
tRPab-min-tck = <2>;
|
||||
tRPpb-min-tck = <2>;
|
||||
tRRD-min-tck = <2>;
|
||||
tRTP-min-tck = <2>;
|
||||
tW2W-C2C-min-tck = <0>;
|
||||
tWL-min-tck = <8>;
|
||||
tWR-min-tck = <7>;
|
||||
tWTR-min-tck = <2>;
|
||||
tXP-min-tck = <2>;
|
||||
tXSR-min-tck = <12>;
|
||||
|
||||
timings {
|
||||
compatible = "jedec,lpddr3-timings";
|
||||
max-freq = <800000000>;
|
||||
min-freq = <100000000>;
|
||||
tCKE = <3750>;
|
||||
tCKESR = <3750>;
|
||||
tFAW = <25000>;
|
||||
tMRD = <7000>;
|
||||
tR2R-C2C = <0>;
|
||||
tRAS = <23000>;
|
||||
tRC = <33750>;
|
||||
tRCD = <10000>;
|
||||
tRFC = <65000>;
|
||||
tRPab = <12000>;
|
||||
tRPpb = <12000>;
|
||||
tRRD = <6000>;
|
||||
tRTP = <3750>;
|
||||
tW2W-C2C = <0>;
|
||||
tWR = <7500>;
|
||||
tWTR = <3750>;
|
||||
tXP = <3750>;
|
||||
tXSR = <70000>;
|
||||
};
|
||||
};
|
||||
@@ -1,52 +0,0 @@
|
||||
* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "jedec,lpddr2-timings"
|
||||
- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
|
||||
- max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
|
||||
|
||||
Optional properties:
|
||||
|
||||
The following properties represent AC timing parameters from the memory
|
||||
data-sheet of the device for a given speed-bin. All these properties are
|
||||
of type <u32> and the default unit is ps (pico seconds). Parameters with
|
||||
a different unit have a suffix indicating the unit such as 'tRAS-max-ns'
|
||||
- tRCD
|
||||
- tWR
|
||||
- tRAS-min
|
||||
- tRRD
|
||||
- tWTR
|
||||
- tXP
|
||||
- tRTP
|
||||
- tDQSCK-max
|
||||
- tFAW
|
||||
- tZQCS
|
||||
- tZQinit
|
||||
- tRPab
|
||||
- tZQCL
|
||||
- tCKESR
|
||||
- tRAS-max-ns
|
||||
- tDQSCK-max-derated
|
||||
|
||||
Example:
|
||||
|
||||
timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
|
||||
compatible = "jedec,lpddr2-timings";
|
||||
min-freq = <10000000>;
|
||||
max-freq = <400000000>;
|
||||
tRPab = <21000>;
|
||||
tRCD = <18000>;
|
||||
tWR = <15000>;
|
||||
tRAS-min = <42000>;
|
||||
tRRD = <10000>;
|
||||
tWTR = <7500>;
|
||||
tXP = <7500>;
|
||||
tRTP = <7500>;
|
||||
tCKESR = <15000>;
|
||||
tDQSCK-max = <5500>;
|
||||
tFAW = <50000>;
|
||||
tZQCS = <90000>;
|
||||
tZQCL = <360000>;
|
||||
tZQinit = <1000000>;
|
||||
tRAS-max-ns = <70000>;
|
||||
};
|
||||
@@ -1,58 +0,0 @@
|
||||
* AC timing parameters of LPDDR3 memories for a given speed-bin.
|
||||
|
||||
The structures are based on LPDDR2 and extended where needed.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "jedec,lpddr3-timings"
|
||||
- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
|
||||
- reg : maximum DDR clock frequency for the speed-bin. Type is <u32>
|
||||
|
||||
Optional properties:
|
||||
|
||||
The following properties represent AC timing parameters from the memory
|
||||
data-sheet of the device for a given speed-bin. All these properties are
|
||||
of type <u32> and the default unit is ps (pico seconds).
|
||||
- tRFC
|
||||
- tRRD
|
||||
- tRPab
|
||||
- tRPpb
|
||||
- tRCD
|
||||
- tRC
|
||||
- tRAS
|
||||
- tWTR
|
||||
- tWR
|
||||
- tRTP
|
||||
- tW2W-C2C
|
||||
- tR2R-C2C
|
||||
- tFAW
|
||||
- tXSR
|
||||
- tXP
|
||||
- tCKE
|
||||
- tCKESR
|
||||
- tMRD
|
||||
|
||||
Example:
|
||||
|
||||
timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
|
||||
compatible = "jedec,lpddr3-timings";
|
||||
reg = <800000000>; /* workaround: it shows max-freq */
|
||||
min-freq = <100000000>;
|
||||
tRFC = <65000>;
|
||||
tRRD = <6000>;
|
||||
tRPab = <12000>;
|
||||
tRPpb = <12000>;
|
||||
tRCD = <10000>;
|
||||
tRC = <33750>;
|
||||
tRAS = <23000>;
|
||||
tWTR = <3750>;
|
||||
tWR = <7500>;
|
||||
tRTP = <3750>;
|
||||
tW2W-C2C = <0>;
|
||||
tR2R-C2C = <0>;
|
||||
tFAW = <25000>;
|
||||
tXSR = <70000>;
|
||||
tXP = <3750>;
|
||||
tCKE = <3750>;
|
||||
tCKESR = <3750>;
|
||||
tMRD = <7000>;
|
||||
};
|
||||
@@ -1,107 +0,0 @@
|
||||
* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "<vendor>,<type>", and generic value "jedec,lpddr3".
|
||||
Example "<vendor>,<type>" values:
|
||||
"samsung,K3QF2F20DB"
|
||||
|
||||
- density : <u32> representing density in Mb (Mega bits)
|
||||
- io-width : <u32> representing bus width. Possible values are 8, 16, 32, 64
|
||||
- #address-cells: Must be set to 1
|
||||
- #size-cells: Must be set to 0
|
||||
|
||||
Optional properties:
|
||||
|
||||
- manufacturer-id : <u32> Manufacturer ID value read from Mode Register 5
|
||||
- revision-id : <u32 u32> Revision IDs read from Mode Registers 6 and 7
|
||||
|
||||
The following optional properties represent the minimum value of some AC
|
||||
timing parameters of the DDR device in terms of number of clock cycles.
|
||||
These values shall be obtained from the device data-sheet.
|
||||
- tRFC-min-tck
|
||||
- tRRD-min-tck
|
||||
- tRPab-min-tck
|
||||
- tRPpb-min-tck
|
||||
- tRCD-min-tck
|
||||
- tRC-min-tck
|
||||
- tRAS-min-tck
|
||||
- tWTR-min-tck
|
||||
- tWR-min-tck
|
||||
- tRTP-min-tck
|
||||
- tW2W-C2C-min-tck
|
||||
- tR2R-C2C-min-tck
|
||||
- tWL-min-tck
|
||||
- tDQSCK-min-tck
|
||||
- tRL-min-tck
|
||||
- tFAW-min-tck
|
||||
- tXSR-min-tck
|
||||
- tXP-min-tck
|
||||
- tCKE-min-tck
|
||||
- tCKESR-min-tck
|
||||
- tMRD-min-tck
|
||||
|
||||
Child nodes:
|
||||
- The lpddr3 node may have one or more child nodes of type "lpddr3-timings".
|
||||
"lpddr3-timings" provides AC timing parameters of the device for
|
||||
a given speed-bin. Please see
|
||||
Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt
|
||||
for more information on "lpddr3-timings"
|
||||
|
||||
Example:
|
||||
|
||||
samsung_K3QF2F20DB: lpddr3 {
|
||||
compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
|
||||
density = <16384>;
|
||||
io-width = <32>;
|
||||
manufacturer-id = <1>;
|
||||
revision-id = <123 234>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tRFC-min-tck = <17>;
|
||||
tRRD-min-tck = <2>;
|
||||
tRPab-min-tck = <2>;
|
||||
tRPpb-min-tck = <2>;
|
||||
tRCD-min-tck = <3>;
|
||||
tRC-min-tck = <6>;
|
||||
tRAS-min-tck = <5>;
|
||||
tWTR-min-tck = <2>;
|
||||
tWR-min-tck = <7>;
|
||||
tRTP-min-tck = <2>;
|
||||
tW2W-C2C-min-tck = <0>;
|
||||
tR2R-C2C-min-tck = <0>;
|
||||
tWL-min-tck = <8>;
|
||||
tDQSCK-min-tck = <5>;
|
||||
tRL-min-tck = <14>;
|
||||
tFAW-min-tck = <5>;
|
||||
tXSR-min-tck = <12>;
|
||||
tXP-min-tck = <2>;
|
||||
tCKE-min-tck = <2>;
|
||||
tCKESR-min-tck = <2>;
|
||||
tMRD-min-tck = <5>;
|
||||
|
||||
timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
|
||||
compatible = "jedec,lpddr3-timings";
|
||||
/* workaround: 'reg' shows max-freq */
|
||||
reg = <800000000>;
|
||||
min-freq = <100000000>;
|
||||
tRFC = <65000>;
|
||||
tRRD = <6000>;
|
||||
tRPab = <12000>;
|
||||
tRPpb = <12000>;
|
||||
tRCD = <10000>;
|
||||
tRC = <33750>;
|
||||
tRAS = <23000>;
|
||||
tWTR = <3750>;
|
||||
tWR = <7500>;
|
||||
tRTP = <3750>;
|
||||
tW2W-C2C = <0>;
|
||||
tR2R-C2C = <0>;
|
||||
tFAW = <25000>;
|
||||
tXSR = <70000>;
|
||||
tXP = <3750>;
|
||||
tCKE = <3750>;
|
||||
tCKESR = <3750>;
|
||||
tMRD = <7000>;
|
||||
};
|
||||
}
|
||||
@@ -0,0 +1,113 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ifc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: FSL/NXP Integrated Flash Controller
|
||||
|
||||
maintainers:
|
||||
- Li Yang <leoyang.li@nxp.com>
|
||||
|
||||
description: |
|
||||
NXP's integrated flash controller (IFC) is an advanced version of the
|
||||
enhanced local bus controller which includes similar programming and signal
|
||||
interfaces with an extended feature set. The IFC provides access to multiple
|
||||
external memory types, such as NAND flash (SLC and MLC), NOR flash, EPROM,
|
||||
SRAM and other memories where address and data are shared on a bus.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^memory-controller@[0-9a-f]+$"
|
||||
|
||||
compatible:
|
||||
const: fsl,ifc
|
||||
|
||||
"#address-cells":
|
||||
enum: [2, 3]
|
||||
description: |
|
||||
Should be either two or three. The first cell is the chipselect
|
||||
number, and the remaining cells are the offset into the chipselect.
|
||||
|
||||
"#size-cells":
|
||||
enum: [1, 2]
|
||||
description: |
|
||||
Either one or two, depending on how large each chipselect can be.
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
description: |
|
||||
IFC may have one or two interrupts. If two interrupt specifiers are
|
||||
present, the first is the "common" interrupt (CM_EVTER_STAT), and the
|
||||
second is the NAND interrupt (NAND_EVTER_STAT). If there is only one,
|
||||
that interrupt reports both types of event.
|
||||
|
||||
little-endian:
|
||||
type: boolean
|
||||
description: |
|
||||
If this property is absent, the big-endian mode will be in use as default
|
||||
for registers.
|
||||
|
||||
ranges:
|
||||
description: |
|
||||
Each range corresponds to a single chipselect, and covers the entire
|
||||
access window as configured.
|
||||
|
||||
patternProperties:
|
||||
"^.*@[a-f0-9]+(,[a-f0-9]+)+$":
|
||||
type: object
|
||||
description: |
|
||||
Child device nodes describe the devices connected to IFC such as NOR (e.g.
|
||||
cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices
|
||||
like FPGAs, CPLDs, etc.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
memory-controller@ffe1e000 {
|
||||
compatible = "fsl,ifc";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0 0xffe1e000 0 0x2000>;
|
||||
interrupts = <16 2 19 2>;
|
||||
little-endian;
|
||||
|
||||
/* NOR, NAND Flashes and CPLD on board */
|
||||
ranges = <0x0 0x0 0x0 0xee000000 0x02000000>,
|
||||
<0x1 0x0 0x0 0xffa00000 0x00010000>,
|
||||
<0x3 0x0 0x0 0xffb00000 0x00020000>;
|
||||
|
||||
flash@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x2000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
|
||||
partition@0 {
|
||||
/* 32MB for user data */
|
||||
reg = <0x0 0x02000000>;
|
||||
label = "NOR Data";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,82 +0,0 @@
|
||||
Integrated Flash Controller
|
||||
|
||||
Properties:
|
||||
- name : Should be ifc
|
||||
- compatible : should contain "fsl,ifc". The version of the integrated
|
||||
flash controller can be found in the IFC_REV register at
|
||||
offset zero.
|
||||
|
||||
- #address-cells : Should be either two or three. The first cell is the
|
||||
chipselect number, and the remaining cells are the
|
||||
offset into the chipselect.
|
||||
- #size-cells : Either one or two, depending on how large each chipselect
|
||||
can be.
|
||||
- reg : Offset and length of the register set for the device
|
||||
- interrupts: IFC may have one or two interrupts. If two interrupt
|
||||
specifiers are present, the first is the "common"
|
||||
interrupt (CM_EVTER_STAT), and the second is the NAND
|
||||
interrupt (NAND_EVTER_STAT). If there is only one,
|
||||
that interrupt reports both types of event.
|
||||
|
||||
- little-endian : If this property is absent, the big-endian mode will
|
||||
be in use as default for registers.
|
||||
|
||||
- ranges : Each range corresponds to a single chipselect, and covers
|
||||
the entire access window as configured.
|
||||
|
||||
Child device nodes describe the devices connected to IFC such as NOR (e.g.
|
||||
cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices
|
||||
like FPGAs, CPLDs, etc.
|
||||
|
||||
Example:
|
||||
|
||||
ifc@ffe1e000 {
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0 0xffe1e000 0 0x2000>;
|
||||
interrupts = <16 2 19 2>;
|
||||
little-endian;
|
||||
|
||||
/* NOR, NAND Flashes and CPLD on board */
|
||||
ranges = <0x0 0x0 0x0 0xee000000 0x02000000
|
||||
0x1 0x0 0x0 0xffa00000 0x00010000
|
||||
0x3 0x0 0x0 0xffb00000 0x00020000>;
|
||||
|
||||
flash@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x2000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
|
||||
partition@0 {
|
||||
/* 32MB for user data */
|
||||
reg = <0x0 0x02000000>;
|
||||
label = "NOR Data";
|
||||
};
|
||||
};
|
||||
|
||||
flash@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc-nand";
|
||||
reg = <0x1 0x0 0x10000>;
|
||||
|
||||
partition@0 {
|
||||
/* This location must not be altered */
|
||||
/* 1MB for u-boot Bootloader Image */
|
||||
reg = <0x0 0x00100000>;
|
||||
label = "NAND U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
cpld@3,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p1010rdb-cpld";
|
||||
reg = <0x3 0x0 0x000001f>;
|
||||
};
|
||||
};
|
||||
@@ -16,7 +16,7 @@ description: |
|
||||
MediaTek SMI have two generations of HW architecture, here is the list
|
||||
which generation the SoCs use:
|
||||
generation 1: mt2701 and mt7623.
|
||||
generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8192 and mt8195.
|
||||
generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8192 and mt8195.
|
||||
|
||||
There's slight differences between the two SMI, for generation 2, the
|
||||
register which control the iommu port is at each larb's register base. But
|
||||
@@ -35,6 +35,7 @@ properties:
|
||||
- mediatek,mt8167-smi-common
|
||||
- mediatek,mt8173-smi-common
|
||||
- mediatek,mt8183-smi-common
|
||||
- mediatek,mt8186-smi-common
|
||||
- mediatek,mt8192-smi-common
|
||||
- mediatek,mt8195-smi-common-vdo
|
||||
- mediatek,mt8195-smi-common-vpp
|
||||
@@ -88,10 +89,9 @@ allOf:
|
||||
- mediatek,mt2701-smi-common
|
||||
then:
|
||||
properties:
|
||||
clock:
|
||||
items:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
clock-names:
|
||||
items:
|
||||
- const: apb
|
||||
@@ -108,10 +108,9 @@ allOf:
|
||||
required:
|
||||
- mediatek,smi
|
||||
properties:
|
||||
clock:
|
||||
items:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
clock-names:
|
||||
items:
|
||||
- const: apb
|
||||
@@ -127,16 +126,16 @@ allOf:
|
||||
enum:
|
||||
- mediatek,mt6779-smi-common
|
||||
- mediatek,mt8183-smi-common
|
||||
- mediatek,mt8186-smi-common
|
||||
- mediatek,mt8192-smi-common
|
||||
- mediatek,mt8195-smi-common-vdo
|
||||
- mediatek,mt8195-smi-common-vpp
|
||||
|
||||
then:
|
||||
properties:
|
||||
clock:
|
||||
items:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
clocks:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
clock-names:
|
||||
items:
|
||||
- const: apb
|
||||
@@ -146,10 +145,9 @@ allOf:
|
||||
|
||||
else: # for gen2 HW that don't have gals
|
||||
properties:
|
||||
clock:
|
||||
items:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
items:
|
||||
- const: apb
|
||||
|
||||
@@ -23,6 +23,7 @@ properties:
|
||||
- mediatek,mt8167-smi-larb
|
||||
- mediatek,mt8173-smi-larb
|
||||
- mediatek,mt8183-smi-larb
|
||||
- mediatek,mt8186-smi-larb
|
||||
- mediatek,mt8192-smi-larb
|
||||
- mediatek,mt8195-smi-larb
|
||||
|
||||
@@ -75,15 +76,16 @@ allOf:
|
||||
compatible:
|
||||
enum:
|
||||
- mediatek,mt8183-smi-larb
|
||||
- mediatek,mt8186-smi-larb
|
||||
- mediatek,mt8195-smi-larb
|
||||
|
||||
then:
|
||||
properties:
|
||||
clock:
|
||||
items:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
clock-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: apb
|
||||
- const: smi
|
||||
@@ -91,10 +93,9 @@ allOf:
|
||||
|
||||
else:
|
||||
properties:
|
||||
clock:
|
||||
items:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
items:
|
||||
- const: apb
|
||||
@@ -108,7 +109,7 @@ allOf:
|
||||
- mediatek,mt2701-smi-larb
|
||||
- mediatek,mt2712-smi-larb
|
||||
- mediatek,mt6779-smi-larb
|
||||
- mediatek,mt8167-smi-larb
|
||||
- mediatek,mt8186-smi-larb
|
||||
- mediatek,mt8192-smi-larb
|
||||
- mediatek,mt8195-smi-larb
|
||||
|
||||
|
||||
@@ -40,7 +40,8 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,r9a07g044-rpc-if # RZ/G2{L,LC}
|
||||
- const: renesas,rzg2l-rpc-if # RZ/G2L family
|
||||
- renesas,r9a07g054-rpc-if # RZ/V2L
|
||||
- const: renesas,rzg2l-rpc-if
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
||||
@@ -51,8 +51,7 @@ properties:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle'
|
||||
description: |
|
||||
phandle of the connected DRAM memory device. For more information please
|
||||
refer to documentation file:
|
||||
Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt
|
||||
refer to jedec,lpddr3.yaml.
|
||||
|
||||
operating-points-v2: true
|
||||
|
||||
|
||||
@@ -12,13 +12,14 @@ maintainers:
|
||||
- Jianxin Pan <jianxin.pan@amlogic.com>
|
||||
|
||||
description: |+
|
||||
Secure Power Domains used in Meson A1/C1 SoCs, and should be the child node
|
||||
Secure Power Domains used in Meson A1/C1/S4 SoCs, and should be the child node
|
||||
of secure-monitor.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- amlogic,meson-a1-pwrc
|
||||
- amlogic,meson-s4-pwrc
|
||||
|
||||
"#power-domain-cells":
|
||||
const: 1
|
||||
|
||||
@@ -26,7 +26,9 @@ properties:
|
||||
- mediatek,mt8167-power-controller
|
||||
- mediatek,mt8173-power-controller
|
||||
- mediatek,mt8183-power-controller
|
||||
- mediatek,mt8186-power-controller
|
||||
- mediatek,mt8192-power-controller
|
||||
- mediatek,mt8195-power-controller
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
@@ -64,6 +66,7 @@ patternProperties:
|
||||
"include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
|
||||
"include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
|
||||
"include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
|
||||
"include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain.
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
|
||||
@@ -17,6 +17,7 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,mdm9607-rpmpd
|
||||
- qcom,msm8226-rpmpd
|
||||
- qcom,msm8916-rpmpd
|
||||
- qcom,msm8939-rpmpd
|
||||
- qcom,msm8953-rpmpd
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user