mirror of
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Merge tag 'drm-next-2022-03-24' of git://anongit.freedesktop.org/drm/drm
Pull drm updates from Dave Airlie: "Lots of work all over, Intel improving DG2 support, amdkfd CRIU support, msm new hw support, and faster fbdev support. dma-buf: - rename dma-buf-map to iosys-map core: - move buddy allocator to core - add pci/platform init macros - improve EDID parser deep color handling - EDID timing type 7 support - add GPD Win Max quirk - add yes/no helpers to string_helpers - flatten syncobj chains - add nomodeset support to lots of drivers - improve fb-helper clipping support - add default property value interface fbdev: - improve fbdev ops speed ttm: - add a backpointer from ttm bo->ttm resource dp: - move displayport headers - add a dp helper module bridge: - anx7625 atomic support, HDCP support panel: - split out panel-lvds and lvds bindings - find panels in OF subnodes privacy: - add chromeos privacy screen support fb: - hot unplug fw fb on forced removal simpledrm: - request region instead of marking ioresource busy - add panel oreintation property udmabuf: - fix oops with 0 pages amdgpu: - power management code cleanup - Enable freesync video mode by default - RAS code cleanup - Improve VRAM access for debug using SDMA - SR-IOV rework special register access and fixes - profiling power state request ioctl - expose IP discovery via sysfs - Cyan skillfish updates - GC 10.3.7, SDMA 5.2.7, DCN 3.1.6 updates - expose benchmark tests via debugfs - add module param to disable XGMI for testing - GPU reset debugfs register dumping support amdkfd: - CRIU support - SDMA queue fixes radeon: - UVD suspend fix - iMac backlight fix i915: - minimal parallel submission for execlists - DG2-G12 subplatform added - DG2 programming workarounds - DG2 accelerated migration support - flat CCS and CCS engine support for XeHP - initial small BAR support - drop fake LMEM support - ADL-N PCH support - bigjoiner updates - introduce VMA resources and async unbinding - register definitions cleanups - multi-FBC refactoring - DG1 OPROM over SPI support - ADL-N platform enabling - opregion mailbox #5 support - DP MST ESI improvements - drm device based logging - async flip optimisation for DG2 - CPU arch abstraction fixes - improve GuC ADS init to work on aarch64 - tweak TTM LRU priority hint - GuC 69.0.3 support - remove short term execbuf pins nouveau: - higher DP/eDP bitrates - backlight fixes msm: - dpu + dp support for sc8180x - dp support for sm8350 - dpu + dsi support for qcm2290 - 10nm dsi phy tuning support - bridge support for dp encoder - gpu support for additional 7c3 SKUs ingenic: - HDMI support for JZ4780 - aux channel EDID support ast: - AST2600 support - add wide screen support - create DP/DVI connectors omapdrm: - fix implicit dma_buf fencing vc4: - add CSC + full range support - better display firmware handoff panfrost: - add initial dual-core GPU support stm: - new revision support - fb handover support mediatek: - transfer display binding document to yaml format. - add mt8195 display device binding. - allow commands to be sent during video mode. - add wait_for_event for crtc disable by cmdq. tegra: - YUV format support rcar-du: - LVDS support for M3-W+ (R8A77961) exynos: - BGR pixel format for FIMD device" * tag 'drm-next-2022-03-24' of git://anongit.freedesktop.org/drm/drm: (1529 commits) drm/i915/display: Do not re-enable PSR after it was marked as not reliable drm/i915/display: Fix HPD short pulse handling for eDP drm/amdgpu: Use drm_mode_copy() drm/radeon: Use drm_mode_copy() drm/amdgpu: Use ternary operator in `vcn_v1_0_start()` drm/amdgpu: Remove pointless on stack mode copies drm/amd/pm: fix indenting in __smu_cmn_reg_print_error() drm/amdgpu/dc: fix typos in comments drm/amdgpu: fix typos in comments drm/amd/pm: fix typos in comments drm/amdgpu: Add stolen reserved memory for MI25 SRIOV. drm/amdgpu: Merge get_reserved_allocation to get_vbios_allocations. drm/amdkfd: evict svm bo worker handle error drm/amdgpu/vcn: fix vcn ring test failure in igt reload test drm/amdgpu: only allow secure submission on rings which support that drm/amdgpu: fixed the warnings reported by kernel test robot drm/amd/display: 3.2.177 drm/amd/display: [FW Promotion] Release 0.0.108.0 drm/amd/display: Add save/restore PANEL_PWRSEQ_REF_DIV2 drm/amd/display: Wait for hubp read line for Pollock ...
This commit is contained in:
Linus Torvalds
@@ -83,6 +83,9 @@ properties:
|
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type: boolean
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description: let the driver enable audio HDMI codec function or not.
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|
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aux-bus:
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$ref: /schemas/display/dp-aux-bus.yaml#
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|
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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|
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@@ -150,5 +153,19 @@ examples:
|
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};
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};
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};
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aux-bus {
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panel {
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compatible = "innolux,n125hce-gn1";
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power-supply = <&pp3300_disp_x>;
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backlight = <&backlight_lcd0>;
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|
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port {
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panel_in: endpoint {
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remote-endpoint = <&anx7625_out>;
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};
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};
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};
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};
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};
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};
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@@ -0,0 +1,82 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/bridge/ingenic,jz4780-hdmi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Bindings for Ingenic JZ4780 HDMI Transmitter
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maintainers:
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- H. Nikolaus Schaller <hns@goldelico.com>
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|
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description: |
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The HDMI Transmitter in the Ingenic JZ4780 is a Synopsys DesignWare HDMI 1.4
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TX controller IP with accompanying PHY IP.
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allOf:
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- $ref: synopsys,dw-hdmi.yaml#
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properties:
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compatible:
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const: ingenic,jz4780-dw-hdmi
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reg-io-width:
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const: 4
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clocks:
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maxItems: 2
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: Input from LCD controller output.
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: Link to the HDMI connector.
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required:
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- compatible
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- clocks
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- clock-names
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- ports
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- reg-io-width
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/ingenic,jz4780-cgu.h>
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hdmi: hdmi@10180000 {
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compatible = "ingenic,jz4780-dw-hdmi";
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reg = <0x10180000 0x8000>;
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reg-io-width = <4>;
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ddc-i2c-bus = <&i2c4>;
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interrupt-parent = <&intc>;
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interrupts = <3>;
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clocks = <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>;
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clock-names = "iahb", "isfr";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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hdmi_in: port@0 {
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reg = <0>;
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dw_hdmi_in: endpoint {
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remote-endpoint = <&jz4780_lcd_out>;
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};
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};
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hdmi_out: port@1 {
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reg = <1>;
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dw_hdmi_out: endpoint {
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remote-endpoint = <&hdmi_con>;
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};
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};
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};
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};
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|
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...
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@@ -39,6 +39,7 @@ properties:
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- const: lvds-encoder # Generic LVDS encoder compatible fallback
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- items:
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- enum:
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- ti,ds90cf364a # For the DS90CF364A FPD-Link LVDS Receiver
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- ti,ds90cf384a # For the DS90CF384A FPD-Link LVDS Receiver
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- const: lvds-decoder # Generic LVDS decoders compatible fallback
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- enum:
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@@ -67,7 +68,7 @@ properties:
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- vesa-24
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description: |
|
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The color signals mapping order. See details in
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Documentation/devicetree/bindings/display/panel/lvds.yaml
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Documentation/devicetree/bindings/display/lvds.yaml
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|
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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|
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@@ -28,6 +28,7 @@ properties:
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- renesas,r8a7793-lvds # for R-Car M2-N compatible LVDS encoders
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- renesas,r8a7795-lvds # for R-Car H3 compatible LVDS encoders
|
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- renesas,r8a7796-lvds # for R-Car M3-W compatible LVDS encoders
|
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- renesas,r8a77961-lvds # for R-Car M3-W+ compatible LVDS encoders
|
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- renesas,r8a77965-lvds # for R-Car M3-N compatible LVDS encoders
|
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- renesas,r8a77970-lvds # for R-Car V3M compatible LVDS encoders
|
||||
- renesas,r8a77980-lvds # for R-Car V3H compatible LVDS encoders
|
||||
|
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@@ -32,6 +32,9 @@ properties:
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maxItems: 1
|
||||
description: GPIO specifier for bridge_en pin (active high).
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|
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vcc-supply:
|
||||
description: A 1.8V power supply (see regulator/regulator.yaml).
|
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|
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ports:
|
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$ref: /schemas/graph.yaml#/properties/ports
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|
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@@ -91,7 +94,6 @@ properties:
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required:
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- compatible
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- reg
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- enable-gpios
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- ports
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|
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allOf:
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@@ -133,6 +135,7 @@ examples:
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reg = <0x2d>;
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enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
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vcc-supply = <®_sn65dsi83_1v8>;
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ports {
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#address-cells = <1>;
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|
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@@ -1,10 +1,10 @@
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||||
# SPDX-License-Identifier: GPL-2.0
|
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%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/lvds.yaml#
|
||||
$id: http://devicetree.org/schemas/display/lvds.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
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title: LVDS Display Panel
|
||||
title: LVDS Display Common Properties
|
||||
|
||||
maintainers:
|
||||
- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
|
||||
@@ -13,8 +13,8 @@ maintainers:
|
||||
description: |+
|
||||
LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple
|
||||
incompatible data link layers have been used over time to transmit image data
|
||||
to LVDS panels. This bindings supports display panels compatible with the
|
||||
following specifications.
|
||||
to LVDS devices. This bindings supports devices compatible with the following
|
||||
specifications.
|
||||
|
||||
[JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February
|
||||
1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA)
|
||||
@@ -26,18 +26,7 @@ description: |+
|
||||
Device compatible with those specifications have been marketed under the
|
||||
FPD-Link and FlatLink brands.
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
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const: panel-lvds
|
||||
description:
|
||||
Shall contain "panel-lvds" in addition to a mandatory panel-specific
|
||||
compatible string defined in individual panel bindings. The "panel-lvds"
|
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value shall never be used on its own.
|
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|
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data-mapping:
|
||||
enum:
|
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- jeida-18
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@@ -96,22 +85,6 @@ properties:
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||||
If set, reverse the bit order described in the data mappings below on all
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data lanes, transmitting bits for slots 6 to 0 instead of 0 to 6.
|
||||
|
||||
port: true
|
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ports: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- data-mapping
|
||||
- width-mm
|
||||
- height-mm
|
||||
- panel-timing
|
||||
|
||||
oneOf:
|
||||
- required:
|
||||
- port
|
||||
- required:
|
||||
- ports
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
@@ -0,0 +1,77 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,aal.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek display adaptive ambient light processor
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
Mediatek display adaptive ambient light processor, namely AAL,
|
||||
is responsible for backlight power saving and sunlight visibility improving.
|
||||
AAL device node must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
|
||||
for details.
|
||||
|
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properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt8173-disp-aal
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt2712-disp-aal
|
||||
- mediatek,mt8183-disp-aal
|
||||
- mediatek,mt8192-disp-aal
|
||||
- mediatek,mt8195-disp-aal
|
||||
- enum:
|
||||
- mediatek,mt8173-disp-aal
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
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interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description: A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: AAL Clock
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description: The register of client driver can be configured by gce with
|
||||
4 arguments defined in this property, such as phandle of gce, subsys id,
|
||||
register offset and size. Each GCE subsys id is mapping to a client
|
||||
defined in the header include/dt-bindings/gce/<chip>-gce.h.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- power-domains
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
aal@14015000 {
|
||||
compatible = "mediatek,mt8173-disp-aal";
|
||||
reg = <0 0x14015000 0 0x1000>;
|
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interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_AAL>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
|
||||
};
|
||||
@@ -0,0 +1,76 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,ccorr.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek display color correction
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
Mediatek display color correction, namely CCORR, reproduces correct color
|
||||
on panels with different color gamut.
|
||||
CCORR device node must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
|
||||
for details.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt8183-disp-ccorr
|
||||
- items:
|
||||
- const: mediatek,mt8192-disp-ccorr
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8195-disp-ccorr
|
||||
- enum:
|
||||
- mediatek,mt8192-disp-ccorr
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description: A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: CCORR Clock
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description: The register of client driver can be configured by gce with
|
||||
4 arguments defined in this property, such as phandle of gce, subsys id,
|
||||
register offset and size. Each GCE subsys id is mapping to a client
|
||||
defined in the header include/dt-bindings/gce/<chip>-gce.h.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- power-domains
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
ccorr0: ccorr@1400f000 {
|
||||
compatible = "mediatek,mt8183-disp-ccorr";
|
||||
reg = <0 0x1400f000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
|
||||
clocks = <&mmsys CLK_MM_DISP_CCORR0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
|
||||
};
|
||||
@@ -0,0 +1,86 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,color.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek display color processor
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
Mediatek display color processor, namely COLOR, provides hue, luma and
|
||||
saturation adjustments to get better picture quality and to have one panel
|
||||
resemble the other in their output characteristics.
|
||||
COLOR device node must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
|
||||
for details.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt2701-disp-color
|
||||
- items:
|
||||
- const: mediatek,mt8167-disp-color
|
||||
- items:
|
||||
- const: mediatek,mt8173-disp-color
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt7623-disp-color
|
||||
- mediatek,mt2712-disp-color
|
||||
- enum:
|
||||
- mediatek,mt2701-disp-color
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8183-disp-color
|
||||
- mediatek,mt8192-disp-color
|
||||
- mediatek,mt8195-disp-color
|
||||
- enum:
|
||||
- mediatek,mt8173-disp-color
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description: A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: COLOR Clock
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description: The register of client driver can be configured by gce with
|
||||
4 arguments defined in this property, such as phandle of gce, subsys id,
|
||||
register offset and size. Each GCE subsys id is mapping to a client
|
||||
defined in the header include/dt-bindings/gce/<chip>-gce.h.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- power-domains
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
color0: color@14013000 {
|
||||
compatible = "mediatek,mt8173-disp-color";
|
||||
reg = <0 0x14013000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
|
||||
};
|
||||
@@ -1,210 +0,0 @@
|
||||
Mediatek display subsystem
|
||||
==========================
|
||||
|
||||
The Mediatek display subsystem consists of various DISP function blocks in the
|
||||
MMSYS register space. The connections between them can be configured by output
|
||||
and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
|
||||
of frame signal are distributed to the other function blocks by a DISP_MUTEX
|
||||
function block.
|
||||
|
||||
All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml.
|
||||
|
||||
DISP function blocks
|
||||
====================
|
||||
|
||||
A display stream starts at a source function block that reads pixel data from
|
||||
memory and ends with a sink function block that drives pixels on a display
|
||||
interface, or writes pixels back to memory. All DISP function blocks have
|
||||
their own register space, interrupt, and clock gate. The blocks that can
|
||||
access memory additionally have to list the IOMMU and local arbiter they are
|
||||
connected to.
|
||||
|
||||
For a description of the display interface sink function blocks, see
|
||||
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
|
||||
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml.
|
||||
|
||||
Required properties (all function blocks):
|
||||
- compatible: "mediatek,<chip>-disp-<function>", one of
|
||||
"mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
|
||||
"mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc)
|
||||
"mediatek,<chip>-disp-rdma" - read DMA / line buffer
|
||||
"mediatek,<chip>-disp-wdma" - write DMA
|
||||
"mediatek,<chip>-disp-ccorr" - color correction
|
||||
"mediatek,<chip>-disp-color" - color processor
|
||||
"mediatek,<chip>-disp-dither" - dither
|
||||
"mediatek,<chip>-disp-aal" - adaptive ambient light controller
|
||||
"mediatek,<chip>-disp-gamma" - gamma correction
|
||||
"mediatek,<chip>-disp-merge" - merge streams from two RDMA sources
|
||||
"mediatek,<chip>-disp-postmask" - control round corner for display frame
|
||||
"mediatek,<chip>-disp-split" - split stream to two encoders
|
||||
"mediatek,<chip>-disp-ufoe" - data compression engine
|
||||
"mediatek,<chip>-dsi" - DSI controller, see mediatek,dsi.txt
|
||||
"mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
|
||||
"mediatek,<chip>-disp-mutex" - display mutex
|
||||
"mediatek,<chip>-disp-od" - overdrive
|
||||
the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and mt8192.
|
||||
- reg: Physical base address and length of the function block register space
|
||||
- interrupts: The interrupt signal from the function block (required, except for
|
||||
merge and split function blocks).
|
||||
- clocks: device clocks
|
||||
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
|
||||
For most function blocks this is just a single clock input. Only the DSI and
|
||||
DPI controller nodes have multiple clock inputs. These are documented in
|
||||
mediatek,dsi.txt and mediatek,dpi.txt, respectively.
|
||||
An exception is that the mt8183 mutex is always free running with no clocks property.
|
||||
|
||||
Required properties (DMA function blocks):
|
||||
- compatible: Should be one of
|
||||
"mediatek,<chip>-disp-ovl"
|
||||
"mediatek,<chip>-disp-rdma"
|
||||
"mediatek,<chip>-disp-wdma"
|
||||
the supported chips are mt2701, mt8167 and mt8173.
|
||||
- iommus: Should point to the respective IOMMU block with master port as
|
||||
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
|
||||
for details.
|
||||
|
||||
Optional properties (RDMA function blocks):
|
||||
- mediatek,rdma-fifo-size: rdma fifo size may be different even in same SOC, add this
|
||||
property to the corresponding rdma
|
||||
the value is the Max value which defined in hardware data sheet.
|
||||
mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
|
||||
mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
|
||||
mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
|
||||
|
||||
Examples:
|
||||
|
||||
mmsys: clock-controller@14000000 {
|
||||
compatible = "mediatek,mt8173-mmsys", "syscon";
|
||||
reg = <0 0x14000000 0 0x1000>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
ovl0: ovl@1400c000 {
|
||||
compatible = "mediatek,mt8173-disp-ovl";
|
||||
reg = <0 0x1400c000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OVL0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_OVL0>;
|
||||
};
|
||||
|
||||
ovl1: ovl@1400d000 {
|
||||
compatible = "mediatek,mt8173-disp-ovl";
|
||||
reg = <0 0x1400d000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OVL1>;
|
||||
iommus = <&iommu M4U_PORT_DISP_OVL1>;
|
||||
};
|
||||
|
||||
rdma0: rdma@1400e000 {
|
||||
compatible = "mediatek,mt8173-disp-rdma";
|
||||
reg = <0 0x1400e000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
|
||||
mediatek,rdma-fifosize = <8192>;
|
||||
};
|
||||
|
||||
rdma1: rdma@1400f000 {
|
||||
compatible = "mediatek,mt8173-disp-rdma";
|
||||
reg = <0 0x1400f000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
|
||||
iommus = <&iommu M4U_PORT_DISP_RDMA1>;
|
||||
};
|
||||
|
||||
rdma2: rdma@14010000 {
|
||||
compatible = "mediatek,mt8173-disp-rdma";
|
||||
reg = <0 0x14010000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_RDMA2>;
|
||||
iommus = <&iommu M4U_PORT_DISP_RDMA2>;
|
||||
};
|
||||
|
||||
wdma0: wdma@14011000 {
|
||||
compatible = "mediatek,mt8173-disp-wdma";
|
||||
reg = <0 0x14011000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_WDMA0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_WDMA0>;
|
||||
};
|
||||
|
||||
wdma1: wdma@14012000 {
|
||||
compatible = "mediatek,mt8173-disp-wdma";
|
||||
reg = <0 0x14012000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_WDMA1>;
|
||||
iommus = <&iommu M4U_PORT_DISP_WDMA1>;
|
||||
};
|
||||
|
||||
color0: color@14013000 {
|
||||
compatible = "mediatek,mt8173-disp-color";
|
||||
reg = <0 0x14013000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
|
||||
};
|
||||
|
||||
color1: color@14014000 {
|
||||
compatible = "mediatek,mt8173-disp-color";
|
||||
reg = <0 0x14014000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_COLOR1>;
|
||||
};
|
||||
|
||||
aal@14015000 {
|
||||
compatible = "mediatek,mt8173-disp-aal";
|
||||
reg = <0 0x14015000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_AAL>;
|
||||
};
|
||||
|
||||
gamma@14016000 {
|
||||
compatible = "mediatek,mt8173-disp-gamma";
|
||||
reg = <0 0x14016000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_GAMMA>;
|
||||
};
|
||||
|
||||
ufoe@1401a000 {
|
||||
compatible = "mediatek,mt8173-disp-ufoe";
|
||||
reg = <0 0x1401a000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_UFOE>;
|
||||
};
|
||||
|
||||
dsi0: dsi@1401b000 {
|
||||
/* See mediatek,dsi.txt for details */
|
||||
};
|
||||
|
||||
dpi0: dpi@1401d000 {
|
||||
/* See mediatek,dpi.txt for details */
|
||||
};
|
||||
|
||||
mutex: mutex@14020000 {
|
||||
compatible = "mediatek,mt8173-disp-mutex";
|
||||
reg = <0 0x14020000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_MUTEX_32K>;
|
||||
};
|
||||
|
||||
od@14023000 {
|
||||
compatible = "mediatek,mt8173-disp-od";
|
||||
reg = <0 0x14023000 0 0x1000>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OD>;
|
||||
};
|
||||
@@ -0,0 +1,76 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,dither.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek display dither processor
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
Mediatek display dither processor, namely DITHER, works by approximating
|
||||
unavailable colors with available colors and by mixing and matching available
|
||||
colors to mimic unavailable ones.
|
||||
DITHER device node must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
|
||||
for details.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt8183-disp-dither
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8192-disp-dither
|
||||
- mediatek,mt8195-disp-dither
|
||||
- enum:
|
||||
- mediatek,mt8183-disp-dither
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description: A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: DITHER Clock
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description: The register of client driver can be configured by gce with
|
||||
4 arguments defined in this property, such as phandle of gce, subsys id,
|
||||
register offset and size. Each GCE subsys id is mapping to a client
|
||||
defined in the header include/dt-bindings/gce/<chip>-gce.h.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- power-domains
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
dither0: dither@14012000 {
|
||||
compatible = "mediatek,mt8183-disp-dither";
|
||||
reg = <0 0x14012000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
|
||||
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
|
||||
};
|
||||
@@ -0,0 +1,71 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: mediatek display DSC controller
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
The DSC standard is a specification of the algorithms used for
|
||||
compressing and decompressing image display streams, including
|
||||
the specification of the syntax and semantics of the compressed
|
||||
video bit stream. DSC is designed for real-time systems with
|
||||
real-time compression, transmission, decompression and Display.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt8195-disp-dsc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: DSC Wrapper Clock
|
||||
|
||||
power-domains:
|
||||
description: A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description:
|
||||
The register of client driver can be configured by gce with 4 arguments
|
||||
defined in this property, such as phandle of gce, subsys id,
|
||||
register offset and size.
|
||||
Each subsys id is mapping to a base address of display function blocks
|
||||
register which is defined in the gce header
|
||||
include/dt-bindings/gce/<chip>-gce.h.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- power-domains
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
dsc0: disp_dsc_wrap@1c009000 {
|
||||
compatible = "mediatek,mt8195-disp-dsc";
|
||||
reg = <0 0x1c009000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
|
||||
clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
|
||||
mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
|
||||
};
|
||||
@@ -0,0 +1,147 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek Ethdr Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
ETHDR is designed for HDR video and graphics conversion in the external display path.
|
||||
It handles multiple HDR input types and performs tone mapping, color space/color
|
||||
format conversion, and then combine different layers, output the required HDR or
|
||||
SDR signal to the subsequent display path. This engine is composed of two video
|
||||
frontends, two graphic frontends, one video backend and a mixer. ETHDR has two
|
||||
DMA function blocks, DS and ADL. These two function blocks read the pre-programmed
|
||||
registers from DRAM and set them to HW in the v-blanking period.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: mediatek,mt8195-disp-ethdr
|
||||
reg:
|
||||
maxItems: 7
|
||||
reg-names:
|
||||
items:
|
||||
- const: mixer
|
||||
- const: vdo_fe0
|
||||
- const: vdo_fe1
|
||||
- const: gfx_fe0
|
||||
- const: gfx_fe1
|
||||
- const: vdo_be
|
||||
- const: adl_ds
|
||||
interrupts:
|
||||
minItems: 1
|
||||
iommus:
|
||||
description: The compatible property is DMA function blocks.
|
||||
Should point to the respective IOMMU block with master port as argument,
|
||||
see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
|
||||
details.
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
clocks:
|
||||
items:
|
||||
- description: mixer clock
|
||||
- description: video frontend 0 clock
|
||||
- description: video frontend 1 clock
|
||||
- description: graphic frontend 0 clock
|
||||
- description: graphic frontend 1 clock
|
||||
- description: video backend clock
|
||||
- description: autodownload and menuload clock
|
||||
- description: video frontend 0 async clock
|
||||
- description: video frontend 1 async clock
|
||||
- description: graphic frontend 0 async clock
|
||||
- description: graphic frontend 1 async clock
|
||||
- description: video backend async clock
|
||||
- description: ethdr top clock
|
||||
clock-names:
|
||||
items:
|
||||
- const: mixer
|
||||
- const: vdo_fe0
|
||||
- const: vdo_fe1
|
||||
- const: gfx_fe0
|
||||
- const: gfx_fe1
|
||||
- const: vdo_be
|
||||
- const: adl_ds
|
||||
- const: vdo_fe0_async
|
||||
- const: vdo_fe1_async
|
||||
- const: gfx_fe0_async
|
||||
- const: gfx_fe1_async
|
||||
- const: vdo_be_async
|
||||
- const: ethdr_top
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
resets:
|
||||
maxItems: 5
|
||||
mediatek,gce-client-reg:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
description: The register of display function block to be set by gce.
|
||||
There are 4 arguments in this property, gce node, subsys id, offset and
|
||||
register size. The subsys id is defined in the gce header of each chips
|
||||
include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
|
||||
display function block.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- interrupts
|
||||
- power-domains
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
disp_ethdr@1c114000 {
|
||||
compatible = "mediatek,mt8195-disp-ethdr";
|
||||
reg = <0 0x1c114000 0 0x1000>,
|
||||
<0 0x1c115000 0 0x1000>,
|
||||
<0 0x1c117000 0 0x1000>,
|
||||
<0 0x1c119000 0 0x1000>,
|
||||
<0 0x1c11A000 0 0x1000>,
|
||||
<0 0x1c11B000 0 0x1000>,
|
||||
<0 0x1c11C000 0 0x1000>;
|
||||
reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
|
||||
"vdo_be", "adl_ds";
|
||||
mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
|
||||
<&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,
|
||||
<&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,
|
||||
<&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,
|
||||
<&gce0 SUBSYS_1c11XXXX 0xA000 0x1000>,
|
||||
<&gce0 SUBSYS_1c11XXXX 0xB000 0x1000>,
|
||||
<&gce0 SUBSYS_1c11XXXX 0xC000 0x1000>;
|
||||
clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
|
||||
<&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
|
||||
<&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
|
||||
<&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
|
||||
<&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
|
||||
<&vdosys1 CLK_VDO1_HDR_VDO_BE>,
|
||||
<&vdosys1 CLK_VDO1_26M_SLOW>,
|
||||
<&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
|
||||
<&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
|
||||
<&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
|
||||
<&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
|
||||
<&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
|
||||
<&topckgen CLK_TOP_ETHDR_SEL>;
|
||||
clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
|
||||
"vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
|
||||
"gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
|
||||
"ethdr_top";
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
|
||||
iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
|
||||
<&iommu_vpp M4U_PORT_L3_HDR_ADL>;
|
||||
interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
|
||||
resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
|
||||
<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
|
||||
<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
|
||||
<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
|
||||
<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
|
||||
};
|
||||
|
||||
...
|
||||
@@ -0,0 +1,77 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,gamma.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek display gamma correction
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
Mediatek display gamma correction, namely GAMMA, provides a nonlinear
|
||||
operation used to adjust luminance in display system.
|
||||
GAMMA device node must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
|
||||
for details.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt8173-disp-gamma
|
||||
- items:
|
||||
- const: mediatek,mt8183-disp-gamma
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8192-disp-gamma
|
||||
- mediatek,mt8195-disp-gamma
|
||||
- enum:
|
||||
- mediatek,mt8183-disp-gamma
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description: A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: GAMMA Clock
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description: The register of client driver can be configured by gce with
|
||||
4 arguments defined in this property, such as phandle of gce, subsys id,
|
||||
register offset and size. Each GCE subsys id is mapping to a client
|
||||
defined in the header include/dt-bindings/gce/<chip>-gce.h.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- power-domains
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
gamma@14016000 {
|
||||
compatible = "mediatek,mt8173-disp-gamma";
|
||||
reg = <0 0x14016000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_GAMMA>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
|
||||
};
|
||||
@@ -0,0 +1,110 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek display merge
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
Mediatek display merge, namely MERGE, is used to merge two slice-per-line
|
||||
inputs into one side-by-side output.
|
||||
MERGE device node must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
|
||||
for details.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt8173-disp-merge
|
||||
- items:
|
||||
- const: mediatek,mt8195-disp-merge
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description: A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
items:
|
||||
- description: MERGE Clock
|
||||
- description: MERGE Async Clock
|
||||
Controlling the synchronous process between MERGE and other display
|
||||
function blocks cross clock domain.
|
||||
|
||||
clock-names:
|
||||
maxItems: 2
|
||||
items:
|
||||
- const: merge
|
||||
- const: merge_async
|
||||
|
||||
mediatek,merge-fifo-en:
|
||||
description:
|
||||
The setting of merge fifo is mainly provided for the display latency
|
||||
buffer to ensure that the back-end panel display data will not be
|
||||
underrun, a little more data is needed in the fifo.
|
||||
According to the merge fifo settings, when the water level is detected
|
||||
to be insufficient, it will trigger RDMA sending ultra and preulra
|
||||
command to SMI to speed up the data rate.
|
||||
type: boolean
|
||||
|
||||
mediatek,merge-mute:
|
||||
description: Support mute function. Mute the content of merge output.
|
||||
type: boolean
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description: The register of client driver can be configured by gce with
|
||||
4 arguments defined in this property, such as phandle of gce, subsys id,
|
||||
register offset and size. Each GCE subsys id is mapping to a client
|
||||
defined in the header include/dt-bindings/gce/<chip>-gce.h.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
description: reset controller
|
||||
See Documentation/devicetree/bindings/reset/reset.txt for details.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- power-domains
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
merge@14017000 {
|
||||
compatible = "mediatek,mt8173-disp-merge";
|
||||
reg = <0 0x14017000 0 0x1000>;
|
||||
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_MERGE>;
|
||||
};
|
||||
|
||||
merge5: disp_vpp_merge5@1c110000 {
|
||||
compatible = "mediatek,mt8195-disp-merge";
|
||||
reg = <0 0x1c110000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
|
||||
<&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
|
||||
clock-names = "merge","merge_async";
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
|
||||
mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
|
||||
mediatek,merge-fifo-en = <1>;
|
||||
resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
|
||||
};
|
||||
@@ -0,0 +1,83 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek mutex
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
Mediatek mutex, namely MUTEX, is used to send the triggers signals called
|
||||
Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
|
||||
data path or MDP data path.
|
||||
In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
|
||||
the shadow register.
|
||||
MUTEX device node must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
|
||||
for details.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt2701-disp-mutex
|
||||
- items:
|
||||
- const: mediatek,mt2712-disp-mutex
|
||||
- items:
|
||||
- const: mediatek,mt8167-disp-mutex
|
||||
- items:
|
||||
- const: mediatek,mt8173-disp-mutex
|
||||
- items:
|
||||
- const: mediatek,mt8183-disp-mutex
|
||||
- items:
|
||||
- const: mediatek,mt8192-disp-mutex
|
||||
- items:
|
||||
- const: mediatek,mt8195-disp-mutex
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description: A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: MUTEX Clock
|
||||
|
||||
mediatek,gce-events:
|
||||
description:
|
||||
The event id which is mapping to the specific hardware event signal
|
||||
to gce. The event id is defined in the gce header
|
||||
include/dt-bindings/gce/<chip>-gce.h of each chips.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- power-domains
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
mutex: mutex@14020000 {
|
||||
compatible = "mediatek,mt8173-disp-mutex";
|
||||
reg = <0 0x14020000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_MUTEX_32K>;
|
||||
mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
|
||||
<CMDQ_EVENT_MUTEX1_STREAM_EOF>;
|
||||
};
|
||||
@@ -0,0 +1,53 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,od.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek display overdirve
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
Mediatek display overdrive, namely OD, increases the transition values
|
||||
of pixels between consecutive frames to make LCD rotate faster.
|
||||
OD device node must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
|
||||
for details.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt2712-disp-od
|
||||
- items:
|
||||
- const: mediatek,mt8173-disp-od
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: OD Clock
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
od@14023000 {
|
||||
compatible = "mediatek,mt8173-disp-od";
|
||||
reg = <0 0x14023000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OD>;
|
||||
};
|
||||
@@ -0,0 +1,78 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl-2l.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek display overlay 2 layer
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
Mediatek display overlay 2 layer, namely OVL-2L, provides 2 more layer
|
||||
for OVL.
|
||||
OVL-2L device node must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
|
||||
for details.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt8183-disp-ovl-2l
|
||||
- items:
|
||||
- const: mediatek,mt8192-disp-ovl-2l
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description: A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: OVL-2L Clock
|
||||
|
||||
iommus:
|
||||
description:
|
||||
This property should point to the respective IOMMU block with master port as argument,
|
||||
see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description: The register of client driver can be configured by gce with
|
||||
4 arguments defined in this property, such as phandle of gce, subsys id,
|
||||
register offset and size. Each GCE subsys id is mapping to a client
|
||||
defined in the header include/dt-bindings/gce/<chip>-gce.h.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- power-domains
|
||||
- clocks
|
||||
- iommus
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
ovl_2l0: ovl@14009000 {
|
||||
compatible = "mediatek,mt8183-disp-ovl-2l";
|
||||
reg = <0 0x14009000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
|
||||
iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
|
||||
};
|
||||
@@ -0,0 +1,93 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek display overlay
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
Mediatek display overlay, namely OVL, can do alpha blending from
|
||||
the memory.
|
||||
OVL device node must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
|
||||
for details.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt2701-disp-ovl
|
||||
- items:
|
||||
- const: mediatek,mt8173-disp-ovl
|
||||
- items:
|
||||
- const: mediatek,mt8183-disp-ovl
|
||||
- items:
|
||||
- const: mediatek,mt8192-disp-ovl
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt7623-disp-ovl
|
||||
- mediatek,mt2712-disp-ovl
|
||||
- enum:
|
||||
- mediatek,mt2701-disp-ovl
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8195-disp-ovl
|
||||
- enum:
|
||||
- mediatek,mt8183-disp-ovl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description: A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: OVL Clock
|
||||
|
||||
iommus:
|
||||
description:
|
||||
This property should point to the respective IOMMU block with master port as argument,
|
||||
see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description: The register of client driver can be configured by gce with
|
||||
4 arguments defined in this property, such as phandle of gce, subsys id,
|
||||
register offset and size. Each GCE subsys id is mapping to a client
|
||||
defined in the header include/dt-bindings/gce/<chip>-gce.h.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- power-domains
|
||||
- clocks
|
||||
- iommu
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
ovl0: ovl@1400c000 {
|
||||
compatible = "mediatek,mt8173-disp-ovl";
|
||||
reg = <0 0x1400c000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OVL0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_OVL0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
|
||||
};
|
||||
@@ -0,0 +1,69 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,postmask.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek display postmask
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
Mediatek display postmask, namely POSTMASK, provides round corner pattern
|
||||
generation.
|
||||
POSTMASK device node must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
|
||||
for details.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: mediatek,mt8192-disp-postmask
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description: A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: POSTMASK Clock
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description: The register of client driver can be configured by gce with
|
||||
4 arguments defined in this property, such as phandle of gce, subsys id,
|
||||
register offset and size. Each GCE subsys id is mapping to a client
|
||||
defined in the header include/dt-bindings/gce/<chip>-gce.h.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- power-domains
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
postmask0: postmask@1400d000 {
|
||||
compatible = "mediatek,mt8192-disp-postmask";
|
||||
reg = <0 0x1400d000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
|
||||
clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user