spi: Replace all spi->chip_select and spi->cs_gpiod references with function call

Supporting multi-cs in spi drivers would require the chip_select & cs_gpiod
members of struct spi_device to be an array. But changing the type of these
members to array would break the spi driver functionality. To make the
transition smoother introduced four new APIs to get/set the
spi->chip_select & spi->cs_gpiod and replaced all spi->chip_select and
spi->cs_gpiod references with get or set API calls.
While adding multi-cs support in further patches the chip_select & cs_gpiod
members of the spi_device structure would be converted to arrays & the
"idx" parameter of the APIs would be used as array index i.e.,
spi->chip_select[idx] & spi->cs_gpiod[idx] respectively.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
Acked-by: Heiko Stuebner <heiko@sntech.de> # Rockchip drivers
Reviewed-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org> # Aspeed driver
Reviewed-by: Dhruva Gole <d-gole@ti.com> # SPI Cadence QSPI
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> # spi-stm32-qspi
Acked-by: William Zhang <william.zhang@broadcom.com> # bcm63xx-hsspi driver
Reviewed-by: Serge Semin <fancer.lancer@gmail.com> # DW SSI part
Link: https://lore.kernel.org/r/167847070432.26.15076794204368669839@mailman-core.alsa-project.org
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Amit Kumar Mahapatra via Alsa-devel
2023-03-10 23:02:03 +05:30
committed by Mark Brown
parent 21d19e601f
commit 9e264f3f85
92 changed files with 333 additions and 328 deletions

View File

@@ -80,7 +80,7 @@ static void altera_spi_set_cs(struct spi_device *spi, bool is_high)
altr_spi_writel(hw, ALTERA_SPI_TARGET_SEL, 0);
} else {
altr_spi_writel(hw, ALTERA_SPI_TARGET_SEL,
BIT(spi->chip_select));
BIT(spi_get_chipselect(spi, 0)));
hw->imr |= ALTERA_SPI_CONTROL_SSO_MSK;
altr_spi_writel(hw, ALTERA_SPI_CONTROL, hw->imr);
}

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@@ -347,7 +347,7 @@ fin_msg:
case AMD_SPI_V1:
break;
case AMD_SPI_V2:
amd_spi_clear_chip(amd_spi, message->spi->chip_select);
amd_spi_clear_chip(amd_spi, spi_get_chipselect(message->spi, 0));
break;
default:
return -ENODEV;
@@ -364,7 +364,7 @@ static int amd_spi_master_transfer(struct spi_master *master,
struct amd_spi *amd_spi = spi_master_get_devdata(master);
struct spi_device *spi = msg->spi;
amd_spi_select_chip(amd_spi, spi->chip_select);
amd_spi_select_chip(amd_spi, spi_get_chipselect(spi, 0));
/*
* Extract spi_transfers from the spi message and

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@@ -125,7 +125,7 @@ static int ar934x_spi_transfer_one_message(struct spi_controller *ctlr,
iowrite32(reg, sp->base + AR934X_SPI_DATAOUT);
}
reg = AR934X_SPI_SHIFT_VAL(spi->chip_select, term,
reg = AR934X_SPI_SHIFT_VAL(spi_get_chipselect(spi, 0), term,
trx_cur * 8);
iowrite32(reg, sp->base + AR934X_SPI_REG_SHIFT_CTRL);
stat = readl_poll_timeout(

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@@ -437,9 +437,9 @@ static void a3700_spi_set_cs(struct spi_device *spi, bool enable)
struct a3700_spi *a3700_spi = spi_controller_get_devdata(spi->controller);
if (!enable)
a3700_spi_activate_cs(a3700_spi, spi->chip_select);
a3700_spi_activate_cs(a3700_spi, spi_get_chipselect(spi, 0));
else
a3700_spi_deactivate_cs(a3700_spi, spi->chip_select);
a3700_spi_deactivate_cs(a3700_spi, spi_get_chipselect(spi, 0));
}
static void a3700_spi_header_set(struct a3700_spi *a3700_spi)

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@@ -296,7 +296,7 @@ static const struct aspeed_spi_data ast2400_spi_data;
static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
{
struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
struct aspeed_spi_chip *chip = &aspi->chips[mem->spi->chip_select];
struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(mem->spi, 0)];
u32 addr_mode, addr_mode_backup;
u32 ctl_val;
int ret = 0;
@@ -377,7 +377,8 @@ static const char *aspeed_spi_get_name(struct spi_mem *mem)
struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
struct device *dev = aspi->dev;
return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select);
return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev),
spi_get_chipselect(mem->spi, 0));
}
struct aspeed_spi_window {
@@ -553,7 +554,7 @@ static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip);
static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
{
struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(desc->mem->spi, 0)];
struct spi_mem_op *op = &desc->info.op_tmpl;
u32 ctl_val;
int ret = 0;
@@ -620,7 +621,7 @@ static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc,
u64 offset, size_t len, void *buf)
{
struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(desc->mem->spi, 0)];
/* Switch to USER command mode if mapping window is too small */
if (chip->ahb_window_size < offset + len) {
@@ -670,7 +671,7 @@ static int aspeed_spi_setup(struct spi_device *spi)
{
struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master);
const struct aspeed_spi_data *data = aspi->data;
unsigned int cs = spi->chip_select;
unsigned int cs = spi_get_chipselect(spi, 0);
struct aspeed_spi_chip *chip = &aspi->chips[cs];
chip->aspi = aspi;
@@ -697,7 +698,7 @@ static int aspeed_spi_setup(struct spi_device *spi)
static void aspeed_spi_cleanup(struct spi_device *spi)
{
struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master);
unsigned int cs = spi->chip_select;
unsigned int cs = spi_get_chipselect(spi, 0);
aspeed_spi_chip_enable(aspi, cs, false);

View File

@@ -390,7 +390,7 @@ static int at91_usart_spi_setup(struct spi_device *spi)
dev_dbg(&spi->dev,
"setup: bpw %u mode 0x%x -> mr %d %08x\n",
spi->bits_per_word, spi->mode, spi->chip_select, mr);
spi->bits_per_word, spi->mode, spi_get_chipselect(spi, 0), mr);
return 0;
}

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@@ -71,7 +71,7 @@ static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
{
struct ath79_spi *sp = ath79_spidev_to_sp(spi);
int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
u32 cs_bit = AR71XX_SPI_IOC_CS(spi_get_chipselect(spi, 0));
if (cs_high)
sp->ioc_base |= cs_bit;
@@ -140,7 +140,7 @@ static int ath79_exec_mem_op(struct spi_mem *mem,
struct ath79_spi *sp = ath79_spidev_to_sp(mem->spi);
/* Ensures that reading is performed on device connected to hardware cs0 */
if (mem->spi->chip_select || mem->spi->cs_gpiod)
if (spi_get_chipselect(mem->spi, 0) || spi_get_csgpiod(mem->spi, 0))
return -ENOTSUPP;
/* Only use for fast-read op. */

View File

@@ -327,10 +327,10 @@ static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
int chip_select;
u32 mr;
if (spi->cs_gpiod)
if (spi_get_csgpiod(spi, 0))
chip_select = as->native_cs_for_gpio;
else
chip_select = spi->chip_select;
chip_select = spi_get_chipselect(spi, 0);
if (atmel_spi_is_v2(as)) {
spi_writel(as, CSR0 + 4 * chip_select, asd->csr);
@@ -378,10 +378,10 @@ static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
int chip_select;
u32 mr;
if (spi->cs_gpiod)
if (spi_get_csgpiod(spi, 0))
chip_select = as->native_cs_for_gpio;
else
chip_select = spi->chip_select;
chip_select = spi_get_chipselect(spi, 0);
/* only deactivate *this* device; sometimes transfers to
* another device may be active when this routine is called.
@@ -394,7 +394,7 @@ static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
dev_dbg(&spi->dev, "DEactivate NPCS, mr %08x\n", mr);
if (!spi->cs_gpiod)
if (!spi_get_csgpiod(spi, 0))
spi_writel(as, CR, SPI_BIT(LASTXFER));
}
@@ -800,10 +800,10 @@ static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
unsigned long bus_hz;
int chip_select;
if (spi->cs_gpiod)
if (spi_get_csgpiod(spi, 0))
chip_select = as->native_cs_for_gpio;
else
chip_select = spi->chip_select;
chip_select = spi_get_chipselect(spi, 0);
/* v1 chips start out at half the peripheral bus speed. */
bus_hz = as->spi_clk;
@@ -1189,7 +1189,7 @@ static int atmel_spi_setup(struct spi_device *spi)
as = spi_controller_get_devdata(spi->controller);
/* see notes above re chipselect */
if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH)) {
if (!spi_get_csgpiod(spi, 0) && (spi->mode & SPI_CS_HIGH)) {
dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
return -EINVAL;
}
@@ -1201,16 +1201,16 @@ static int atmel_spi_setup(struct spi_device *spi)
*/
initialize_native_cs_for_gpio(as);
if (spi->cs_gpiod && as->native_cs_free) {
if (spi_get_csgpiod(spi, 0) && as->native_cs_free) {
dev_err(&spi->dev,
"No native CS available to support this GPIO CS\n");
return -EBUSY;
}
if (spi->cs_gpiod)
if (spi_get_csgpiod(spi, 0))
chip_select = as->native_cs_for_gpio;
else
chip_select = spi->chip_select;
chip_select = spi_get_chipselect(spi, 0);
csr = SPI_BF(BITS, bits - 8);
if (spi->mode & SPI_CPOL)
@@ -1218,7 +1218,7 @@ static int atmel_spi_setup(struct spi_device *spi)
if (!(spi->mode & SPI_CPHA))
csr |= SPI_BIT(NCPHA);
if (!spi->cs_gpiod)
if (!spi_get_csgpiod(spi, 0))
csr |= SPI_BIT(CSAAT);
csr |= SPI_BF(DLYBS, 0);
@@ -1244,7 +1244,7 @@ static int atmel_spi_setup(struct spi_device *spi)
dev_dbg(&spi->dev,
"setup: bpw %u mode 0x%x -> csr%d %08x\n",
bits, spi->mode, spi->chip_select, csr);
bits, spi->mode, spi_get_chipselect(spi, 0), csr);
if (!atmel_spi_is_v2(as))
spi_writel(as, CSR0 + 4 * chip_select, csr);

View File

@@ -166,7 +166,7 @@ static void au1550_spi_chipsel(struct spi_device *spi, int value)
switch (value) {
case BITBANG_CS_INACTIVE:
if (hw->pdata->deactivate_cs)
hw->pdata->deactivate_cs(hw->pdata, spi->chip_select,
hw->pdata->deactivate_cs(hw->pdata, spi_get_chipselect(spi, 0),
cspol);
break;
@@ -211,7 +211,7 @@ static void au1550_spi_chipsel(struct spi_device *spi, int value)
} while ((stat & PSC_SPISTAT_DR) == 0);
if (hw->pdata->activate_cs)
hw->pdata->activate_cs(hw->pdata, spi->chip_select,
hw->pdata->activate_cs(hw->pdata, spi_get_chipselect(spi, 0),
cspol);
break;
}

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@@ -193,7 +193,7 @@ static void spi_engine_gen_cs(struct spi_engine_program *p, bool dry,
unsigned int mask = 0xff;
if (assert)
mask ^= BIT(spi->chip_select);
mask ^= BIT(spi_get_chipselect(spi, 0));
spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_ASSERT(1, mask));
}

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@@ -986,7 +986,7 @@ static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
if (has_bspi(qspi))
mspi_cdram &= ~1;
else
mspi_cdram |= (~(1 << spi->chip_select) &
mspi_cdram |= (~(1 << spi_get_chipselect(spi, 0)) &
MSPI_CDRAM_PCS);
write_cdram_slot(qspi, slot, mspi_cdram);
@@ -1046,8 +1046,8 @@ static int bcm_qspi_bspi_exec_mem_op(struct spi_device *spi,
return -EIO;
from = op->addr.val;
if (!spi->cs_gpiod)
bcm_qspi_chip_select(qspi, spi->chip_select);
if (!spi_get_csgpiod(spi, 0))
bcm_qspi_chip_select(qspi, spi_get_chipselect(spi, 0));
bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
/*
@@ -1126,8 +1126,8 @@ static int bcm_qspi_transfer_one(struct spi_master *master,
int slots;
unsigned long timeo = msecs_to_jiffies(100);
if (!spi->cs_gpiod)
bcm_qspi_chip_select(qspi, spi->chip_select);
if (!spi_get_csgpiod(spi, 0))
bcm_qspi_chip_select(qspi, spi_get_chipselect(spi, 0));
qspi->trans_pos.trans = trans;
qspi->trans_pos.byte = 0;

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@@ -1274,9 +1274,9 @@ static int bcm2835_spi_setup(struct spi_device *spi)
* The SPI core has successfully requested the CS GPIO line from the
* device tree, so we are done.
*/
if (spi->cs_gpiod)
if (spi_get_csgpiod(spi, 0))
return 0;
if (spi->chip_select > 1) {
if (spi_get_chipselect(spi, 0) > 1) {
/* error in the case of native CS requested with CS > 1
* officially there is a CS2, but it is not documented
* which GPIO is connected with that...
@@ -1301,18 +1301,19 @@ static int bcm2835_spi_setup(struct spi_device *spi)
if (!chip)
return 0;
spi->cs_gpiod = gpiochip_request_own_desc(chip, 8 - spi->chip_select,
DRV_NAME,
GPIO_LOOKUP_FLAGS_DEFAULT,
GPIOD_OUT_LOW);
if (IS_ERR(spi->cs_gpiod)) {
ret = PTR_ERR(spi->cs_gpiod);
spi_set_csgpiod(spi, 0, gpiochip_request_own_desc(chip,
8 - (spi_get_chipselect(spi, 0)),
DRV_NAME,
GPIO_LOOKUP_FLAGS_DEFAULT,
GPIOD_OUT_LOW));
if (IS_ERR(spi_get_csgpiod(spi, 0))) {
ret = PTR_ERR(spi_get_csgpiod(spi, 0));
goto err_cleanup;
}
/* and set up the "mode" and level */
dev_info(&spi->dev, "setting up native-CS%i to use GPIO\n",
spi->chip_select);
spi_get_chipselect(spi, 0));
return 0;

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@@ -448,7 +448,7 @@ static int bcm2835aux_spi_setup(struct spi_device *spi)
if (spi->mode & SPI_NO_CS)
return 0;
if (spi->cs_gpiod)
if (spi_get_csgpiod(spi, 0))
return 0;
/* for dt-backwards compatibility: only support native on CS0
@@ -465,7 +465,7 @@ static int bcm2835aux_spi_setup(struct spi_device *spi)
dev_warn(&spi->dev,
"Native CS is not supported - please configure cs-gpio in device-tree\n");
if (spi->chip_select == 0)
if (spi_get_chipselect(spi, 0) == 0)
return 0;
dev_warn(&spi->dev, "Native CS is not working for cs > 0\n");

View File

@@ -349,7 +349,7 @@ static int bcm63xx_hsspi_do_prepend_txrx(struct spi_device *spi,
struct spi_transfer *t)
{
struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
unsigned int chip_select = spi->chip_select;
unsigned int chip_select = spi_get_chipselect(spi, 0);
u16 opcode = 0, val;
const u8 *tx = t->tx_buf;
u8 *rx = t->rx_buf;
@@ -441,7 +441,7 @@ static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs,
static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
struct spi_device *spi, int hz)
{
unsigned int profile = spi->chip_select;
unsigned int profile = spi_get_chipselect(spi, 0);
u32 reg;
reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
@@ -468,7 +468,7 @@ static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
{
struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
unsigned int chip_select = spi->chip_select;
unsigned int chip_select = spi_get_chipselect(spi, 0);
u16 opcode = 0, val;
int pending = t->len;
int step_size = HSSPI_BUFFER_LEN;
@@ -478,7 +478,7 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
if (!t->cs_off)
bcm63xx_hsspi_set_cs(bs, spi->chip_select, true);
bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), true);
if (tx && rx)
opcode = HSSPI_OP_READ_WRITE;
@@ -545,14 +545,14 @@ static int bcm63xx_hsspi_setup(struct spi_device *spi)
u32 reg;
reg = __raw_readl(bs->regs +
HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
HSSPI_PROFILE_SIGNAL_CTRL_REG(spi_get_chipselect(spi, 0)));
reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
if (spi->mode & SPI_CPHA)
reg |= SIGNAL_CTRL_LAUNCH_RISING;
else
reg |= SIGNAL_CTRL_LATCH_RISING;
__raw_writel(reg, bs->regs +
HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
HSSPI_PROFILE_SIGNAL_CTRL_REG(spi_get_chipselect(spi, 0)));
mutex_lock(&bs->bus_mutex);
reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
@@ -560,16 +560,16 @@ static int bcm63xx_hsspi_setup(struct spi_device *spi)
/* only change actual polarities if there is no transfer */
if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) {
if (spi->mode & SPI_CS_HIGH)
reg |= BIT(spi->chip_select);
reg |= BIT(spi_get_chipselect(spi, 0));
else
reg &= ~BIT(spi->chip_select);
reg &= ~BIT(spi_get_chipselect(spi, 0));
__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
}
if (spi->mode & SPI_CS_HIGH)
bs->cs_polarity |= BIT(spi->chip_select);
bs->cs_polarity |= BIT(spi_get_chipselect(spi, 0));
else
bs->cs_polarity &= ~BIT(spi->chip_select);
bs->cs_polarity &= ~BIT(spi_get_chipselect(spi, 0));
mutex_unlock(&bs->bus_mutex);
@@ -600,7 +600,7 @@ static int bcm63xx_hsspi_do_dummy_cs_txrx(struct spi_device *spi,
* e. At the end restore the polarities again to their default values.
*/
dummy_cs = !spi->chip_select;
dummy_cs = !spi_get_chipselect(spi, 0);
bcm63xx_hsspi_set_cs(bs, dummy_cs, true);
list_for_each_entry(t, &msg->transfers, transfer_list) {
@@ -633,22 +633,22 @@ static int bcm63xx_hsspi_do_dummy_cs_txrx(struct spi_device *spi,
keep_cs = true;
} else {
if (!t->cs_off)
bcm63xx_hsspi_set_cs(bs, spi->chip_select, false);
bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), false);
spi_transfer_cs_change_delay_exec(msg, t);
if (!list_next_entry(t, transfer_list)->cs_off)
bcm63xx_hsspi_set_cs(bs, spi->chip_select, true);
bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), true);
}
} else if (!list_is_last(&t->transfer_list, &msg->transfers) &&
t->cs_off != list_next_entry(t, transfer_list)->cs_off) {
bcm63xx_hsspi_set_cs(bs, spi->chip_select, t->cs_off);
bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), t->cs_off);
}
}
bcm63xx_hsspi_set_cs(bs, dummy_cs, false);
if (status || !keep_cs)
bcm63xx_hsspi_set_cs(bs, spi->chip_select, false);
bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), false);
return status;
}

View File

@@ -282,7 +282,7 @@ static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
/* Issue the transfer */
cmd = SPI_CMD_START_IMMEDIATE;
cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
cmd |= (spi_get_chipselect(spi, 0) << SPI_CMD_DEVICE_ID_SHIFT);
bcm_spi_writew(bs, cmd, SPI_CMD);
/* Enable the CMD_DONE interrupt */

View File

@@ -193,7 +193,7 @@ static void bcmbca_hsspi_set_cs(struct bcmbca_hsspi *bs, unsigned int cs,
static void bcmbca_hsspi_set_clk(struct bcmbca_hsspi *bs,
struct spi_device *spi, int hz)
{
unsigned int profile = spi->chip_select;
unsigned int profile = spi_get_chipselect(spi, 0);
u32 reg;
reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
@@ -251,7 +251,7 @@ static int bcmbca_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t,
struct spi_message *msg)
{
struct bcmbca_hsspi *bs = spi_master_get_devdata(spi->master);
unsigned int chip_select = spi->chip_select;
unsigned int chip_select = spi_get_chipselect(spi, 0);
u16 opcode = 0, val;
int pending = t->len;
int step_size = HSSPI_BUFFER_LEN;
@@ -312,7 +312,7 @@ static int bcmbca_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t,
PINGPONG_COMMAND_START_NOW;
__raw_writel(reg, bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
if (bcmbca_hsspi_wait_cmd(bs, spi->chip_select))
if (bcmbca_hsspi_wait_cmd(bs, spi_get_chipselect(spi, 0)))
return -ETIMEDOUT;
pending -= curr_step;
@@ -332,33 +332,33 @@ static int bcmbca_hsspi_setup(struct spi_device *spi)
u32 reg;
reg = __raw_readl(bs->regs +
HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
HSSPI_PROFILE_SIGNAL_CTRL_REG(spi_get_chipselect(spi, 0)));
reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
if (spi->mode & SPI_CPHA)
reg |= SIGNAL_CTRL_LAUNCH_RISING;
else
reg |= SIGNAL_CTRL_LATCH_RISING;
__raw_writel(reg, bs->regs +
HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
HSSPI_PROFILE_SIGNAL_CTRL_REG(spi_get_chipselect(spi, 0)));
mutex_lock(&bs->bus_mutex);
reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
if (spi->mode & SPI_CS_HIGH)
reg |= BIT(spi->chip_select);
reg |= BIT(spi_get_chipselect(spi, 0));
else
reg &= ~BIT(spi->chip_select);
reg &= ~BIT(spi_get_chipselect(spi, 0));
__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
if (spi->mode & SPI_CS_HIGH)
bs->cs_polarity |= BIT(spi->chip_select);
bs->cs_polarity |= BIT(spi_get_chipselect(spi, 0));
else
bs->cs_polarity &= ~BIT(spi->chip_select);
bs->cs_polarity &= ~BIT(spi_get_chipselect(spi, 0));
reg = __raw_readl(bs->spim_ctrl);
reg &= ~BIT(spi->chip_select + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT);
reg &= ~BIT(spi_get_chipselect(spi, 0) + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT);
if (spi->mode & SPI_CS_HIGH)
reg |= BIT(spi->chip_select + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT);
reg |= BIT(spi_get_chipselect(spi, 0) + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT);
__raw_writel(reg, bs->spim_ctrl);
mutex_unlock(&bs->bus_mutex);
@@ -388,16 +388,16 @@ static int bcmbca_hsspi_transfer_one(struct spi_master *master,
keep_cs = true;
} else {
if (!t->cs_off)
bcmbca_hsspi_set_cs(bs, spi->chip_select, false);
bcmbca_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), false);
spi_transfer_cs_change_delay_exec(msg, t);
if (!list_next_entry(t, transfer_list)->cs_off)
bcmbca_hsspi_set_cs(bs, spi->chip_select, true);
bcmbca_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), true);
}
} else if (!list_is_last(&t->transfer_list, &msg->transfers) &&
t->cs_off != list_next_entry(t, transfer_list)->cs_off) {
bcmbca_hsspi_set_cs(bs, spi->chip_select, t->cs_off);
bcmbca_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), t->cs_off);
}
msg->actual_length += t->len;
@@ -406,7 +406,7 @@ static int bcmbca_hsspi_transfer_one(struct spi_master *master,
mutex_unlock(&bs->msg_mutex);
if (status || !keep_cs)
bcmbca_hsspi_set_cs(bs, spi->chip_select, false);
bcmbca_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), false);
msg->status = status;
spi_finalize_current_message(master);

View File

@@ -1355,7 +1355,7 @@ static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
struct cqspi_flash_pdata *f_pdata;
f_pdata = &cqspi->f_pdata[mem->spi->chip_select];
f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)];
cqspi_configure(f_pdata, mem->spi->max_speed_hz);
if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
@@ -1561,7 +1561,8 @@ static const char *cqspi_get_name(struct spi_mem *mem)
struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
struct device *dev = &cqspi->pdev->dev;
return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select);
return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev),
spi_get_chipselect(mem->spi, 0));
}
static const struct spi_controller_mem_ops cqspi_mem_ops = {

View File

@@ -409,8 +409,8 @@ static int cdns_xspi_mem_op(struct cdns_xspi_dev *cdns_xspi,
{
enum spi_mem_data_dir dir = op->data.dir;
if (cdns_xspi->cur_cs != mem->spi->chip_select)
cdns_xspi->cur_cs = mem->spi->chip_select;
if (cdns_xspi->cur_cs != spi_get_chipselect(mem->spi, 0))
cdns_xspi->cur_cs = spi_get_chipselect(mem->spi, 0);
return cdns_xspi_send_stig_command(cdns_xspi, op,
(dir != SPI_MEM_NO_DATA));

View File

@@ -185,11 +185,11 @@ static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
/* Select the slave */
ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
if (!(xspi->is_decoded_cs))
ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) <<
ctrl_reg |= ((~(CDNS_SPI_SS0 << spi_get_chipselect(spi, 0))) <<
CDNS_SPI_SS_SHIFT) &
CDNS_SPI_CR_SSCTRL;
else
ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) &
ctrl_reg |= (spi_get_chipselect(spi, 0) << CDNS_SPI_SS_SHIFT) &
CDNS_SPI_CR_SSCTRL;
}

View File

@@ -57,8 +57,8 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
mpi_cfg.s.cslate = cpha ? 1 : 0;
mpi_cfg.s.enable = 1;
if (spi->chip_select < 4)
p->cs_enax |= 1ull << (12 + spi->chip_select);
if (spi_get_chipselect(spi, 0) < 4)
p->cs_enax |= 1ull << (12 + spi_get_chipselect(spi, 0));
mpi_cfg.u64 |= p->cs_enax;
if (mpi_cfg.u64 != p->last_cfg) {
@@ -78,7 +78,7 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
}
mpi_tx.u64 = 0;
mpi_tx.s.csid = spi->chip_select;
mpi_tx.s.csid = spi_get_chipselect(spi, 0);
mpi_tx.s.leavecs = 1;
mpi_tx.s.txnum = tx_buf ? OCTEON_SPI_MAX_BYTES : 0;
mpi_tx.s.totnum = OCTEON_SPI_MAX_BYTES;
@@ -103,7 +103,7 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
}
mpi_tx.u64 = 0;
mpi_tx.s.csid = spi->chip_select;
mpi_tx.s.csid = spi_get_chipselect(spi, 0);
if (last_xfer)
mpi_tx.s.leavecs = xfer->cs_change;
else

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