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Merge tag 'pinctrl-v5.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Browse Source 
Pull pin control updates from Linus Walleij:
 "There is a lot going on!

  Core changes:

   - A semantic change to handle pinmux and pinconf in explicit order
     while up until now we depended on the semantic order in the device
     tree. The device tree is a functional programming language and does
     not imply any order, so the right thing is for the pin control core
     to provide these semantics.

   - Add a new pinmux-select debugfs file which makes it possible to go
     in and select functions for a pin manually (iteratively, at the
     prompt) for debugging purposes.

   - Fixes to gpio regmap handling for a new pin control driver making
     use of regmap-gpio.

   - Use octal permissions on debugfs files.

  New drivers:

   - A massive rewrite of the former custom pin control driver for MIPS
     Broadcom devices to instead use the pin control subsystem. New pin
     control drivers for BCM6345, BCM6328, BCM6358, BCM6362, BCM6368,
     BCM63268 and BCM6318 SoC variants are implemented.

   - Support for PM8350, PM8350B, PM8350C, PMK8350, PMR735A and PMR735B
     in the Qualcomm PMIC GPIO driver. Also the two GPIOs on PM8008 are
     supported.

   - Support for the Rockchip RK3568/RK3566 pin controller.

   - Support for Ingenic JZ4730, JZ4750, JZ4755, JZ4775 and X2000.

   - Support for Mediatek MTK8195.

   - Add a new Xilinx ZynqMP pin control driver.

  Driver improvements and non-urgent fixes:

   - Modularization and improvements of the Rockchip drivers.

   - Some new pins added to the description of new Renesas SoCs.

   - Clarifications of the GPIO base calculation in the Intel driver.

   - Fix the function names for the MPP54 and MPP55 pins in the Armada
     CP110 pin controller.

   - GPIO wakeup interrupt map for Qualcomm SC7280 and SM8350.

   - Support for ACPI probing of the Qualcomm SC8180x.

   - Fix interrupt clear status on rockchip

   - Fix some missing pins on the Ingenic JZ4770, some semantic fixes
     for the behaviour of the Ingenic pin controller. Add DMIC pins for
     JZ4780, X1000, X1500 and X1830.

   - A slew of janitorial like of_node_put() calls"

* tag 'pinctrl-v5.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits)
  pinctrl: Add Xilinx ZynqMP pinctrl driver support
  firmware: xilinx: Add pinctrl support
  pinctrl: rockchip: do coding style for mux route struct
  pinctrl: Add PIN_CONFIG_MODE_PWM to enum pin_config_param
  pinctrl: Introduce MODE group in enum pin_config_param
  pinctrl: Keep enum pin_config_param ordered by name
  dt-bindings: pinctrl: Add binding for ZynqMP pinctrl driver
  pinctrl: core: Fix kernel doc string for pin_get_name()
  pinctrl: mediatek: use spin lock in mtk_rmw
  pinctrl: add drive for I2C related pins on MT8195
  pinctrl: add pinctrl driver on mt8195
  dt-bindings: pinctrl: mt8195: add pinctrl file and binding document
  pinctrl: Ingenic: Add pinctrl driver for X2000.
  pinctrl: Ingenic: Add pinctrl driver for JZ4775.
  pinctrl: Ingenic: Add pinctrl driver for JZ4755.
  pinctrl: Ingenic: Add pinctrl driver for JZ4750.
  pinctrl: Ingenic: Add pinctrl driver for JZ4730.
  dt-bindings: pinctrl: Add bindings for new Ingenic SoCs.
  pinctrl: Ingenic: Reformat the code.
  pinctrl: Ingenic: Add DMIC pins support for Ingenic SoCs.
  ...
This commit is contained in:
Linus Torvalds
2021-04-30 13:04:30 -07:00
parent 592fa9532d 8b242ca700
commit 65ec0a7d24
121 changed files with 13663 additions and 1072 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt
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@@ -142,8 +142,8 @@ mpp50 50 gpio, ge1(rxclk), mss_i2c(sda), spi1(csn0), uart2(txd), uart0(rxd), xg(
mpp51 51 gpio, ge1(rxd0), mss_i2c(sck), spi1(csn1), uart2(rxd), uart0(cts), sdio(pwr10)
mpp52 52 gpio, ge1(rxd1), synce1(clk), synce2(clk), spi1(csn2), uart1(cts), led(clk), pcie(rstoutn), pcie0(clkreq)
mpp53 53 gpio, ge1(rxd2), ptp(clk), spi1(csn3), uart1(rxd), led(stb), sdio(led)
mpp54 54 gpio, ge1(rxd3), synce2(clk), ptp(pclk_out), synce1(clk), led(data), sdio(hw_rst), sdio(wr_protect)
mpp55 55 gpio, ge1(rxctl_rxdv), ptp(pulse), sdio(led), sdio(card_detect)
mpp54 54 gpio, ge1(rxd3), synce2(clk), ptp(pclk_out), synce1(clk), led(data), sdio(hw_rst), sdio_wp(wr_protect)
mpp55 55 gpio, ge1(rxctl_rxdv), ptp(pulse), sdio(led), sdio_cd(card_detect)
mpp56 56 gpio, tdm(drx), au(i2sdo_spdifo), spi0(clk), uart1(rxd), sata1(present_act), sdio(clk)
mpp57 57 gpio, mss_i2c(sda), ptp(pclk_out), tdm(intn), au(i2sbclk), spi0(mosi), uart1(txd), sata0(present_act), sdio(cmd)
mpp58 58 gpio, mss_i2c(sck), ptp(clk), tdm(rstn), au(i2sdi), spi0(miso), uart1(cts), led(clk), sdio(d0)

46
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.txt
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@@ -1,46 +0,0 @@
Bindings for the Broadcom's brcm,bcm6345-gpio memory-mapped GPIO controllers.
These bindings can be used on any BCM63xx SoC. However, BCM6338 and BCM6345
are the only ones which don't need a pinctrl driver.
BCM6338 have 8-bit data and dirout registers, where GPIO state can be read
and/or written, and the direction changed from input to output.
BCM6345 have 16-bit data and dirout registers, where GPIO state can be read
and/or written, and the direction changed from input to output.
Required properties:
- compatible: should be "brcm,bcm6345-gpio"
- reg-names: must contain
"dat" - data register
"dirout" - direction (output) register
- reg: address + size pairs describing the GPIO register sets;
order must correspond with the order of entries in reg-names
- #gpio-cells: must be set to 2. The first cell is the pin number and
the second cell is used to specify the gpio polarity:
0 = active high
1 = active low
- gpio-controller: Marks the device node as a gpio controller.
Optional properties:
- native-endian: use native endian memory.
Examples:
- BCM6338:
gpio: gpio-controller@fffe0407 {
compatible = "brcm,bcm6345-gpio";
reg-names = "dirout", "dat";
reg = <0xfffe0407 1>, <0xfffe040f 1>;
#gpio-cells = <2>;
gpio-controller;
};
- BCM6345:
gpio: gpio-controller@fffe0406 {
compatible = "brcm,bcm6345-gpio";
reg-names = "dirout", "dat";
reg = <0xfffe0406 2>, <0xfffe040a 2>;
native-endian;
#gpio-cells = <2>;
gpio-controller;
};

86
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml Normal file
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@@ -0,0 +1,86 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/brcm,bcm6345-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6345 GPIO controller
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description: |+
Bindings for Broadcom's BCM63xx memory-mapped GPIO controllers.
These bindings can be used on any BCM63xx SoC. However, BCM6338 and BCM6345
are the only ones which don't need a pinctrl driver.
BCM6338 have 8-bit data and dirout registers, where GPIO state can be read
and/or written, and the direction changed from input to output.
BCM6345 have 16-bit data and dirout registers, where GPIO state can be read
and/or written, and the direction changed from input to output.
BCM6318, BCM6328, BCM6358, BCM6362, BCM6368 and BCM63268 have 32-bit data
and dirout registers, where GPIO state can be read and/or written, and the
direction changed from input to output.
properties:
compatible:
enum:
- brcm,bcm6318-gpio
- brcm,bcm6328-gpio
- brcm,bcm6345-gpio
- brcm,bcm6358-gpio
- brcm,bcm6362-gpio
- brcm,bcm6368-gpio
- brcm,bcm63268-gpio
gpio-controller: true
"#gpio-cells":
const: 2
gpio-ranges:
maxItems: 1
native-endian: true
reg:
maxItems: 2
reg-names:
items:
- const: dirout
- const: dat
required:
- compatible
- reg
- reg-names
- gpio-controller
- '#gpio-cells'
additionalProperties: false
examples:
- |
gpio@fffe0406 {
compatible = "brcm,bcm6345-gpio";
reg-names = "dirout", "dat";
reg = <0xfffe0406 2>, <0xfffe040a 2>;
native-endian;
gpio-controller;
#gpio-cells = <2>;
};
- |
gpio@0 {
compatible = "brcm,bcm63268-gpio";
reg-names = "dirout", "dat";
reg = <0x0 0x8>, <0x8 0x8>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 52>;
#gpio-cells = <2>;
};

177
Documentation/devicetree/bindings/mfd/brcm,bcm6318-gpio-sysctl.yaml Normal file
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@@ -0,0 +1,177 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/brcm,bcm6318-gpio-sysctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6318 GPIO System Controller Device Tree Bindings
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description:
Broadcom BCM6318 SoC GPIO system controller which provides a register map
for controlling the GPIO and pins of the SoC.
properties:
"#address-cells": true
"#size-cells": true
compatible:
items:
- const: brcm,bcm6318-gpio-sysctl
- const: syscon
- const: simple-mfd
ranges:
maxItems: 1
reg:
maxItems: 1
patternProperties:
"^gpio@[0-9a-f]+$":
# Child node
type: object
$ref: "../gpio/brcm,bcm6345-gpio.yaml"
description:
GPIO controller for the SoC GPIOs. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
"^pinctrl@[0-9a-f]+$":
# Child node
type: object
$ref: "../pinctrl/brcm,bcm6318-pinctrl.yaml"
description:
Pin controller for the SoC pins. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.yaml.
required:
- "#address-cells"
- compatible
- ranges
- reg
- "#size-cells"
additionalProperties: false
examples:
- |
syscon@10000080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "brcm,bcm6318-gpio-sysctl", "syscon", "simple-mfd";
reg = <0x10000080 0x80>;
ranges = <0 0x10000080 0x80>;
gpio@0 {
compatible = "brcm,bcm6318-gpio";
reg-names = "dirout", "dat";
reg = <0x0 0x8>, <0x8 0x8>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 50>;
#gpio-cells = <2>;
};
pinctrl: pinctrl@10 {
compatible = "brcm,bcm6318-pinctrl";
reg = <0x18 0x10>, <0x54 0x18>;
pinctrl_ephy0_spd_led: ephy0_spd_led-pins {
function = "ephy0_spd_led";
pins = "gpio0";
};
pinctrl_ephy1_spd_led: ephy1_spd_led-pins {
function = "ephy1_spd_led";
pins = "gpio1";
};
pinctrl_ephy2_spd_led: ephy2_spd_led-pins {
function = "ephy2_spd_led";
pins = "gpio2";
};
pinctrl_ephy3_spd_led: ephy3_spd_led-pins {
function = "ephy3_spd_led";
pins = "gpio3";
};
pinctrl_ephy0_act_led: ephy0_act_led-pins {
function = "ephy0_act_led";
pins = "gpio4";
};
pinctrl_ephy1_act_led: ephy1_act_led-pins {
function = "ephy1_act_led";
pins = "gpio5";
};
pinctrl_ephy2_act_led: ephy2_act_led-pins {
function = "ephy2_act_led";
pins = "gpio6";
};
pinctrl_ephy3_act_led: ephy3_act_led-pins {
function = "ephy3_act_led";
pins = "gpio7";
};
pinctrl_serial_led: serial_led-pins {
pinctrl_serial_led_data: serial_led_data-pins {
function = "serial_led_data";
pins = "gpio6";
};
pinctrl_serial_led_clk: serial_led_clk-pins {
function = "serial_led_clk";
pins = "gpio7";
};
};
pinctrl_inet_act_led: inet_act_led-pins {
function = "inet_act_led";
pins = "gpio8";
};
pinctrl_inet_fail_led: inet_fail_led-pins {
function = "inet_fail_led";
pins = "gpio9";
};
pinctrl_dsl_led: dsl_led-pins {
function = "dsl_led";
pins = "gpio10";
};
pinctrl_post_fail_led: post_fail_led-pins {
function = "post_fail_led";
pins = "gpio11";
};
pinctrl_wlan_wps_led: wlan_wps_led-pins {
function = "wlan_wps_led";
pins = "gpio12";
};
pinctrl_usb_pwron: usb_pwron-pins {
function = "usb_pwron";
pins = "gpio13";
};
pinctrl_usb_device_led: usb_device_led-pins {
function = "usb_device_led";
pins = "gpio13";
};
pinctrl_usb_active: usb_active-pins {
function = "usb_active";
pins = "gpio40";
};
};
};

194
Documentation/devicetree/bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml Normal file
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@@ -0,0 +1,194 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/brcm,bcm63268-gpio-sysctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM63268 GPIO System Controller Device Tree Bindings
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description:
Broadcom BCM63268 SoC GPIO system controller which provides a register map
for controlling the GPIO and pins of the SoC.
properties:
"#address-cells": true
"#size-cells": true
compatible:
items:
- const: brcm,bcm63268-gpio-sysctl
- const: syscon
- const: simple-mfd
ranges:
maxItems: 1
reg:
maxItems: 1
patternProperties:
"^gpio@[0-9a-f]+$":
# Child node
type: object
$ref: "../gpio/brcm,bcm6345-gpio.yaml"
description:
GPIO controller for the SoC GPIOs. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
"^pinctrl@[0-9a-f]+$":
# Child node
type: object
$ref: "../pinctrl/brcm,bcm63268-pinctrl.yaml"
description:
Pin controller for the SoC pins. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml.
required:
- "#address-cells"
- compatible
- ranges
- reg
- "#size-cells"
additionalProperties: false
examples:
- |
syscon@100000c0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "brcm,bcm63268-gpio-sysctl", "syscon", "simple-mfd";
reg = <0x100000c0 0x80>;
ranges = <0 0x100000c0 0x80>;
gpio@0 {
compatible = "brcm,bcm63268-gpio";
reg-names = "dirout", "dat";
reg = <0x0 0x8>, <0x8 0x8>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 52>;
#gpio-cells = <2>;
};
pinctrl: pinctrl@10 {
compatible = "brcm,bcm63268-pinctrl";
reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>;
pinctrl_serial_led: serial_led-pins {
pinctrl_serial_led_clk: serial_led_clk-pins {
function = "serial_led_clk";
pins = "gpio0";
};
pinctrl_serial_led_data: serial_led_data-pins {
function = "serial_led_data";
pins = "gpio1";
};
};
pinctrl_hsspi_cs4: hsspi_cs4-pins {
function = "hsspi_cs4";
pins = "gpio16";
};
pinctrl_hsspi_cs5: hsspi_cs5-pins {
function = "hsspi_cs5";
pins = "gpio17";
};
pinctrl_hsspi_cs6: hsspi_cs6-pins {
function = "hsspi_cs6";
pins = "gpio8";
};
pinctrl_hsspi_cs7: hsspi_cs7-pins {
function = "hsspi_cs7";
pins = "gpio9";
};
pinctrl_adsl_spi: adsl_spi-pins {
pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
function = "adsl_spi_miso";
pins = "gpio18";
};
pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
function = "adsl_spi_mosi";
pins = "gpio19";
};
};
pinctrl_vreq_clk: vreq_clk-pins {
function = "vreq_clk";
pins = "gpio22";
};
pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins {
function = "pcie_clkreq_b";
pins = "gpio23";
};
pinctrl_robosw_led_clk: robosw_led_clk-pins {
function = "robosw_led_clk";
pins = "gpio30";
};
pinctrl_robosw_led_data: robosw_led_data-pins {
function = "robosw_led_data";
pins = "gpio31";
};
pinctrl_nand: nand-pins {
function = "nand";
group = "nand_grp";
};
pinctrl_gpio35_alt: gpio35_alt-pins {
function = "gpio35_alt";
pin = "gpio35";
};
pinctrl_dectpd: dectpd-pins {
function = "dectpd";
group = "dectpd_grp";
};
pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins {
function = "vdsl_phy_override_0";
group = "vdsl_phy_override_0_grp";
};
pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins {
function = "vdsl_phy_override_1";
group = "vdsl_phy_override_1_grp";
};
pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins {
function = "vdsl_phy_override_2";
group = "vdsl_phy_override_2_grp";
};
pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins {
function = "vdsl_phy_override_3";
group = "vdsl_phy_override_3_grp";
};
pinctrl_dsl_gpio8: dsl_gpio8-pins {
function = "dsl_gpio8";
group = "dsl_gpio8";
};
pinctrl_dsl_gpio9: dsl_gpio9-pins {
function = "dsl_gpio9";
group = "dsl_gpio9";
};
};
};

162
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@@ -0,0 +1,162 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/brcm,bcm6328-gpio-sysctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6328 GPIO System Controller Device Tree Bindings
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description:
Broadcom BCM6328 SoC GPIO system controller which provides a register map
for controlling the GPIO and pins of the SoC.
properties:
"#address-cells": true
"#size-cells": true
compatible:
items:
- const: brcm,bcm6328-gpio-sysctl
- const: syscon
- const: simple-mfd
ranges:
maxItems: 1
reg:
maxItems: 1
patternProperties:
"^gpio@[0-9a-f]+$":
# Child node
type: object
$ref: "../gpio/brcm,bcm6345-gpio.yaml"
description:
GPIO controller for the SoC GPIOs. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
"^pinctrl@[0-9a-f]+$":
# Child node
type: object
$ref: "../pinctrl/brcm,bcm6328-pinctrl.yaml"
description:
Pin controller for the SoC pins. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml.
required:
- "#address-cells"
- compatible
- ranges
- reg
- "#size-cells"
additionalProperties: false
examples:
- |
syscon@10000080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "brcm,bcm6328-gpio-sysctl", "syscon", "simple-mfd";
reg = <0x10000080 0x80>;
ranges = <0 0x10000080 0x80>;
gpio@0 {
compatible = "brcm,bcm6328-gpio";
reg-names = "dirout", "dat";
reg = <0x0 0x8>, <0x8 0x8>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 32>;
#gpio-cells = <2>;
};
pinctrl: pinctrl@18 {
compatible = "brcm,bcm6328-pinctrl";
reg = <0x18 0x10>;
pinctrl_serial_led: serial_led-pins {
pinctrl_serial_led_data: serial_led_data-pins {
function = "serial_led_data";
pins = "gpio6";
};
pinctrl_serial_led_clk: serial_led_clk-pins {
function = "serial_led_clk";
pins = "gpio7";
};
};
pinctrl_inet_act_led: inet_act_led-pins {
function = "inet_act_led";
pins = "gpio11";
};
pinctrl_pcie_clkreq: pcie_clkreq-pins {
function = "pcie_clkreq";
pins = "gpio16";
};
pinctrl_ephy0_spd_led: ephy0_spd_led-pins {
function = "led";
pins = "gpio17";
};
pinctrl_ephy1_spd_led: ephy1_spd_led-pins {
function = "led";
pins = "gpio18";
};
pinctrl_ephy2_spd_led: ephy2_spd_led-pins {
function = "led";
pins = "gpio19";
};
pinctrl_ephy3_spd_led: ephy3_spd_led-pins {
function = "led";
pins = "gpio20";
};
pinctrl_ephy0_act_led: ephy0_act_led-pins {
function = "ephy0_act_led";
pins = "gpio25";
};
pinctrl_ephy1_act_led: ephy1_act_led-pins {
function = "ephy1_act_led";
pins = "gpio26";
};
pinctrl_ephy2_act_led: ephy2_act_led-pins {
function = "ephy2_act_led";
pins = "gpio27";
};
pinctrl_ephy3_act_led: ephy3_act_led-pins {
function = "ephy3_act_led";
pins = "gpio28";
};
pinctrl_hsspi_cs1: hsspi_cs1-pins {
function = "hsspi_cs1";
pins = "hsspi_cs1";
};
pinctrl_usb_port1_device: usb_port1_device-pins {
function = "usb_device_port";
pins = "usb_port1";
};
pinctrl_usb_port1_host: usb_port1_host-pins {
function = "usb_host_port";
pins = "usb_port1";
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/brcm,bcm6358-gpio-sysctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6358 GPIO System Controller Device Tree Bindings
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description:
Broadcom BCM6358 SoC GPIO system controller which provides a register map
for controlling the GPIO and pins of the SoC.
properties:
"#address-cells": true
"#size-cells": true
compatible:
items:
- const: brcm,bcm6358-gpio-sysctl
- const: syscon
- const: simple-mfd
ranges:
maxItems: 1
reg:
maxItems: 1
patternProperties:
"^gpio@[0-9a-f]+$":
# Child node
type: object
$ref: "../gpio/brcm,bcm6345-gpio.yaml"
description:
GPIO controller for the SoC GPIOs. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
"^pinctrl@[0-9a-f]+$":
# Child node
type: object
$ref: "../pinctrl/brcm,bcm6358-pinctrl.yaml"
description:
Pin controller for the SoC pins. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.yaml.
required:
- "#address-cells"
- compatible
- ranges
- reg
- "#size-cells"
additionalProperties: false
examples:
- |
syscon@fffe0080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "brcm,bcm6358-gpio-sysctl", "syscon", "simple-mfd";
reg = <0xfffe0080 0x80>;
ranges = <0 0xfffe0080 0x80>;
gpio@0 {
compatible = "brcm,bcm6358-gpio";
reg-names = "dirout", "dat";
reg = <0x0 0x8>, <0x8 0x8>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 40>;
#gpio-cells = <2>;
};
pinctrl: pinctrl@18 {
compatible = "brcm,bcm6358-pinctrl";
reg = <0x18 0x4>;
pinctrl_ebi_cs: ebi_cs-pins {
function = "ebi_cs";
groups = "ebi_cs_grp";
};
pinctrl_uart1: uart1-pins {
function = "uart1";
groups = "uart1_grp";
};
pinctrl_serial_led: serial_led-pins {
function = "serial_led";
groups = "serial_led_grp";
};
pinctrl_legacy_led: legacy_led-pins {
function = "legacy_led";
groups = "legacy_led_grp";
};
pinctrl_led: led-pins {
function = "led";
groups = "led_grp";
};
pinctrl_spi_cs_23: spi_cs-pins {
function = "spi_cs";
groups = "spi_cs_grp";
};
pinctrl_utopia: utopia-pins {
function = "utopia";
groups = "utopia_grp";
};
pinctrl_pwm_syn_clk: pwm_syn_clk-pins {
function = "pwm_syn_clk";
groups = "pwm_syn_clk_grp";
};
pinctrl_sys_irq: sys_irq-pins {
function = "sys_irq";
groups = "sys_irq_grp";
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/brcm,bcm6362-gpio-sysctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6362 GPIO System Controller Device Tree Bindings
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description:
Broadcom BCM6362 SoC GPIO system controller which provides a register map
for controlling the GPIO and pins of the SoC.
properties:
"#address-cells": true
"#size-cells": true
compatible:
items:
- const: brcm,bcm6362-gpio-sysctl
- const: syscon
- const: simple-mfd
ranges:
maxItems: 1
reg:
maxItems: 1
patternProperties:
"^gpio@[0-9a-f]+$":
# Child node
type: object
$ref: "../gpio/brcm,bcm6345-gpio.yaml"
description:
GPIO controller for the SoC GPIOs. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
"^pinctrl@[0-9a-f]+$":
# Child node
type: object
$ref: "../pinctrl/brcm,bcm6362-pinctrl.yaml"
description:
Pin controller for the SoC pins. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.yaml.
required:
- "#address-cells"
- compatible
- ranges
- reg
- "#size-cells"
additionalProperties: false
examples:
- |
syscon@10000080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "brcm,bcm6362-gpio-sysctl", "syscon", "simple-mfd";
reg = <0x10000080 0x80>;
ranges = <0 0x10000080 0x80>;
gpio@0 {
compatible = "brcm,bcm6362-gpio";
reg-names = "dirout", "dat";
reg = <0x0 0x8>, <0x8 0x8>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 48>;
#gpio-cells = <2>;
};
pinctrl: pinctrl@18 {
compatible = "brcm,bcm6362-pinctrl";
reg = <0x18 0x10>, <0x38 0x4>;
pinctrl_usb_device_led: usb_device_led-pins {
function = "usb_device_led";
pins = "gpio0";
};
pinctrl_sys_irq: sys_irq-pins {
function = "sys_irq";
pins = "gpio1";
};
pinctrl_serial_led: serial_led-pins {
pinctrl_serial_led_clk: serial_led_clk-pins {
function = "serial_led_clk";
pins = "gpio2";
};
pinctrl_serial_led_data: serial_led_data-pins {
function = "serial_led_data";
pins = "gpio3";
};
};
pinctrl_robosw_led_data: robosw_led_data-pins {
function = "robosw_led_data";
pins = "gpio4";
};
pinctrl_robosw_led_clk: robosw_led_clk-pins {
function = "robosw_led_clk";
pins = "gpio5";
};
pinctrl_robosw_led0: robosw_led0-pins {
function = "robosw_led0";
pins = "gpio6";
};
pinctrl_robosw_led1: robosw_led1-pins {
function = "robosw_led1";
pins = "gpio7";
};
pinctrl_inet_led: inet_led-pins {
function = "inet_led";
pins = "gpio8";
};
pinctrl_spi_cs2: spi_cs2-pins {
function = "spi_cs2";
pins = "gpio9";
};
pinctrl_spi_cs3: spi_cs3-pins {
function = "spi_cs3";
pins = "gpio10";
};
pinctrl_ntr_pulse: ntr_pulse-pins {
function = "ntr_pulse";
pins = "gpio11";
};
pinctrl_uart1_scts: uart1_scts-pins {
function = "uart1_scts";
pins = "gpio12";
};
pinctrl_uart1_srts: uart1_srts-pins {
function = "uart1_srts";
pins = "gpio13";
};
pinctrl_uart1: uart1-pins {
pinctrl_uart1_sdin: uart1_sdin-pins {
function = "uart1_sdin";
pins = "gpio14";
};
pinctrl_uart1_sdout: uart1_sdout-pins {
function = "uart1_sdout";
pins = "gpio15";
};
};
pinctrl_adsl_spi: adsl_spi-pins {
pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
function = "adsl_spi_miso";
pins = "gpio16";
};
pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
function = "adsl_spi_mosi";
pins = "gpio17";
};
pinctrl_adsl_spi_clk: adsl_spi_clk-pins {
function = "adsl_spi_clk";
pins = "gpio18";
};
pinctrl_adsl_spi_cs: adsl_spi_cs-pins {
function = "adsl_spi_cs";
pins = "gpio19";
};
};
pinctrl_ephy0_led: ephy0_led-pins {
function = "ephy0_led";
pins = "gpio20";
};
pinctrl_ephy1_led: ephy1_led-pins {
function = "ephy1_led";
pins = "gpio21";
};
pinctrl_ephy2_led: ephy2_led-pins {
function = "ephy2_led";
pins = "gpio22";
};
pinctrl_ephy3_led: ephy3_led-pins {
function = "ephy3_led";
pins = "gpio23";
};
pinctrl_ext_irq0: ext_irq0-pins {
function = "ext_irq0";
pins = "gpio24";
};
pinctrl_ext_irq1: ext_irq1-pins {
function = "ext_irq1";
pins = "gpio25";
};
pinctrl_ext_irq2: ext_irq2-pins {
function = "ext_irq2";
pins = "gpio26";
};
pinctrl_ext_irq3: ext_irq3-pins {
function = "ext_irq3";
pins = "gpio27";
};
pinctrl_nand: nand-pins {
function = "nand";
group = "nand_grp";
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/brcm,bcm6368-gpio-sysctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6368 GPIO System Controller Device Tree Bindings
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description:
Broadcom BCM6368 SoC GPIO system controller which provides a register map
for controlling the GPIO and pins of the SoC.
properties:
"#address-cells": true
"#size-cells": true
compatible:
items:
- const: brcm,bcm6368-gpio-sysctl
- const: syscon
- const: simple-mfd
ranges:
maxItems: 1
reg:
maxItems: 1
patternProperties:
"^gpio@[0-9a-f]+$":
# Child node
type: object
$ref: "../gpio/brcm,bcm6345-gpio.yaml"
description:
GPIO controller for the SoC GPIOs. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
"^pinctrl@[0-9a-f]+$":
# Child node
type: object
$ref: "../pinctrl/brcm,bcm6368-pinctrl.yaml"
description:
Pin controller for the SoC pins. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.yaml.
required:
- "#address-cells"
- compatible
- ranges
- reg
- "#size-cells"
additionalProperties: false
examples:
- |
syscon@10000080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "brcm,bcm6368-gpio-sysctl", "syscon", "simple-mfd";
reg = <0x10000080 0x80>;
ranges = <0 0x10000080 0x80>;
gpio@0 {
compatible = "brcm,bcm6368-gpio";
reg-names = "dirout", "dat";
reg = <0x0 0x8>, <0x8 0x8>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 38>;
#gpio-cells = <2>;
};
pinctrl: pinctrl@18 {
compatible = "brcm,bcm6368-pinctrl";
reg = <0x18 0x4>, <0x38 0x4>;
pinctrl_analog_afe_0: analog_afe_0-pins {
function = "analog_afe_0";
pins = "gpio0";
};
pinctrl_analog_afe_1: analog_afe_1-pins {
function = "analog_afe_1";
pins = "gpio1";
};
pinctrl_sys_irq: sys_irq-pins {
function = "sys_irq";
pins = "gpio2";
};
pinctrl_serial_led: serial_led-pins {
pinctrl_serial_led_data: serial_led_data-pins {
function = "serial_led_data";
pins = "gpio3";
};
pinctrl_serial_led_clk: serial_led_clk-pins {
function = "serial_led_clk";
pins = "gpio4";
};
};
pinctrl_inet_led: inet_led-pins {
function = "inet_led";
pins = "gpio5";
};
pinctrl_ephy0_led: ephy0_led-pins {
function = "ephy0_led";
pins = "gpio6";
};
pinctrl_ephy1_led: ephy1_led-pins {
function = "ephy1_led";
pins = "gpio7";
};
pinctrl_ephy2_led: ephy2_led-pins {
function = "ephy2_led";
pins = "gpio8";
};
pinctrl_ephy3_led: ephy3_led-pins {
function = "ephy3_led";
pins = "gpio9";
};
pinctrl_robosw_led_data: robosw_led_data-pins {
function = "robosw_led_data";
pins = "gpio10";
};
pinctrl_robosw_led_clk: robosw_led_clk-pins {
function = "robosw_led_clk";
pins = "gpio11";
};
pinctrl_robosw_led0: robosw_led0-pins {
function = "robosw_led0";
pins = "gpio12";
};
pinctrl_robosw_led1: robosw_led1-pins {
function = "robosw_led1";
pins = "gpio13";
};
pinctrl_usb_device_led: usb_device_led-pins {
function = "usb_device_led";
pins = "gpio14";
};
pinctrl_pci: pci-pins {
pinctrl_pci_req1: pci_req1-pins {
function = "pci_req1";
pins = "gpio16";
};
pinctrl_pci_gnt1: pci_gnt1-pins {
function = "pci_gnt1";
pins = "gpio17";
};
pinctrl_pci_intb: pci_intb-pins {
function = "pci_intb";
pins = "gpio18";
};
pinctrl_pci_req0: pci_req0-pins {
function = "pci_req0";
pins = "gpio19";
};
pinctrl_pci_gnt0: pci_gnt0-pins {
function = "pci_gnt0";
pins = "gpio20";
};
};
pinctrl_pcmcia: pcmcia-pins {
pinctrl_pcmcia_cd1: pcmcia_cd1-pins {
function = "pcmcia_cd1";
pins = "gpio22";
};
pinctrl_pcmcia_cd2: pcmcia_cd2-pins {
function = "pcmcia_cd2";
pins = "gpio23";
};
pinctrl_pcmcia_vs1: pcmcia_vs1-pins {
function = "pcmcia_vs1";
pins = "gpio24";
};
pinctrl_pcmcia_vs2: pcmcia_vs2-pins {
function = "pcmcia_vs2";
pins = "gpio25";
};
};
pinctrl_ebi_cs2: ebi_cs2-pins {
function = "ebi_cs2";
pins = "gpio26";
};
pinctrl_ebi_cs3: ebi_cs3-pins {
function = "ebi_cs3";
pins = "gpio27";
};
pinctrl_spi_cs2: spi_cs2-pins {
function = "spi_cs2";
pins = "gpio28";
};
pinctrl_spi_cs3: spi_cs3-pins {
function = "spi_cs3";
pins = "gpio29";
};
pinctrl_spi_cs4: spi_cs4-pins {
function = "spi_cs4";
pins = "gpio30";
};
pinctrl_spi_cs5: spi_cs5-pins {
function = "spi_cs5";
pins = "gpio31";
};
pinctrl_uart1: uart1-pins {
function = "uart1";
group = "uart1_grp";
};
};
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6318-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6318 pin controller
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description:
Bindings for Broadcom's BCM6318 memory-mapped pin controller.
properties:
compatible:
const: brcm,bcm6318-pinctrl
reg:
maxItems: 2
patternProperties:
'-pins$':
type: object
$ref: pinmux-node.yaml#
properties:
function:
enum: [ ephy0_spd_led, ephy1_spd_led, ephy2_spd_led, ephy3_spd_led,
ephy0_act_led, ephy1_act_led, ephy2_act_led, ephy3_act_led,
serial_led_data, serial_led_clk, inet_act_led, inet_fail_led,
dsl_led, post_fail_led, wlan_wps_led, usb_pwron,
usb_device_led, usb_active ]
pins:
enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7,
gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio40 ]
required:
- compatible
- reg
additionalProperties: false
examples:
- |
pinctrl@18 {
compatible = "brcm,bcm6318-pinctrl";
reg = <0x18 0x10>, <0x54 0x18>;
pinctrl_ephy0_spd_led: ephy0_spd_led-pins {
function = "ephy0_spd_led";
pins = "gpio0";
};
pinctrl_ephy1_spd_led: ephy1_spd_led-pins {
function = "ephy1_spd_led";
pins = "gpio1";
};
pinctrl_ephy2_spd_led: ephy2_spd_led-pins {
function = "ephy2_spd_led";
pins = "gpio2";
};
pinctrl_ephy3_spd_led: ephy3_spd_led-pins {
function = "ephy3_spd_led";
pins = "gpio3";
};
pinctrl_ephy0_act_led: ephy0_act_led-pins {
function = "ephy0_act_led";
pins = "gpio4";
};
pinctrl_ephy1_act_led: ephy1_act_led-pins {
function = "ephy1_act_led";
pins = "gpio5";
};
pinctrl_ephy2_act_led: ephy2_act_led-pins {
function = "ephy2_act_led";
pins = "gpio6";
};
pinctrl_ephy3_act_led: ephy3_act_led-pins {
function = "ephy3_act_led";
pins = "gpio7";
};
pinctrl_serial_led: serial_led-pins {
pinctrl_serial_led_data: serial_led_data-pins {
function = "serial_led_data";
pins = "gpio6";
};
pinctrl_serial_led_clk: serial_led_clk-pins {
function = "serial_led_clk";
pins = "gpio7";
};
};
pinctrl_inet_act_led: inet_act_led-pins {
function = "inet_act_led";
pins = "gpio8";
};
pinctrl_inet_fail_led: inet_fail_led-pins {
function = "inet_fail_led";
pins = "gpio9";
};
pinctrl_dsl_led: dsl_led-pins {
function = "dsl_led";
pins = "gpio10";
};
pinctrl_post_fail_led: post_fail_led-pins {
function = "post_fail_led";
pins = "gpio11";
};
pinctrl_wlan_wps_led: wlan_wps_led-pins {
function = "wlan_wps_led";
pins = "gpio12";
};
pinctrl_usb_pwron: usb_pwron-pins {
function = "usb_pwron";
pins = "gpio13";
};
pinctrl_usb_device_led: usb_device_led-pins {
function = "usb_device_led";
pins = "gpio13";
};
pinctrl_usb_active: usb_active-pins {
function = "usb_active";
pins = "gpio40";
};
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm63268-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM63268 pin controller
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description:
Bindings for Broadcom's BCM63268 memory-mapped pin controller.
properties:
compatible:
const: brcm,bcm63268-pinctrl
reg:
maxItems: 3
patternProperties:
'-pins$':
type: object
$ref: pinmux-node.yaml#
properties:
function:
enum: [ serial_led_clk, serial_led_data, hsspi_cs4, hsspi_cs5,
hsspi_cs6, hsspi_cs7, adsl_spi_miso, adsl_spi_mosi,
vreq_clk, pcie_clkreq_b, robosw_led_clk, robosw_led_data,
nand, gpio35_alt, dectpd, vdsl_phy_override_0,
vdsl_phy_override_1, vdsl_phy_override_2,
vdsl_phy_override_3, dsl_gpio8, dsl_gpio9 ]
pins:
enum: [ gpio0, gpio1, gpio16, gpio17, gpio8, gpio9, gpio18, gpio19,
gpio22, gpio23, gpio30, gpio31, nand_grp, gpio35
dectpd_grp, vdsl_phy_override_0_grp,
vdsl_phy_override_1_grp, vdsl_phy_override_2_grp,
vdsl_phy_override_3_grp, dsl_gpio8, dsl_gpio9 ]
required:
- compatible
- reg
additionalProperties: false
examples:
- |
pinctrl@10 {
compatible = "brcm,bcm63268-pinctrl";
reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>;
pinctrl_serial_led: serial_led-pins {
pinctrl_serial_led_clk: serial_led_clk-pins {
function = "serial_led_clk";
pins = "gpio0";
};
pinctrl_serial_led_data: serial_led_data-pins {
function = "serial_led_data";
pins = "gpio1";
};
};
pinctrl_hsspi_cs4: hsspi_cs4-pins {
function = "hsspi_cs4";
pins = "gpio16";
};
pinctrl_hsspi_cs5: hsspi_cs5-pins {
function = "hsspi_cs5";
pins = "gpio17";
};
pinctrl_hsspi_cs6: hsspi_cs6-pins {
function = "hsspi_cs6";
pins = "gpio8";
};
pinctrl_hsspi_cs7: hsspi_cs7-pins {
function = "hsspi_cs7";
pins = "gpio9";
};
pinctrl_adsl_spi: adsl_spi-pins {
pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
function = "adsl_spi_miso";
pins = "gpio18";
};
pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
function = "adsl_spi_mosi";
pins = "gpio19";
};
};
pinctrl_vreq_clk: vreq_clk-pins {
function = "vreq_clk";
pins = "gpio22";
};
pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins {
function = "pcie_clkreq_b";
pins = "gpio23";
};
pinctrl_robosw_led_clk: robosw_led_clk-pins {
function = "robosw_led_clk";
pins = "gpio30";
};
pinctrl_robosw_led_data: robosw_led_data-pins {
function = "robosw_led_data";
pins = "gpio31";
};
pinctrl_nand: nand-pins {
function = "nand";
group = "nand_grp";
};
pinctrl_gpio35_alt: gpio35_alt-pins {
function = "gpio35_alt";
pin = "gpio35";
};
pinctrl_dectpd: dectpd-pins {
function = "dectpd";
group = "dectpd_grp";
};
pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins {
function = "vdsl_phy_override_0";
group = "vdsl_phy_override_0_grp";
};
pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins {
function = "vdsl_phy_override_1";
group = "vdsl_phy_override_1_grp";
};
pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins {
function = "vdsl_phy_override_2";
group = "vdsl_phy_override_2_grp";
};
pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins {
function = "vdsl_phy_override_3";
group = "vdsl_phy_override_3_grp";
};
pinctrl_dsl_gpio8: dsl_gpio8-pins {
function = "dsl_gpio8";
group = "dsl_gpio8";
};
pinctrl_dsl_gpio9: dsl_gpio9-pins {
function = "dsl_gpio9";
group = "dsl_gpio9";
};
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6328-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6328 pin controller
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description:
Bindings for Broadcom's BCM6328 memory-mapped pin controller.
properties:
compatible:
const: brcm,bcm6328-pinctrl
reg:
maxItems: 1
patternProperties:
'-pins$':
type: object
$ref: pinmux-node.yaml#
properties:
function:
enum: [ serial_led_data, serial_led_clk, inet_act_led, pcie_clkreq,
led, ephy0_act_led, ephy1_act_led, ephy2_act_led,
ephy3_act_led, hsspi_cs1, usb_device_port, usb_host_port ]
pins:
enum: [ gpio6, gpio7, gpio11, gpio16, gpio17, gpio18, gpio19,
gpio20, gpio25, gpio26, gpio27, gpio28, hsspi_cs1,
usb_port1 ]
required:
- compatible
- reg
additionalProperties: false
examples:
- |
pinctrl@18 {
compatible = "brcm,bcm6328-pinctrl";
reg = <0x18 0x10>;
pinctrl_serial_led: serial_led-pins {
pinctrl_serial_led_data: serial_led_data-pins {
function = "serial_led_data";
pins = "gpio6";
};
pinctrl_serial_led_clk: serial_led_clk-pins {
function = "serial_led_clk";
pins = "gpio7";
};
};
pinctrl_inet_act_led: inet_act_led-pins {
function = "inet_act_led";
pins = "gpio11";
};
pinctrl_pcie_clkreq: pcie_clkreq-pins {
function = "pcie_clkreq";
pins = "gpio16";
};
pinctrl_ephy0_spd_led: ephy0_spd_led-pins {
function = "led";
pins = "gpio17";
};
pinctrl_ephy1_spd_led: ephy1_spd_led-pins {
function = "led";
pins = "gpio18";
};
pinctrl_ephy2_spd_led: ephy2_spd_led-pins {
function = "led";
pins = "gpio19";
};
pinctrl_ephy3_spd_led: ephy3_spd_led-pins {
function = "led";
pins = "gpio20";
};
pinctrl_ephy0_act_led: ephy0_act_led-pins {
function = "ephy0_act_led";
pins = "gpio25";
};
pinctrl_ephy1_act_led: ephy1_act_led-pins {
function = "ephy1_act_led";
pins = "gpio26";
};
pinctrl_ephy2_act_led: ephy2_act_led-pins {
function = "ephy2_act_led";
pins = "gpio27";
};
pinctrl_ephy3_act_led: ephy3_act_led-pins {
function = "ephy3_act_led";
pins = "gpio28";
};
pinctrl_hsspi_cs1: hsspi_cs1-pins {
function = "hsspi_cs1";
pins = "hsspi_cs1";
};
pinctrl_usb_port1_device: usb_port1_device-pins {
function = "usb_device_port";
pins = "usb_port1";
};
pinctrl_usb_port1_host: usb_port1_host-pins {
function = "usb_host_port";
pins = "usb_port1";
};
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6358-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6358 pin controller
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description:
Bindings for Broadcom's BCM6358 memory-mapped pin controller.
properties:
compatible:
const: brcm,bcm6358-pinctrl
reg:
maxItems: 1
patternProperties:
'-pins$':
type: object
$ref: pinmux-node.yaml#
properties:
function:
enum: [ ebi_cs, uart1, serial_led, legacy_led, led, spi_cs, utopia,
pwm_syn_clk, sys_irq ]
pins:
enum: [ ebi_cs_grp, uart1_grp, serial_led_grp, legacy_led_grp,
led_grp, spi_cs_grp, utopia_grp, pwm_syn_clk, sys_irq_grp ]
required:
- compatible
- reg
additionalProperties: false
examples:
- |
pinctrl@18 {
compatible = "brcm,bcm6358-pinctrl";
reg = <0x18 0x4>;
pinctrl_ebi_cs: ebi_cs-pins {
function = "ebi_cs";
groups = "ebi_cs_grp";
};
pinctrl_uart1: uart1-pins {
function = "uart1";
groups = "uart1_grp";
};
pinctrl_serial_led: serial_led-pins {
function = "serial_led";
groups = "serial_led_grp";
};
pinctrl_legacy_led: legacy_led-pins {
function = "legacy_led";
groups = "legacy_led_grp";
};
pinctrl_led: led-pins {
function = "led";
groups = "led_grp";
};
pinctrl_spi_cs_23: spi_cs-pins {
function = "spi_cs";
groups = "spi_cs_grp";
};
pinctrl_utopia: utopia-pins {
function = "utopia";
groups = "utopia_grp";
};
pinctrl_pwm_syn_clk: pwm_syn_clk-pins {
function = "pwm_syn_clk";
groups = "pwm_syn_clk_grp";
};
pinctrl_sys_irq: sys_irq-pins {
function = "sys_irq";
groups = "sys_irq_grp";
};
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6362-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6362 pin controller
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description:
Bindings for Broadcom's BCM6362 memory-mapped pin controller.
properties:
compatible:
const: brcm,bcm6362-pinctrl
reg:
maxItems: 2
patternProperties:
'-pins$':
type: object
$ref: pinmux-node.yaml#
properties:
function:
enum: [ usb_device_led, sys_irq, serial_led_clk, serial_led_data,
robosw_led_data, robosw_led_clk, robosw_led0, robosw_led1,
inet_led, spi_cs2, spi_cs3, ntr_pulse, uart1_scts,
uart1_srts, uart1_sdin, uart1_sdout, adsl_spi_miso,
adsl_spi_mosi, adsl_spi_clk, adsl_spi_cs, ephy0_led,
ephy1_led, ephy2_led, ephy3_led, ext_irq0, ext_irq1,
ext_irq2, ext_irq3, nand ]
pins:
enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7,
gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14,
gpio15, gpio16, gpio17, gpio18, gpio19, gpio20, gpio21,
gpio22, gpio23, gpio24, gpio25, gpio26, gpio27, nand_grp ]
required:
- compatible
- reg
additionalProperties: false
examples:
- |
pinctrl@18 {
compatible = "brcm,bcm6362-pinctrl";
reg = <0x18 0x10>, <0x38 0x4>;
pinctrl_usb_device_led: usb_device_led-pins {
function = "usb_device_led";
pins = "gpio0";
};
pinctrl_sys_irq: sys_irq-pins {
function = "sys_irq";
pins = "gpio1";
};
pinctrl_serial_led: serial_led-pins {
pinctrl_serial_led_clk: serial_led_clk-pins {
function = "serial_led_clk";
pins = "gpio2";
};
pinctrl_serial_led_data: serial_led_data-pins {
function = "serial_led_data";
pins = "gpio3";
};
};
pinctrl_robosw_led_data: robosw_led_data-pins {
function = "robosw_led_data";
pins = "gpio4";
};
pinctrl_robosw_led_clk: robosw_led_clk-pins {
function = "robosw_led_clk";
pins = "gpio5";
};
pinctrl_robosw_led0: robosw_led0-pins {
function = "robosw_led0";
pins = "gpio6";
};
pinctrl_robosw_led1: robosw_led1-pins {
function = "robosw_led1";
pins = "gpio7";
};
pinctrl_inet_led: inet_led-pins {
function = "inet_led";
pins = "gpio8";
};
pinctrl_spi_cs2: spi_cs2-pins {
function = "spi_cs2";
pins = "gpio9";
};
pinctrl_spi_cs3: spi_cs3-pins {
function = "spi_cs3";
pins = "gpio10";
};
pinctrl_ntr_pulse: ntr_pulse-pins {
function = "ntr_pulse";
pins = "gpio11";
};
pinctrl_uart1_scts: uart1_scts-pins {
function = "uart1_scts";
pins = "gpio12";
};
pinctrl_uart1_srts: uart1_srts-pins {
function = "uart1_srts";
pins = "gpio13";
};
pinctrl_uart1: uart1-pins {
pinctrl_uart1_sdin: uart1_sdin-pins {
function = "uart1_sdin";
pins = "gpio14";
};
pinctrl_uart1_sdout: uart1_sdout-pins {
function = "uart1_sdout";
pins = "gpio15";
};
};
pinctrl_adsl_spi: adsl_spi-pins {
pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
function = "adsl_spi_miso";
pins = "gpio16";
};
pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
function = "adsl_spi_mosi";
pins = "gpio17";
};
pinctrl_adsl_spi_clk: adsl_spi_clk-pins {
function = "adsl_spi_clk";
pins = "gpio18";
};
pinctrl_adsl_spi_cs: adsl_spi_cs-pins {
function = "adsl_spi_cs";
pins = "gpio19";
};
};
pinctrl_ephy0_led: ephy0_led-pins {
function = "ephy0_led";
pins = "gpio20";
};
pinctrl_ephy1_led: ephy1_led-pins {
function = "ephy1_led";
pins = "gpio21";
};
pinctrl_ephy2_led: ephy2_led-pins {
function = "ephy2_led";
pins = "gpio22";
};
pinctrl_ephy3_led: ephy3_led-pins {
function = "ephy3_led";
pins = "gpio23";
};
pinctrl_ext_irq0: ext_irq0-pins {
function = "ext_irq0";
pins = "gpio24";
};
pinctrl_ext_irq1: ext_irq1-pins {
function = "ext_irq1";
pins = "gpio25";
};
pinctrl_ext_irq2: ext_irq2-pins {
function = "ext_irq2";
pins = "gpio26";
};
pinctrl_ext_irq3: ext_irq3-pins {
function = "ext_irq3";
pins = "gpio27";
};
pinctrl_nand: nand-pins {
function = "nand";
group = "nand_grp";
};
};

217
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@@ -0,0 +1,217 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6368-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6368 pin controller
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description:
Bindings for Broadcom's BCM6368 memory-mapped pin controller.
properties:
compatible:
const: brcm,bcm6368-pinctrl
reg:
maxItems: 2
patternProperties:
'-pins$':
type: object
$ref: pinmux-node.yaml#
properties:
function:
enum: [ analog_afe_0, analog_afe_1, sys_irq, serial_led_data,
serial_led_clk, inet_led, ephy0_led, ephy1_led, ephy2_led,
ephy3_led, robosw_led_data, robosw_led_clk, robosw_led0,
robosw_led1, usb_device_led, pci_req1, pci_gnt1, pci_intb,
pci_req0, pci_gnt0, pcmcia_cd1, pcmcia_cd2, pcmcia_vs1,
pcmcia_vs2, ebi_cs2, ebi_cs3, spi_cs2, spi_cs3, spi_cs4,
spi_cs5, uart1 ]
pins:
enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7,
gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14,
gpio16, gpio17, gpio18, gpio19, gpio20, gpio22, gpio23,
gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30,
gpio31, uart1_grp ]
required:
- compatible
- reg
additionalProperties: false
examples:
- |
pinctrl@18 {
compatible = "brcm,bcm6368-pinctrl";
reg = <0x18 0x4>, <0x38 0x4>;
pinctrl_analog_afe_0: analog_afe_0-pins {
function = "analog_afe_0";
pins = "gpio0";
};
pinctrl_analog_afe_1: analog_afe_1-pins {
function = "analog_afe_1";
pins = "gpio1";
};
pinctrl_sys_irq: sys_irq-pins {
function = "sys_irq";
pins = "gpio2";
};
pinctrl_serial_led: serial_led-pins {
pinctrl_serial_led_data: serial_led_data-pins {
function = "serial_led_data";
pins = "gpio3";
};
pinctrl_serial_led_clk: serial_led_clk-pins {
function = "serial_led_clk";
pins = "gpio4";
};
};
pinctrl_inet_led: inet_led-pins {
function = "inet_led";
pins = "gpio5";
};
pinctrl_ephy0_led: ephy0_led-pins {
function = "ephy0_led";
pins = "gpio6";
};
pinctrl_ephy1_led: ephy1_led-pins {
function = "ephy1_led";
pins = "gpio7";
};
pinctrl_ephy2_led: ephy2_led-pins {
function = "ephy2_led";
pins = "gpio8";
};
pinctrl_ephy3_led: ephy3_led-pins {
function = "ephy3_led";
pins = "gpio9";
};
pinctrl_robosw_led_data: robosw_led_data-pins {
function = "robosw_led_data";
pins = "gpio10";
};
pinctrl_robosw_led_clk: robosw_led_clk-pins {
function = "robosw_led_clk";
pins = "gpio11";
};
pinctrl_robosw_led0: robosw_led0-pins {
function = "robosw_led0";
pins = "gpio12";
};
pinctrl_robosw_led1: robosw_led1-pins {
function = "robosw_led1";
pins = "gpio13";
};
pinctrl_usb_device_led: usb_device_led-pins {
function = "usb_device_led";
pins = "gpio14";
};
pinctrl_pci: pci-pins {
pinctrl_pci_req1: pci_req1-pins {
function = "pci_req1";
pins = "gpio16";
};
pinctrl_pci_gnt1: pci_gnt1-pins {
function = "pci_gnt1";
pins = "gpio17";
};
pinctrl_pci_intb: pci_intb-pins {
function = "pci_intb";
pins = "gpio18";
};
pinctrl_pci_req0: pci_req0-pins {
function = "pci_req0";
pins = "gpio19";
};
pinctrl_pci_gnt0: pci_gnt0-pins {
function = "pci_gnt0";
pins = "gpio20";
};
};
pinctrl_pcmcia: pcmcia-pins {
pinctrl_pcmcia_cd1: pcmcia_cd1-pins {
function = "pcmcia_cd1";
pins = "gpio22";
};
pinctrl_pcmcia_cd2: pcmcia_cd2-pins {
function = "pcmcia_cd2";
pins = "gpio23";
};
pinctrl_pcmcia_vs1: pcmcia_vs1-pins {
function = "pcmcia_vs1";
pins = "gpio24";
};
pinctrl_pcmcia_vs2: pcmcia_vs2-pins {
function = "pcmcia_vs2";
pins = "gpio25";
};
};
pinctrl_ebi_cs2: ebi_cs2-pins {
function = "ebi_cs2";
pins = "gpio26";
};
pinctrl_ebi_cs3: ebi_cs3-pins {
function = "ebi_cs3";
pins = "gpio27";
};
pinctrl_spi_cs2: spi_cs2-pins {
function = "spi_cs2";
pins = "gpio28";
};
pinctrl_spi_cs3: spi_cs3-pins {
function = "spi_cs3";
pins = "gpio29";
};
pinctrl_spi_cs4: spi_cs4-pins {
function = "spi_cs4";
pins = "gpio30";
};
pinctrl_spi_cs5: spi_cs5-pins {
function = "spi_cs5";
pins = "gpio31";
};
pinctrl_uart1: uart1-pins {
function = "uart1";
group = "uart1_grp";
};
};

23
Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
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@@ -17,10 +17,12 @@ description: >
naming scheme "PxN" where x is a character identifying the GPIO port with
which the pin is associated and N is an integer from 0 to 31 identifying the
pin within that GPIO port. For example PA0 is the first pin in GPIO port A,
and PB31 is the last pin in GPIO port B. The JZ4740, the X1000 and the X1830
contains 4 GPIO ports, PA to PD, for a total of 128 pins. The JZ4760, the
JZ4770 and the JZ4780 contains 6 GPIO ports, PA to PF, for a total of 192
pins.
and PB31 is the last pin in GPIO port B. The JZ4730, the JZ4740, the JZ4725B,
the X1000 and the X1830 contains 4 GPIO ports, PA to PD, for a total of 128
pins. The X2000 contains 5 GPIO ports, PA to PE, for a total of 160 pins.
The JZ4750, the JZ4755 the JZ4760, the JZ4770 and the JZ4780 contains 6 GPIO
ports, PA to PF, for a total of 192 pins. The JZ4775 contains 7 GPIO ports,
PA to PG, for a total of 224 pins.
maintainers:
- Paul Cercueil <paul@crapouillou.net>
@@ -32,20 +34,28 @@ properties:
compatible:
oneOf:
- enum:
- ingenic,jz4730-pinctrl
- ingenic,jz4740-pinctrl
- ingenic,jz4725b-pinctrl
- ingenic,jz4750-pinctrl
- ingenic,jz4755-pinctrl
- ingenic,jz4760-pinctrl
- ingenic,jz4770-pinctrl
- ingenic,jz4775-pinctrl
- ingenic,jz4780-pinctrl
- ingenic,x1000-pinctrl
- ingenic,x1500-pinctrl
- ingenic,x1830-pinctrl
- ingenic,x2000-pinctrl
- items:
- const: ingenic,jz4760b-pinctrl
- const: ingenic,jz4760-pinctrl
- items:
- const: ingenic,x1000e-pinctrl
- const: ingenic,x1000-pinctrl
- items:
- const: ingenic,x2000e-pinctrl
- const: ingenic,x2000-pinctrl
reg:
maxItems: 1
@@ -62,14 +72,19 @@ patternProperties:
properties:
compatible:
enum:
- ingenic,jz4730-gpio
- ingenic,jz4740-gpio
- ingenic,jz4725b-gpio
- ingenic,jz4750-gpio
- ingenic,jz4755-gpio
- ingenic,jz4760-gpio
- ingenic,jz4770-gpio
- ingenic,jz4775-gpio
- ingenic,jz4780-gpio
- ingenic,x1000-gpio
- ingenic,x1500-gpio
- ingenic,x1830-gpio
- ingenic,x2000-gpio
reg:
items:

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8195.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek MT8195 Pin Controller
maintainers:
- Sean Wang <sean.wang@mediatek.com>
description: |
The Mediatek's Pin controller is used to control SoC pins.
properties:
compatible:
const: mediatek,mt8195-pinctrl
gpio-controller: true
'#gpio-cells':
description: |
Number of cells in GPIO specifier. Since the generic GPIO binding is used,
the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
const: 2
gpio-ranges:
description: gpio valid number range.
maxItems: 1
reg:
description: |
Physical address base for gpio base registers. There are 8 GPIO
physical address base in mt8195.
maxItems: 8
reg-names:
description: |
Gpio base register names.
maxItems: 8
interrupt-controller: true
'#interrupt-cells':
const: 2
interrupts:
description: The interrupt outputs to sysirq.
maxItems: 1
#PIN CONFIGURATION NODES
patternProperties:
'-pins$':
type: object
description: |
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and
input schmitt.
An example of using macro:
pincontroller {
/* GPIO0 set as multifunction GPIO0 */
gpio_pin {
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
};
/* GPIO8 set as multifunction SDA0 */
i2c0_pin {
pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
};
};
$ref: "pinmux-node.yaml"
properties:
pinmux:
description: |
Integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are defined
as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
drive-strength:
description: |
It can support some arguments which is from 0 to 7. It can only support
2/4/6/8/10/12/14/16mA in mt8195.
enum: [0, 1, 2, 3, 4, 5, 6, 7]
bias-pull-down: true
bias-pull-up: true
bias-disable: true
output-high: true
output-low: true
input-enable: true
input-disable: true
input-schmitt-enable: true
input-schmitt-disable: true
required:
- pinmux
additionalProperties: false
required:
- compatible
- reg
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
pio: pinctrl@10005000 {
compatible = "mediatek,mt8195-pinctrl";
reg = <0x10005000 0x1000>,
<0x11d10000 0x1000>,
<0x11d30000 0x1000>,
<0x11d40000 0x1000>,
<0x11e20000 0x1000>,
<0x11eb0000 0x1000>,
<0x11f40000 0x1000>,
<0x1000b000 0x1000>;
reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
"iocfg_br", "iocfg_lm", "iocfg_rb",
"iocfg_tl", "eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 144>;
interrupt-controller;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
#interrupt-cells = <2>;
pio-pins {
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
output-low;
};
};

14
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
View File

@@ -27,8 +27,15 @@ PMIC's from Qualcomm.
"qcom,pm660l-gpio"
"qcom,pm8150-gpio"
"qcom,pm8150b-gpio"
"qcom,pm8350-gpio"
"qcom,pm8350b-gpio"
"qcom,pm8350c-gpio"
"qcom,pmk8350-gpio"
"qcom,pmr735a-gpio"
"qcom,pmr735b-gpio"
"qcom,pm6150-gpio"
"qcom,pm6150l-gpio"
"qcom,pm8008-gpio"
"qcom,pmx55-gpio"
And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio"
@@ -109,8 +116,15 @@ to specify in a pin configuration subnode:
and gpio8)
gpio1-gpio12 for pm8150b (holes on gpio3, gpio4, gpio7)
gpio1-gpio12 for pm8150l (hole on gpio7)
gpio1-gpio10 for pm8350
gpio1-gpio8 for pm8350b
gpio1-gpio9 for pm8350c
gpio1-gpio4 for pmk8350
gpio1-gpio4 for pmr735a
gpio1-gpio4 for pmr735b
gpio1-gpio10 for pm6150
gpio1-gpio12 for pm6150l
gpio1-gpio2 for pm8008
gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10
and gpio11)

1
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
View File

@@ -33,6 +33,7 @@ Required properties for iomux controller:
"rockchip,rk3328-pinctrl": for Rockchip RK3328
"rockchip,rk3368-pinctrl": for Rockchip RK3368
"rockchip,rk3399-pinctrl": for Rockchip RK3399
"rockchip,rk3568-pinctrl": for Rockchip RK3568
- rockchip,grf: phandle referencing a syscon providing the
"general register files"

336
Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml Normal file
View File

@@ -0,0 +1,336 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP Pinctrl
maintainers:
- Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
- Rajan Vaja <rajan.vaja@xilinx.com>
description: |
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
ZynqMP's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, slew rate, etc.
Each configuration node can consist of multiple nodes describing the pinmux and
pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
properties:
compatible:
const: xlnx,zynqmp-pinctrl
patternProperties:
'^(.*-)?(default|gpio)$':
type: object
patternProperties:
'^mux':
type: object
description:
Pinctrl node's client devices use subnodes for pin muxes,
which in turn use below standard properties.
$ref: pinmux-node.yaml#
properties:
groups:
description:
List of groups to select (either this or "pins" must be
specified), available groups for this subnode.
items:
enum: [ethernet0_0_grp, ethernet1_0_grp, ethernet2_0_grp,
ethernet3_0_grp, gemtsu0_0_grp, gemtsu0_1_grp,
gemtsu0_2_grp, mdio0_0_grp, mdio1_0_grp,
mdio1_1_grp, mdio2_0_grp, mdio3_0_grp,
qspi0_0_grp, qspi_ss_0_grp, qspi_fbclk_0_grp,
spi0_0_grp, spi0_ss_0_grp, spi0_ss_1_grp,
spi0_ss_2_grp, spi0_1_grp, spi0_ss_3_grp,
spi0_ss_4_grp, spi0_ss_5_grp, spi0_2_grp,
spi0_ss_6_grp, spi0_ss_7_grp, spi0_ss_8_grp,
spi0_3_grp, spi0_ss_9_grp, spi0_ss_10_grp,
spi0_ss_11_grp, spi0_4_grp, spi0_ss_12_grp,
spi0_ss_13_grp, spi0_ss_14_grp, spi0_5_grp,
spi0_ss_15_grp, spi0_ss_16_grp, spi0_ss_17_grp,
spi1_0_grp, spi1_ss_0_grp, spi1_ss_1_grp,
spi1_ss_2_grp, spi1_1_grp, spi1_ss_3_grp,
spi1_ss_4_grp, spi1_ss_5_grp, spi1_2_grp,
spi1_ss_6_grp, spi1_ss_7_grp, spi1_ss_8_grp,
spi1_3_grp, spi1_ss_9_grp, spi1_ss_10_grp,
spi1_ss_11_grp, spi1_4_grp, spi1_ss_12_grp,
spi1_ss_13_grp, spi1_ss_14_grp, spi1_5_grp,
spi1_ss_15_grp, spi1_ss_16_grp, spi1_ss_17_grp,
sdio0_0_grp, sdio0_1_grp, sdio0_2_grp,
sdio0_3_grp, sdio0_4_grp, sdio0_5_grp,
sdio0_6_grp, sdio0_7_grp, sdio0_8_grp,
sdio0_9_grp, sdio0_10_grp, sdio0_11_grp,
sdio0_12_grp, sdio0_13_grp, sdio0_14_grp,
sdio0_15_grp, sdio0_16_grp, sdio0_17_grp,
sdio0_18_grp, sdio0_19_grp, sdio0_20_grp,
sdio0_21_grp, sdio0_22_grp, sdio0_23_grp,
sdio0_24_grp, sdio0_25_grp, sdio0_26_grp,
sdio0_27_grp, sdio0_28_grp, sdio0_29_grp,
sdio0_30_grp, sdio0_31_grp, sdio0_32_grp,
sdio0_pc_0_grp, sdio0_cd_0_grp, sdio0_wp_0_grp,
sdio0_pc_1_grp, sdio0_cd_1_grp, sdio0_wp_1_grp,
sdio0_pc_2_grp, sdio0_cd_2_grp, sdio0_wp_2_grp,
sdio1_0_grp, sdio1_1_grp, sdio1_2_grp,
sdio1_3_grp, sdio1_4_grp, sdio1_5_grp,
sdio1_6_grp, sdio1_7_grp, sdio1_8_grp,
sdio1_9_grp, sdio1_10_grp, sdio1_11_grp,
sdio1_12_grp, sdio1_13_grp, sdio1_14_grp,
sdio1_15_grp, sdio1_pc_0_grp, sdio1_cd_0_grp,
sdio1_wp_0_grp, sdio1_pc_1_grp, sdio1_cd_1_grp,
sdio1_wp_1_grp, nand0_0_grp, nand0_ce_0_grp,
nand0_rb_0_grp, nand0_dqs_0_grp, nand0_ce_1_grp,
nand0_rb_1_grp, nand0_dqs_1_grp, can0_0_grp,
can0_1_grp, can0_2_grp, can0_3_grp,
can0_4_grp, can0_5_grp, can0_6_grp,
can0_7_grp, can0_8_grp, can0_9_grp,
can0_10_grp, can0_11_grp, can0_12_grp,
can0_13_grp, can0_14_grp, can0_15_grp,
can0_16_grp, can0_17_grp, can0_18_grp,
can1_0_grp, can1_1_grp, can1_2_grp,
can1_3_grp, can1_4_grp, can1_5_grp,
can1_6_grp, can1_7_grp, can1_8_grp,
can1_9_grp, can1_10_grp, can1_11_grp,
can1_12_grp, can1_13_grp, can1_14_grp,
can1_15_grp, can1_16_grp, can1_17_grp,
can1_18_grp, can1_19_grp, uart0_0_grp,
uart0_1_grp, uart0_2_grp, uart0_3_grp,
uart0_4_grp, uart0_5_grp, uart0_6_grp,
uart0_7_grp, uart0_8_grp, uart0_9_grp,
uart0_10_grp, uart0_11_grp, uart0_12_grp,
uart0_13_grp, uart0_14_grp, uart0_15_grp,
uart0_16_grp, uart0_17_grp, uart0_18_grp,
uart1_0_grp, uart1_1_grp, uart1_2_grp,
uart1_3_grp, uart1_4_grp, uart1_5_grp,
uart1_6_grp, uart1_7_grp, uart1_8_grp,
uart1_9_grp, uart1_10_grp, uart1_11_grp,
uart1_12_grp, uart1_13_grp, uart1_14_grp,
uart1_15_grp, uart1_16_grp, uart1_17_grp,
uart1_18_grp, i2c0_0_grp, i2c0_1_grp,
i2c0_2_grp, i2c0_3_grp, i2c0_4_grp,
i2c0_5_grp, i2c0_6_grp, i2c0_7_grp,
i2c0_8_grp, i2c0_9_grp, i2c0_10_grp,
i2c0_11_grp, i2c0_12_grp, i2c0_13_grp,
i2c0_14_grp, i2c0_15_grp, i2c0_16_grp,
i2c0_17_grp, i2c0_18_grp, i2c1_0_grp,
i2c1_1_grp, i2c1_2_grp, i2c1_3_grp,
i2c1_4_grp, i2c1_5_grp, i2c1_6_grp,
i2c1_7_grp, i2c1_8_grp, i2c1_9_grp,
i2c1_10_grp, i2c1_11_grp, i2c1_12_grp,
i2c1_13_grp, i2c1_14_grp, i2c1_15_grp,
i2c1_16_grp, i2c1_17_grp, i2c1_18_grp,
i2c1_19_grp, ttc0_clk_0_grp, ttc0_wav_0_grp,
ttc0_clk_1_grp, ttc0_wav_1_grp, ttc0_clk_2_grp,
ttc0_wav_2_grp, ttc0_clk_3_grp, ttc0_wav_3_grp,
ttc0_clk_4_grp, ttc0_wav_4_grp, ttc0_clk_5_grp,
ttc0_wav_5_grp, ttc0_clk_6_grp, ttc0_wav_6_grp,
ttc0_clk_7_grp, ttc0_wav_7_grp, ttc0_clk_8_grp,
ttc0_wav_8_grp, ttc1_clk_0_grp, ttc1_wav_0_grp,
ttc1_clk_1_grp, ttc1_wav_1_grp, ttc1_clk_2_grp,
ttc1_wav_2_grp, ttc1_clk_3_grp, ttc1_wav_3_grp,
ttc1_clk_4_grp, ttc1_wav_4_grp, ttc1_clk_5_grp,
ttc1_wav_5_grp, ttc1_clk_6_grp, ttc1_wav_6_grp,
ttc1_clk_7_grp, ttc1_wav_7_grp, ttc1_clk_8_grp,
ttc1_wav_8_grp, ttc2_clk_0_grp, ttc2_wav_0_grp,
ttc2_clk_1_grp, ttc2_wav_1_grp, ttc2_clk_2_grp,
ttc2_wav_2_grp, ttc2_clk_3_grp, ttc2_wav_3_grp,
ttc2_clk_4_grp, ttc2_wav_4_grp, ttc2_clk_5_grp,
ttc2_wav_5_grp, ttc2_clk_6_grp, ttc2_wav_6_grp,
ttc2_clk_7_grp, ttc2_wav_7_grp, ttc2_clk_8_grp,
ttc2_wav_8_grp, ttc3_clk_0_grp, ttc3_wav_0_grp,
ttc3_clk_1_grp, ttc3_wav_1_grp, ttc3_clk_2_grp,
ttc3_wav_2_grp, ttc3_clk_3_grp, ttc3_wav_3_grp,
ttc3_clk_4_grp, ttc3_wav_4_grp, ttc3_clk_5_grp,
ttc3_wav_5_grp, ttc3_clk_6_grp, ttc3_wav_6_grp,
ttc3_clk_7_grp, ttc3_wav_7_grp, ttc3_clk_8_grp,
ttc3_wav_8_grp, swdt0_clk_0_grp, swdt0_rst_0_grp,
swdt0_clk_1_grp, swdt0_rst_1_grp, swdt0_clk_2_grp,
swdt0_rst_2_grp, swdt0_clk_3_grp, swdt0_rst_3_grp,
swdt0_clk_4_grp, swdt0_rst_4_grp, swdt0_clk_5_grp,
swdt0_rst_5_grp, swdt0_clk_6_grp, swdt0_rst_6_grp,
swdt0_clk_7_grp, swdt0_rst_7_grp, swdt0_clk_8_grp,
swdt0_rst_8_grp, swdt0_clk_9_grp, swdt0_rst_9_grp,
swdt0_clk_10_grp, swdt0_rst_10_grp, swdt0_clk_11_grp,
swdt0_rst_11_grp, swdt0_clk_12_grp, swdt0_rst_12_grp,
swdt1_clk_0_grp, swdt1_rst_0_grp, swdt1_clk_1_grp,
swdt1_rst_1_grp, swdt1_clk_2_grp, swdt1_rst_2_grp,
swdt1_clk_3_grp, swdt1_rst_3_grp, swdt1_clk_4_grp,
swdt1_rst_4_grp, swdt1_clk_5_grp, swdt1_rst_5_grp,
swdt1_clk_6_grp, swdt1_rst_6_grp, swdt1_clk_7_grp,
swdt1_rst_7_grp, swdt1_clk_8_grp, swdt1_rst_8_grp,
swdt1_clk_9_grp, swdt1_rst_9_grp, swdt1_clk_10_grp,
swdt1_rst_10_grp, swdt1_clk_11_grp, swdt1_rst_11_grp,
swdt1_clk_12_grp, swdt1_rst_12_grp, gpio0_0_grp,
gpio0_1_grp, gpio0_2_grp, gpio0_3_grp,
gpio0_4_grp, gpio0_5_grp, gpio0_6_grp,
gpio0_7_grp, gpio0_8_grp, gpio0_9_grp,
gpio0_10_grp, gpio0_11_grp, gpio0_12_grp,
gpio0_13_grp, gpio0_14_grp, gpio0_15_grp,
gpio0_16_grp, gpio0_17_grp, gpio0_18_grp,
gpio0_19_grp, gpio0_20_grp, gpio0_21_grp,
gpio0_22_grp, gpio0_23_grp, gpio0_24_grp,
gpio0_25_grp, gpio0_26_grp, gpio0_27_grp,
gpio0_28_grp, gpio0_29_grp, gpio0_30_grp,
gpio0_31_grp, gpio0_32_grp, gpio0_33_grp,
gpio0_34_grp, gpio0_35_grp, gpio0_36_grp,
gpio0_37_grp, gpio0_38_grp, gpio0_39_grp,
gpio0_40_grp, gpio0_41_grp, gpio0_42_grp,
gpio0_43_grp, gpio0_44_grp, gpio0_45_grp,
gpio0_46_grp, gpio0_47_grp, gpio0_48_grp,
gpio0_49_grp, gpio0_50_grp, gpio0_51_grp,
gpio0_52_grp, gpio0_53_grp, gpio0_54_grp,
gpio0_55_grp, gpio0_56_grp, gpio0_57_grp,
gpio0_58_grp, gpio0_59_grp, gpio0_60_grp,
gpio0_61_grp, gpio0_62_grp, gpio0_63_grp,
gpio0_64_grp, gpio0_65_grp, gpio0_66_grp,
gpio0_67_grp, gpio0_68_grp, gpio0_69_grp,
gpio0_70_grp, gpio0_71_grp, gpio0_72_grp,
gpio0_73_grp, gpio0_74_grp, gpio0_75_grp,
gpio0_76_grp, gpio0_77_grp, usb0_0_grp,
usb1_0_grp, pmu0_0_grp, pmu0_1_grp,
pmu0_2_grp, pmu0_3_grp, pmu0_4_grp,
pmu0_5_grp, pmu0_6_grp, pmu0_7_grp,
pmu0_8_grp, pmu0_9_grp, pmu0_10_grp,
pmu0_11_grp, pcie0_0_grp, pcie0_1_grp,
pcie0_2_grp, pcie0_3_grp, pcie0_4_grp,
pcie0_5_grp, pcie0_6_grp, pcie0_7_grp,
csu0_0_grp, csu0_1_grp, csu0_2_grp,
csu0_3_grp, csu0_4_grp, csu0_5_grp,
csu0_6_grp, csu0_7_grp, csu0_8_grp,
csu0_9_grp, csu0_10_grp, csu0_11_grp,
dpaux0_0_grp, dpaux0_1_grp, dpaux0_2_grp,
dpaux0_3_grp, pjtag0_0_grp, pjtag0_1_grp,
pjtag0_2_grp, pjtag0_3_grp, pjtag0_4_grp,
pjtag0_5_grp, trace0_0_grp, trace0_clk_0_grp,
trace0_1_grp, trace0_clk_1_grp, trace0_2_grp,
trace0_clk_2_grp, testscan0_0_grp]
maxItems: 78
function:
description:
Specify the alternative function to be configured for the
given pin groups.
enum: [ethernet0, ethernet1, ethernet2, ethernet3, gemtsu0, usb0, usb1, mdio0,
mdio1, mdio2, mdio3, qspi0, qspi_fbclk, qspi_ss, spi0, spi1, spi0_ss,
spi1_ss, sdio0, sdio0_pc, sdio0_wp, sdio0_cd, sdio1, sdio1_pc, sdio1_wp,
sdio1_cd, nand0, nand0_ce, nand0_rb, nand0_dqs, can0, can1, uart0, uart1,
i2c0, i2c1, ttc0_clk, ttc0_wav, ttc1_clk, ttc1_wav, ttc2_clk, ttc2_wav,
ttc3_clk, ttc3_wav, swdt0_clk, swdt0_rst, swdt1_clk, swdt1_rst, gpio0, pmu0,
pcie0, csu0, dpaux0, pjtag0, trace0, trace0_clk, testscan0]
required:
- groups
- function
additionalProperties: false
'^conf':
type: object
description:
Pinctrl node's client devices use subnodes for pin configurations,
which in turn use the standard properties below.
$ref: pincfg-node.yaml#
properties:
groups:
description:
List of pin groups as mentioned above.
pins:
description:
List of pin names to select in this subnode.
items:
pattern: '^MIO([0-9]|[1-6][0-9]|7[0-7])$'
maxItems: 78
bias-pull-up: true
bias-pull-down: true
bias-disable: true
input-schmitt-enable: true
input-schmitt-disable: true
bias-high-impedance: true
low-power-enable: true
low-power-disable: true
slew-rate:
enum: [0, 1]
drive-strength:
description:
Selects the drive strength for MIO pins, in mA.
enum: [2, 4, 8, 12]
power-source:
enum: [0, 1]
oneOf:
- required: [ groups ]
- required: [ pins ]
additionalProperties: false
additionalProperties: false
required:
- compatible
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
zynqmp_firmware: zynqmp-firmware {
pinctrl0: pinctrl {
compatible = "xlnx,zynqmp-pinctrl";
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart0_4_grp", "uart0_5_grp";
function = "uart0";
};
conf {
groups = "uart0_4_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO18";
bias-pull-up;
};
conf-tx {
pins = "MIO19";
bias-disable;
input-schmitt-disable;
};
};
};
};
uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};
...

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