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Merge tag 'media/v6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
Pull media updates from Mauro Carvalho Chehab: - New driver for Mediatek MDP V3 - New driver for NXP i.MX DW100 dewarper - Zoran driver got promoted from staging - Hantro and related drivers got promoted from staging - Several VB1 drivers got moved to staging/deprecated (cpia2, fsl-viu, meye, saa7146, av7110, stkwebcam, tm6000, vpfe_capture, davinci, zr364xx) - Usual set of driver fixes, improvements and cleanups * tag 'media/v6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (107 commits) media: destage Hantro VPU driver media: platform: mtk-mdp3: add MediaTek MDP3 driver media: dt-binding: mediatek: add bindings for MediaTek CCORR and WDMA media: dt-binding: mediatek: add bindings for MediaTek MDP3 components media: xilinx: vipp: Fix refcount leak in xvip_graph_dma_init media: xilinx: video: Add 1X12 greyscale format media: xilinx: csi2rxss: Add 1X12 greyscale format media: staging: media: imx: imx7-media-csi: Increase video mem limit media: uvcvideo: Limit power line control for Sonix Technology media: uvcvideo: Use entity get_cur in uvc_ctrl_set media: uvcvideo: Fix typo 'the the' in comment media: uvcvideo: Use indexed loops in uvc_ctrl_init_ctrl() media: uvcvideo: Fix memory leak in uvc_gpio_parse media: renesas: vsp1: Add support for RZ/G2L VSPD media: renesas: vsp1: Add VSP1_HAS_NON_ZERO_LBA feature bit media: renesas: vsp1: Add support for VSP software version media: renesas: vsp1: Add support to deassert/assert reset line media: dt-bindings: media: renesas,vsp1: Document RZ/G2L VSPD bindings media: meson: vdec: add missing clk_disable_unprepare on error in vdec_hevc_start() media: amphion: fix a bug that vpu core may not resume after suspend ...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,95 @@
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||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
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||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Read Direct Memory Access
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||||
|
||||
maintainers:
|
||||
- Matthias Brugger <matthias.bgg@gmail.com>
|
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- Moudy Ho <moudy.ho@mediatek.com>
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||||
|
||||
description: |
|
||||
MediaTek Read Direct Memory Access(RDMA) component used to do read DMA.
|
||||
It contains one line buffer to store the sufficient pixel data, and
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must be siblings to the central MMSYS_CONFIG node.
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For a description of the MMSYS_CONFIG binding, see
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Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
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for details.
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||||
|
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properties:
|
||||
compatible:
|
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items:
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- const: mediatek,mt8183-mdp3-rdma
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|
||||
reg:
|
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maxItems: 1
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||||
|
||||
mediatek,gce-client-reg:
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||||
$ref: '/schemas/types.yaml#/definitions/phandle-array'
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||||
items:
|
||||
items:
|
||||
- description: phandle of GCE
|
||||
- description: GCE subsys id
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||||
- description: register offset
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||||
- description: register size
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||||
description: The register of client driver can be configured by gce with
|
||||
4 arguments defined in this property. Each GCE subsys id is mapping to
|
||||
a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
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||||
|
||||
mediatek,gce-events:
|
||||
description:
|
||||
The event id which is mapping to the specific hardware event signal
|
||||
to gce. The event id is defined in the gce header
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||||
include/dt-bindings/gce/<chip>-gce.h of each chips.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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||||
|
||||
power-domains:
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maxItems: 1
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||||
|
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clocks:
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||||
items:
|
||||
- description: RDMA clock
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- description: RSZ clock
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|
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iommus:
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maxItems: 1
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||||
|
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mboxes:
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||||
items:
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||||
- description: used for 1st data pipe from RDMA
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- description: used for 2nd data pipe from RDMA
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|
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required:
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- compatible
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||||
- reg
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||||
- mediatek,gce-client-reg
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||||
- mediatek,gce-events
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- power-domains
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||||
- clocks
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- iommus
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- mboxes
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|
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additionalProperties: false
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||||
|
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examples:
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- |
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#include <dt-bindings/clock/mt8183-clk.h>
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#include <dt-bindings/gce/mt8183-gce.h>
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#include <dt-bindings/power/mt8183-power.h>
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#include <dt-bindings/memory/mt8183-larb-port.h>
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mdp3_rdma0: mdp3-rdma0@14001000 {
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compatible = "mediatek,mt8183-mdp3-rdma";
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reg = <0x14001000 0x1000>;
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mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
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mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
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<CMDQ_EVENT_MDP_RDMA0_EOF>;
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power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
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clocks = <&mmsys CLK_MM_MDP_RDMA0>,
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<&mmsys CLK_MM_MDP_RSZ1>;
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iommus = <&iommu>;
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mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
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<&gce 21 CMDQ_THR_PRIO_LOWEST>;
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};
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@@ -0,0 +1,77 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
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%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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|
||||
title: MediaTek Resizer
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|
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maintainers:
|
||||
- Matthias Brugger <matthias.bgg@gmail.com>
|
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- Moudy Ho <moudy.ho@mediatek.com>
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||||
|
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description: |
|
||||
One of Media Data Path 3 (MDP3) components used to do frame resizing.
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||||
|
||||
properties:
|
||||
compatible:
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||||
items:
|
||||
- enum:
|
||||
- mediatek,mt8183-mdp3-rsz
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
items:
|
||||
- description: phandle of GCE
|
||||
- description: GCE subsys id
|
||||
- description: register offset
|
||||
- description: register size
|
||||
description: The register of client driver can be configured by gce with
|
||||
4 arguments defined in this property. Each GCE subsys id is mapping to
|
||||
a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
|
||||
|
||||
mediatek,gce-events:
|
||||
description:
|
||||
The event id which is mapping to the specific hardware event signal
|
||||
to gce. The event id is defined in the gce header
|
||||
include/dt-bindings/gce/<chip>-gce.h of each chips.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- mediatek,gce-client-reg
|
||||
- mediatek,gce-events
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/mt8183-clk.h>
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||||
#include <dt-bindings/gce/mt8183-gce.h>
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||||
|
||||
mdp3_rsz0: mdp3-rsz0@14003000 {
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compatible = "mediatek,mt8183-mdp3-rsz";
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reg = <0x14003000 0x1000>;
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||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
|
||||
mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>,
|
||||
<CMDQ_EVENT_MDP_RSZ0_EOF>;
|
||||
clocks = <&mmsys CLK_MM_MDP_RSZ0>;
|
||||
};
|
||||
|
||||
mdp3_rsz1: mdp3-rsz1@14004000 {
|
||||
compatible = "mediatek,mt8183-mdp3-rsz";
|
||||
reg = <0x14004000 0x1000>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
|
||||
mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>,
|
||||
<CMDQ_EVENT_MDP_RSZ1_EOF>;
|
||||
clocks = <&mmsys CLK_MM_MDP_RSZ1>;
|
||||
};
|
||||
@@ -0,0 +1,80 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Write DMA with Rotation
|
||||
|
||||
maintainers:
|
||||
- Matthias Brugger <matthias.bgg@gmail.com>
|
||||
- Moudy Ho <moudy.ho@mediatek.com>
|
||||
|
||||
description: |
|
||||
One of Media Data Path 3 (MDP3) components used to write DMA with frame rotation.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt8183-mdp3-wrot
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
items:
|
||||
- description: phandle of GCE
|
||||
- description: GCE subsys id
|
||||
- description: register offset
|
||||
- description: register size
|
||||
description: The register of client driver can be configured by gce with
|
||||
4 arguments defined in this property. Each GCE subsys id is mapping to
|
||||
a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
|
||||
|
||||
mediatek,gce-events:
|
||||
description:
|
||||
The event id which is mapping to the specific hardware event signal
|
||||
to gce. The event id is defined in the gce header
|
||||
include/dt-bindings/gce/<chip>-gce.h of each chips.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- mediatek,gce-client-reg
|
||||
- mediatek,gce-events
|
||||
- power-domains
|
||||
- clocks
|
||||
- iommus
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/mt8183-clk.h>
|
||||
#include <dt-bindings/gce/mt8183-gce.h>
|
||||
#include <dt-bindings/power/mt8183-power.h>
|
||||
#include <dt-bindings/memory/mt8183-larb-port.h>
|
||||
|
||||
mdp3_wrot0: mdp3-wrot0@14005000 {
|
||||
compatible = "mediatek,mt8183-mdp3-wrot";
|
||||
reg = <0x14005000 0x1000>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
|
||||
mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
|
||||
<CMDQ_EVENT_MDP_WROT0_EOF>;
|
||||
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
|
||||
clocks = <&mmsys CLK_MM_MDP_WROT0>;
|
||||
iommus = <&iommu>;
|
||||
};
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||||
@@ -20,6 +20,7 @@ properties:
|
||||
- mediatek,mt8173-vcodec-enc-vp8
|
||||
- mediatek,mt8173-vcodec-enc
|
||||
- mediatek,mt8183-vcodec-enc
|
||||
- mediatek,mt8188-vcodec-enc
|
||||
- mediatek,mt8192-vcodec-enc
|
||||
- mediatek,mt8195-vcodec-enc
|
||||
|
||||
|
||||
@@ -57,6 +57,7 @@ properties:
|
||||
enum:
|
||||
- mediatek,mt8192-vcodec-dec
|
||||
- mediatek,mt8186-vcodec-dec
|
||||
- mediatek,mt8188-vcodec-dec
|
||||
- mediatek,mt8195-vcodec-dec
|
||||
|
||||
reg:
|
||||
|
||||
69
Documentation/devicetree/bindings/media/nxp,dw100.yaml
Normal file
69
Documentation/devicetree/bindings/media/nxp,dw100.yaml
Normal file
@@ -0,0 +1,69 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/media/nxp,dw100.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP i.MX8MP DW100 Dewarper core
|
||||
|
||||
maintainers:
|
||||
- Xavier Roumegue <xavier.roumegue@oss.nxp.com>
|
||||
|
||||
description: |-
|
||||
The Dewarp Engine provides high-performance dewarp processing for the
|
||||
correction of the distortion that is introduced in images produced by fisheye
|
||||
and wide angle lenses. It is implemented with a line/tile-cache based
|
||||
architecture. With configurable address mapping look up tables and per tile
|
||||
processing, it successfully generates a corrected output image.
|
||||
The engine can be used to perform scaling, cropping and pixel format
|
||||
conversion.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nxp,imx8mp-dw100
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: The AXI clock
|
||||
- description: The AHB clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: axi
|
||||
- const: ahb
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- power-domains
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx8mp-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/imx8mp-power.h>
|
||||
|
||||
dewarp: dwe@32e30000 {
|
||||
compatible = "nxp,imx8mp-dw100";
|
||||
reg = <0x32e30000 0x10000>;
|
||||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
|
||||
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
|
||||
clock-names = "axi", "ahb";
|
||||
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>;
|
||||
};
|
||||
@@ -17,6 +17,7 @@ description:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- renesas,r9a07g044-vsp2 # RZ/G2L
|
||||
- renesas,vsp1 # R-Car Gen2 and RZ/G1
|
||||
- renesas,vsp2 # R-Car Gen3 and RZ/G2
|
||||
|
||||
@@ -26,8 +27,8 @@ properties:
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
clocks: true
|
||||
clock-names: true
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
@@ -50,17 +51,43 @@ required:
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: renesas,vsp1
|
||||
then:
|
||||
properties:
|
||||
renesas,fcp: false
|
||||
else:
|
||||
required:
|
||||
- renesas,fcp
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,vsp1
|
||||
then:
|
||||
properties:
|
||||
renesas,fcp: false
|
||||
else:
|
||||
required:
|
||||
- renesas,fcp
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,r9a07g044-vsp2
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Main clock
|
||||
- description: Register access clock
|
||||
- description: Video clock
|
||||
clock-names:
|
||||
items:
|
||||
- const: aclk
|
||||
- const: pclk
|
||||
- const: vclk
|
||||
required:
|
||||
- clock-names
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 1
|
||||
clock-names: false
|
||||
|
||||
examples:
|
||||
# R8A7790 (R-Car H2) VSP1-S
|
||||
|
||||
@@ -0,0 +1,68 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/soc/mediatek/mediatek,ccorr.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek color correction
|
||||
|
||||
maintainers:
|
||||
- Matthias Brugger <matthias.bgg@gmail.com>
|
||||
- Moudy Ho <moudy.ho@mediatek.com>
|
||||
|
||||
description: |
|
||||
MediaTek color correction with 3X3 matrix.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt8183-mdp3-ccorr
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
items:
|
||||
- description: phandle of GCE
|
||||
- description: GCE subsys id
|
||||
- description: register offset
|
||||
- description: register size
|
||||
description: The register of client driver can be configured by gce with
|
||||
4 arguments defined in this property. Each GCE subsys id is mapping to
|
||||
a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
|
||||
|
||||
mediatek,gce-events:
|
||||
description:
|
||||
The event id which is mapping to the specific hardware event signal
|
||||
to gce. The event id is defined in the gce header
|
||||
include/dt-bindings/gce/<chip>-gce.h of each chips.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- mediatek,gce-client-reg
|
||||
- mediatek,gce-events
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/mt8183-clk.h>
|
||||
#include <dt-bindings/gce/mt8183-gce.h>
|
||||
|
||||
mdp3_ccorr: mdp3-ccorr@1401c000 {
|
||||
compatible = "mediatek,mt8183-mdp3-ccorr";
|
||||
reg = <0x1401c000 0x1000>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
|
||||
mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>,
|
||||
<CMDQ_EVENT_MDP_CCORR_EOF>;
|
||||
clocks = <&mmsys CLK_MM_MDP_CCORR>;
|
||||
};
|
||||
@@ -0,0 +1,81 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/soc/mediatek/mediatek,wdma.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Write Direct Memory Access
|
||||
|
||||
maintainers:
|
||||
- Matthias Brugger <matthias.bgg@gmail.com>
|
||||
- Moudy Ho <moudy.ho@mediatek.com>
|
||||
|
||||
description: |
|
||||
MediaTek Write Direct Memory Access(WDMA) component used to write
|
||||
the data into DMA.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt8183-mdp3-wdma
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
items:
|
||||
- description: phandle of GCE
|
||||
- description: GCE subsys id
|
||||
- description: register offset
|
||||
- description: register size
|
||||
description: The register of client driver can be configured by gce with
|
||||
4 arguments defined in this property. Each GCE subsys id is mapping to
|
||||
a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
|
||||
|
||||
mediatek,gce-events:
|
||||
description:
|
||||
The event id which is mapping to the specific hardware event signal
|
||||
to gce. The event id is defined in the gce header
|
||||
include/dt-bindings/gce/<chip>-gce.h of each chips.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- mediatek,gce-client-reg
|
||||
- mediatek,gce-events
|
||||
- power-domains
|
||||
- clocks
|
||||
- iommus
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/mt8183-clk.h>
|
||||
#include <dt-bindings/gce/mt8183-gce.h>
|
||||
#include <dt-bindings/power/mt8183-power.h>
|
||||
#include <dt-bindings/memory/mt8183-larb-port.h>
|
||||
|
||||
mdp3_wdma: mdp3-wdma@14006000 {
|
||||
compatible = "mediatek,mt8183-mdp3-wdma";
|
||||
reg = <0x14006000 0x1000>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
|
||||
mediatek,gce-events = <CMDQ_EVENT_MDP_WDMA0_SOF>,
|
||||
<CMDQ_EVENT_MDP_WDMA0_EOF>;
|
||||
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
|
||||
clocks = <&mmsys CLK_MM_MDP_WDMA0>;
|
||||
iommus = <&iommu>;
|
||||
};
|
||||
@@ -19,7 +19,7 @@ Global video workflow
|
||||
|
||||
a) QCI stopped
|
||||
Initially, the QCI interface is stopped.
|
||||
When a buffer is queued (pxa_videobuf_ops->buf_queue), the QCI starts.
|
||||
When a buffer is queued, start_streaming is called and the QCI starts.
|
||||
|
||||
b) QCI started
|
||||
More buffers can be queued while the QCI is started without halting the
|
||||
|
||||
84
Documentation/userspace-api/media/drivers/dw100.rst
Normal file
84
Documentation/userspace-api/media/drivers/dw100.rst
Normal file
@@ -0,0 +1,84 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
DW100 dewarp driver
|
||||
===================
|
||||
|
||||
The Vivante DW100 Dewarp Processor IP core found on i.MX8MP SoC applies a
|
||||
programmable geometrical transformation on the input image to correct distortion
|
||||
introduced by lenses.
|
||||
|
||||
The transformation function is exposed by the hardware as a grid map with 16x16
|
||||
pixel macroblocks indexed using X, Y vertex coordinates.
|
||||
::
|
||||
|
||||
Image width
|
||||
<--------------------------------------->
|
||||
|
||||
^ .-------.-------.-------.-------.-------.
|
||||
| | 16x16 | | | | |
|
||||
I | | pixel | | | | |
|
||||
m | | block | | | | |
|
||||
a | .-------.-------.-------.-------.-------.
|
||||
g | | | | | | |
|
||||
e | | | | | | |
|
||||
| | | | | | |
|
||||
h | .-------.-------.-------.-------.-------.
|
||||
e | | | | | | |
|
||||
i | | | | | | |
|
||||
g | | | | | | |
|
||||
h | .-------.-------.-------.-------.-------.
|
||||
t | | | | | | |
|
||||
| | | | | | |
|
||||
| | | | | | |
|
||||
v '-------'-------'-------'-------'-------'
|
||||
|
||||
Grid of Image Blocks for Dewarping Map
|
||||
|
||||
|
||||
Each x, y coordinate register uses 16 bits to record the coordinate address in
|
||||
an unsigned 12.4 fixed point format (UQ12.4).
|
||||
::
|
||||
|
||||
.----------------------.--------..----------------------.--------.
|
||||
| 31~20 | 19~16 || 15~4 | 3~0 |
|
||||
| (integer) | (frac) || (integer) | (frac) |
|
||||
'----------------------'--------''----------------------'--------'
|
||||
<-------------------------------><------------------------------->
|
||||
Y coordinate X coordinate
|
||||
|
||||
Remap Register Layout
|
||||
|
||||
The dewarping map is set from applications using the
|
||||
V4L2_CID_DW100_DEWARPING_16x16_VERTEX_MAP control. The control contains
|
||||
an array of u32 values storing (x, y) destination coordinates for each
|
||||
vertex of the grid. The x coordinate is stored in the 16 LSBs and the y
|
||||
coordinate in the 16 MSBs.
|
||||
|
||||
The number of elements in the array must match the image size:
|
||||
|
||||
.. code-block:: C
|
||||
|
||||
elems = (DIV_ROUND_UP(width, 16) + 1) * (DIV_ROUND_UP(height, 16) + 1);
|
||||
|
||||
If the control has not been set by the application, the driver uses an identity
|
||||
map.
|
||||
|
||||
More details on the DW100 hardware operations can be found in
|
||||
*chapter 13.15 DeWarp* of IMX8MP_ reference manual.
|
||||
|
||||
The Vivante DW100 m2m driver implements the following driver-specific control:
|
||||
|
||||
``V4L2_CID_DW100_DEWARPING_16x16_VERTEX_MAP (__u32 array)``
|
||||
Specifies to DW100 driver its dewarping map (aka LUT) blob as described in
|
||||
*chapter 13.15.2.3 Dewarping Remap* of IMX8MP_ reference manual as an U32
|
||||
dynamic array. The image is divided into many small 16x16 blocks. If the
|
||||
width/height of the image is not divisible by 16, the size of the
|
||||
rightmost/bottommost block is the remainder. The dewarping map only saves
|
||||
the vertex coordinates of the block. The dewarping grid map is comprised of
|
||||
vertex coordinates for x and y. Each x, y coordinate register uses 16 bits
|
||||
(UQ12.4) to record the coordinate address, with the Y coordinate in the
|
||||
upper bits and X in the lower bits. The driver modifies the dimensions of
|
||||
this control when the sink format is changed, to reflect the new input
|
||||
resolution.
|
||||
|
||||
.. _IMX8MP: https://www.nxp.com/webapp/Download?colCode=IMX8MPRM
|
||||
@@ -33,6 +33,7 @@ For more details see the file COPYING in the source distribution of Linux.
|
||||
|
||||
ccs
|
||||
cx2341x-uapi
|
||||
dw100
|
||||
imx-uapi
|
||||
max2175
|
||||
meye-uapi
|
||||
|
||||
@@ -1,9 +0,0 @@
|
||||
.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
|
||||
|
||||
.. _async:
|
||||
|
||||
****************
|
||||
Asynchronous I/O
|
||||
****************
|
||||
|
||||
This method is not defined yet.
|
||||
@@ -41,7 +41,7 @@ Devices supporting the raw VBI capturing or output API set the
|
||||
in the ``capabilities`` field of struct
|
||||
:c:type:`v4l2_capability` returned by the
|
||||
:ref:`VIDIOC_QUERYCAP` ioctl. At least one of the
|
||||
read/write, streaming or asynchronous I/O methods must be supported. VBI
|
||||
read/write or streaming I/O methods must be supported. VBI
|
||||
devices may or may not have a tuner or modulator.
|
||||
|
||||
Supplemental Functions
|
||||
|
||||
@@ -34,7 +34,7 @@ Devices supporting the SDR transmitter interface set the
|
||||
device has an Digital to Analog Converter (DAC), which is a mandatory
|
||||
element for the SDR transmitter.
|
||||
|
||||
At least one of the read/write, streaming or asynchronous I/O methods
|
||||
At least one of the read/write or streaming I/O methods
|
||||
must be supported.
|
||||
|
||||
|
||||
|
||||
@@ -36,7 +36,7 @@ Devices supporting the sliced VBI capturing or output API set the
|
||||
respectively, in the ``capabilities`` field of struct
|
||||
:c:type:`v4l2_capability` returned by the
|
||||
:ref:`VIDIOC_QUERYCAP` ioctl. At least one of the
|
||||
read/write, streaming or asynchronous :ref:`I/O methods <io>` must be
|
||||
read/write or streaming :ref:`I/O methods <io>` must be
|
||||
supported. Sliced VBI devices may have a tuner or modulator.
|
||||
|
||||
Supplemental Functions
|
||||
|
||||
@@ -316,7 +316,7 @@ This unnamed version was finally merged into Linux 2.5.46.
|
||||
There are new fields to identify the driver, a new RDS device
|
||||
function ``V4L2_CAP_RDS_CAPTURE``, the ``V4L2_CAP_AUDIO`` flag
|
||||
indicates if the device has any audio connectors, another I/O
|
||||
capability ``V4L2_CAP_ASYNCIO`` can be flagged. In response to these
|
||||
capability V4L2_CAP_ASYNCIO can be flagged. In response to these
|
||||
changes the ``type`` field became a bit set and was merged into the
|
||||
``flags`` field. ``V4L2_FLAG_TUNER`` was renamed to
|
||||
``V4L2_CAP_TUNER``, ``V4L2_CAP_VIDEO_OVERLAY`` replaced
|
||||
|
||||
@@ -17,8 +17,7 @@ read or write will fail at any time.
|
||||
|
||||
Other methods must be negotiated. To select the streaming I/O method
|
||||
with memory mapped or user buffers applications call the
|
||||
:ref:`VIDIOC_REQBUFS` ioctl. The asynchronous I/O
|
||||
method is not defined yet.
|
||||
:ref:`VIDIOC_REQBUFS` ioctl.
|
||||
|
||||
Video overlay can be considered another I/O method, although the
|
||||
application does not directly receive the image data. It is selected by
|
||||
@@ -46,6 +45,5 @@ The following sections describe the various I/O methods in more detail.
|
||||
mmap
|
||||
userp
|
||||
dmabuf
|
||||
async
|
||||
buffer
|
||||
field-order
|
||||
|
||||
@@ -332,6 +332,11 @@ call.
|
||||
- 0x0004
|
||||
- This control event was triggered because the minimum, maximum,
|
||||
step or the default value of the control changed.
|
||||
* - ``V4L2_EVENT_CTRL_CH_DIMENSIONS``
|
||||
- 0x0008
|
||||
- This control event was triggered because the dimensions of the
|
||||
control changed. Note that the number of dimensions remains the
|
||||
same.
|
||||
|
||||
|
||||
.. tabularcolumns:: |p{6.6cm}|p{2.2cm}|p{8.5cm}|
|
||||
|
||||
@@ -244,9 +244,6 @@ specification the ioctl returns an ``EINVAL`` error code.
|
||||
- 0x01000000
|
||||
- The device supports the :c:func:`read()` and/or
|
||||
:c:func:`write()` I/O methods.
|
||||
* - ``V4L2_CAP_ASYNCIO``
|
||||
- 0x02000000
|
||||
- The device supports the :ref:`asynchronous <async>` I/O methods.
|
||||
* - ``V4L2_CAP_STREAMING``
|
||||
- 0x04000000
|
||||
- The device supports the :ref:`streaming <mmap>` I/O method.
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user