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Merge tag 'phy-for-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

Browse Source 
Pull phy updates from Vinod Koul:
 "This contains bunch of new device support and one new Sunplus driver
  along with updates which include another big round of qmp phy
  conversion.

  New support:
   - Qualcomm SC8280XP eDP & DP and USB3 UNI phy (Bjorn Andersson)
   - Rockchip rk3568 inno dsidphy (Chris Morgan)
   - ocelot-serdes phy yaml binding (Colin Foster)
   - Renesas gen2-usb phy yaml binding (Geert Uytterhoeven)
   - RGMII suport in lan966x driver (Horatiu Vultur)
   - Qualcomm SM6375 usb snps-femto-v2 bindings (Konrad Dybcio)
   - Rockchip rk356x csi-dphya (Michael Riesch)
   - Qualcomm sdm670 usb2 bindings (Richard Acayan)
   - Sunplus USB2 PHY (Vincent Shih)

  Updates:
   - Mediatek hdmi, ufs, tphy and xsphy updates to use bitfield helpers
     (Chunfeng Yun)
   - Continued Qualcomm qmp phy driver split and cleanup. More patches
     are under review and expected that next cycle might see completion
     of this activity (Dmitry Baryshkov & Johan Hovold)
   - TI wiz driver support for j7200 10g (Roger Quadros)
   - Qualcomm femto phy driver support for override params to help with
     tuning (Sandeep Maheswaram)
   - SGMII support in TI wiz driver (Siddharth Vadapalli)
   - dev_err_probe simplification (Yuan Can)"

* tag 'phy-for-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (170 commits)
  phy: phy-mtk-dp: make array driving_params static const
  dt-bindings: phy: qcom,qusb2: document sdm670 compatible
  phy: qcom-qmp-pcie: fix resource mapping for SDM845 QHP PHY
  phy: rockchip-snps-pcie3: only look for rockchip,pipe-grf on rk3588
  phy: tegra: xusb: Enable usb role switch attribute
  phy: mediatek: fix build warning of FIELD_PREP()
  phy: qcom-qmp-usb: Use dev_err_probe() to simplify code
  phy: qcom-qmp-ufs: Use dev_err_probe() to simplify code
  phy: qcom-qmp-pcie-msm8996: Use dev_err_probe() to simplify code
  phy: qcom-qmp-combo: Use dev_err_probe() to simplify code
  phy: qualcomm: call clk_disable_unprepare in the error handling
  phy: intel: Use dev_err_probe() to simplify code
  phy: tegra: xusb: Use dev_err_probe() to simplify code
  phy: qcom-snps: Use dev_err_probe() to simplify code
  phy: qcom-qusb2: Use dev_err_probe() to simplify code
  phy: qcom-qmp-pcie: Use dev_err_probe() to simplify code
  phy: ti: phy-j721e-wiz: fix reference leaks in wiz_probe()
  phy: mediatek: mipi: remove register access helpers
  phy: mediatek: mipi: mt8183: use common helper to access registers
  phy: mediatek: mipi: mt8183: use GENMASK to generate bits mask
  ...
This commit is contained in:
Linus Torvalds
2022-10-07 16:03:01 -07:00
parent 416a2f4f91 9aa0dade8f
commit 33e591dee9
77 changed files with 5343 additions and 2646 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
View File

@@ -54,6 +54,12 @@ patternProperties:
description:
Clock provider for TI EHRPWM nodes.
"phy@[0-9a-f]+$":
type: object
$ref: /schemas/phy/ti,phy-gmii-sel.yaml#
description:
The phy node corresponding to the ethernet MAC.
required:
- compatible
- reg

1
Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.yaml
View File

@@ -32,6 +32,7 @@ properties:
patternProperties:
"^pcie-phy@[0-9]+$":
type: object
additionalProperties: false
description: >
PCIe PHY child nodes

2
Documentation/devicetree/bindings/phy/cdns,dphy-rx.yaml
View File

@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence DPHY Rx Device Tree Bindings
maintainers:
- Pratyush Yadav <p.yadav@ti.com>
- Pratyush Yadav <pratyush@kernel.org>
properties:
compatible:

2
Documentation/devicetree/bindings/phy/cdns,dphy.yaml
View File

@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence DPHY Device Tree Bindings
maintainers:
- Pratyush Yadav <p.yadav@ti.com>
- Pratyush Yadav <pratyush@kernel.org>
properties:
compatible:

11
Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
View File

@@ -163,6 +163,7 @@ patternProperties:
- PHY_TYPE_USB3
- PHY_TYPE_PCIE
- PHY_TYPE_SATA
- PHY_TYPE_SGMII
nvmem-cells:
items:
@@ -218,6 +219,16 @@ patternProperties:
minimum: 1
maximum: 15
mediatek,pre-emphasis:
description:
The level of pre-emphasis which used to widen the eye opening and
boost eye swing, the unit step is about 4.16% increment; e.g. the
level 1 means amplitude increases about 4.16%, the level 2 is about
8.3% etc. (U2 phy)
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
maximum: 3
mediatek,bc12:
description:
Specify the flag to enable BC1.2 if support it

56
Documentation/devicetree/bindings/phy/mscc,vsc7514-serdes.yaml Normal file
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@@ -0,0 +1,56 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/mscc,vsc7514-serdes.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microsemi Ocelot SerDes muxing
maintainers:
- Alexandre Belloni <alexandre.belloni@bootlin.com>
- UNGLinuxDriver@microchip.com
description: |
On Microsemi Ocelot, there is a handful of registers in HSIO address
space for setting up the SerDes to switch port muxing.
A SerDes X can be "muxed" to work with switch port Y or Z for example.
One specific SerDes can also be used as a PCIe interface.
Hence, a SerDes represents an interface, be it an Ethernet or a PCIe one.
There are two kinds of SerDes: SERDES1G supports 10/100Mbps in
half/full-duplex and 1000Mbps in full-duplex mode while SERDES6G supports
10/100Mbps in half/full-duplex and 1000/2500Mbps in full-duplex mode.
Also, SERDES6G number (aka "macro") 0 is the only interface supporting
QSGMII.
This is a child of the HSIO syscon ("mscc,ocelot-hsio", see
Documentation/devicetree/bindings/mips/mscc.txt) on the Microsemi Ocelot.
properties:
compatible:
enum:
- mscc,vsc7514-serdes
"#phy-cells":
const: 2
description: |
The first number defines the input port to use for a given SerDes macro.
The second defines the macro to use. They are defined in
dt-bindings/phy/phy-ocelot-serdes.h
required:
- compatible
- "#phy-cells"
additionalProperties:
false
examples:
- |
serdes: serdes {
compatible = "mscc,vsc7514-serdes";
#phy-cells = <2>;
};

43
Documentation/devicetree/bindings/phy/phy-ocelot-serdes.txt
View File

@@ -1,43 +0,0 @@
Microsemi Ocelot SerDes muxing driver
-------------------------------------
On Microsemi Ocelot, there is a handful of registers in HSIO address
space for setting up the SerDes to switch port muxing.
A SerDes X can be "muxed" to work with switch port Y or Z for example.
One specific SerDes can also be used as a PCIe interface.
Hence, a SerDes represents an interface, be it an Ethernet or a PCIe one.
There are two kinds of SerDes: SERDES1G supports 10/100Mbps in
half/full-duplex and 1000Mbps in full-duplex mode while SERDES6G supports
10/100Mbps in half/full-duplex and 1000/2500Mbps in full-duplex mode.
Also, SERDES6G number (aka "macro") 0 is the only interface supporting
QSGMII.
This is a child of the HSIO syscon ("mscc,ocelot-hsio", see
Documentation/devicetree/bindings/mips/mscc.txt) on the Microsemi Ocelot.
Required properties:
- compatible: should be "mscc,vsc7514-serdes"
- #phy-cells : from the generic phy bindings, must be 2.
The first number defines the input port to use for a given
SerDes macro. The second defines the macro to use. They are
defined in dt-bindings/phy/phy-ocelot-serdes.h
Example:
serdes: serdes {
compatible = "mscc,vsc7514-serdes";
#phy-cells = <2>;
};
ethernet {
port1 {
phy-handle = <&phy_foo>;
/* Link SERDES1G_5 to port1 */
phys = <&serdes 1 SERDES1G_5>;
};
};

1
Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
View File

@@ -13,6 +13,7 @@ properties:
compatible:
enum:
- rockchip,px30-usb2phy
- rockchip,rk3128-usb2phy
- rockchip,rk3228-usb2phy
- rockchip,rk3308-usb2phy
- rockchip,rk3328-usb2phy

2
Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
View File

@@ -77,6 +77,8 @@ patternProperties:
connector:
type: object
$ref: /schemas/connector/usb-connector.yaml
unevaluatedProperties: false
properties:
vbus-supply: true

2
Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
View File

@@ -19,6 +19,8 @@ properties:
enum:
- qcom,sc7280-edp-phy
- qcom,sc8180x-edp-phy
- qcom,sc8280xp-dp-phy
- qcom,sc8280xp-edp-phy
reg:
items:

189
Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml Normal file
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@@ -0,0 +1,189 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm QMP PHY controller (MSM8996 PCIe)
maintainers:
- Vinod Koul <vkoul@kernel.org>
description:
QMP PHY controller supports physical layer functionality for a number of
controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
properties:
compatible:
const: qcom,msm8996-qmp-pcie-phy
reg:
items:
- description: serdes
"#address-cells":
enum: [ 1, 2 ]
"#size-cells":
enum: [ 1, 2 ]
ranges: true
clocks:
maxItems: 3
clock-names:
items:
- const: aux
- const: cfg_ahb
- const: ref
resets:
maxItems: 3
reset-names:
items:
- const: phy
- const: common
- const: cfg
vdda-phy-supply: true
vdda-pll-supply: true
vddp-ref-clk-supply: true
patternProperties:
"^phy@[0-9a-f]+$":
type: object
description: one child node per PHY provided by this block
properties:
reg:
items:
- description: TX
- description: RX
- description: PCS
clocks:
items:
- description: PIPE clock
clock-names:
deprecated: true
items:
- enum:
- pipe0
- pipe1
- pipe2
resets:
items:
- description: PHY reset
reset-names:
deprecated: true
items:
- enum:
- lane0
- lane1
- lane2
"#clock-cells":
const: 0
clock-output-names:
maxItems: 1
"#phy-cells":
const: 0
required:
- reg
- clocks
- resets
- "#clock-cells"
- clock-output-names
- "#phy-cells"
additionalProperties: false
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
- ranges
- clocks
- clock-names
- resets
- reset-names
- vdda-phy-supply
- vdda-pll-supply
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
pcie_phy: phy-wrapper@34000 {
compatible = "qcom,msm8996-qmp-pcie-phy";
reg = <0x34000 0x488>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x34000 0x4000>;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
<&gcc GCC_PCIE_CLKREF_CLK>;
clock-names = "aux", "cfg_ahb", "ref";
resets = <&gcc GCC_PCIE_PHY_BCR>,
<&gcc GCC_PCIE_PHY_COM_BCR>,
<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
reset-names = "phy", "common", "cfg";
vdda-phy-supply = <&vreg_l28a_0p925>;
vdda-pll-supply = <&vreg_l12a_1p8>;
pciephy_0: phy@1000 {
reg = <0x1000 0x130>,
<0x1200 0x200>,
<0x1400 0x1dc>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
#clock-cells = <0>;
clock-output-names = "pcie_0_pipe_clk_src";
#phy-cells = <0>;
};
pciephy_1: phy@2000 {
reg = <0x2000 0x130>,
<0x2200 0x200>,
<0x2400 0x1dc>;
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
#clock-cells = <0>;
clock-output-names = "pcie_1_pipe_clk_src";
#phy-cells = <0>;
};
pciephy_2: phy@3000 {
reg = <0x3000 0x130>,
<0x3200 0x200>,
<0x3400 0x1dc>;
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
resets = <&gcc GCC_PCIE_2_PHY_BCR>;
#clock-cells = <0>;
clock-output-names = "pcie_2_pipe_clk_src";
#phy-cells = <0>;
};
};

296
Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml Normal file
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@@ -0,0 +1,296 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,qmp-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm QMP PHY controller (PCIe)
maintainers:
- Vinod Koul <vkoul@kernel.org>
description:
QMP PHY controller supports physical layer functionality for a number of
controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
properties:
compatible:
enum:
- qcom,ipq6018-qmp-pcie-phy
- qcom,ipq8074-qmp-gen3-pcie-phy
- qcom,ipq8074-qmp-pcie-phy
- qcom,msm8998-qmp-pcie-phy
- qcom,sc8180x-qmp-pcie-phy
- qcom,sdm845-qhp-pcie-phy
- qcom,sdm845-qmp-pcie-phy
- qcom,sdx55-qmp-pcie-phy
- qcom,sm8250-qmp-gen3x1-pcie-phy
- qcom,sm8250-qmp-gen3x2-pcie-phy
- qcom,sm8250-qmp-modem-pcie-phy
- qcom,sm8450-qmp-gen3x1-pcie-phy
- qcom,sm8450-qmp-gen4x2-pcie-phy
reg:
items:
- description: serdes
"#address-cells":
enum: [ 1, 2 ]
"#size-cells":
enum: [ 1, 2 ]
ranges: true
clocks:
minItems: 2
maxItems: 4
clock-names:
minItems: 2
maxItems: 4
resets:
minItems: 1
maxItems: 2
reset-names:
minItems: 1
maxItems: 2
vdda-phy-supply: true
vdda-pll-supply: true
vddp-ref-clk-supply: true
patternProperties:
"^phy@[0-9a-f]+$":
type: object
description: single PHY-provider child node
properties:
reg:
minItems: 3
maxItems: 6
clocks:
items:
- description: PIPE clock
clock-names:
deprecated: true
items:
- const: pipe0
"#clock-cells":
const: 0
clock-output-names:
maxItems: 1
"#phy-cells":
const: 0
required:
- reg
- clocks
- "#clock-cells"
- clock-output-names
- "#phy-cells"
additionalProperties: false
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
- ranges
- clocks
- clock-names
- resets
- reset-names
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8998-qmp-pcie-phy
then:
properties:
clocks:
maxItems: 3
clock-names:
items:
- const: aux
- const: cfg_ahb
- const: ref
resets:
maxItems: 2
reset-names:
items:
- const: phy
- const: common
required:
- vdda-phy-supply
- vdda-pll-supply
- if:
properties:
compatible:
contains:
enum:
- qcom,ipq6018-qmp-pcie-phy
- qcom,ipq8074-qmp-gen3-pcie-phy
- qcom,ipq8074-qmp-pcie-phy
then:
properties:
clocks:
maxItems: 2
clock-names:
items:
- const: aux
- const: cfg_ahb
resets:
maxItems: 2
reset-names:
items:
- const: phy
- const: common
- if:
properties:
compatible:
contains:
enum:
- qcom,sc8180x-qmp-pcie-phy
- qcom,sdm845-qhp-pcie-phy
- qcom,sdm845-qmp-pcie-phy
- qcom,sdx55-qmp-pcie-phy
- qcom,sm8250-qmp-gen3x1-pcie-phy
- qcom,sm8250-qmp-gen3x2-pcie-phy
- qcom,sm8250-qmp-modem-pcie-phy
- qcom,sm8450-qmp-gen3x1-pcie-phy
- qcom,sm8450-qmp-gen4x2-pcie-phy
then:
properties:
clocks:
maxItems: 4
clock-names:
items:
- const: aux
- const: cfg_ahb
- const: ref
- const: refgen
resets:
maxItems: 1
reset-names:
items:
- const: phy
required:
- vdda-phy-supply
- vdda-pll-supply
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8250-qmp-gen3x2-pcie-phy
- qcom,sm8250-qmp-modem-pcie-phy
- qcom,sm8450-qmp-gen4x2-pcie-phy
then:
patternProperties:
"^phy@[0-9a-f]+$":
properties:
reg:
items:
- description: TX lane 1
- description: RX lane 1
- description: PCS
- description: TX lane 2
- description: RX lane 2
- description: PCS_MISC
- if:
properties:
compatible:
contains:
enum:
- qcom,sc8180x-qmp-pcie-phy
- qcom,sdm845-qmp-pcie-phy
- qcom,sdx55-qmp-pcie-phy
- qcom,sm8250-qmp-gen3x1-pcie-phy
- qcom,sm8450-qmp-gen3x1-pcie-phy
then:
patternProperties:
"^phy@[0-9a-f]+$":
properties:
reg:
items:
- description: TX
- description: RX
- description: PCS
- description: PCS_MISC
- if:
properties:
compatible:
contains:
enum:
- qcom,ipq6018-qmp-pcie-phy
- qcom,ipq8074-qmp-pcie-phy
- qcom,msm8998-qmp-pcie-phy
- qcom,sdm845-qhp-pcie-phy
then:
patternProperties:
"^phy@[0-9a-f]+$":
properties:
reg:
items:
- description: TX
- description: RX
- description: PCS
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
phy-wrapper@1c0e000 {
compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
reg = <0x01c0e000 0x1c0>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x01c0e000 0x1000>;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
<&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "refgen";
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "phy";
vdda-phy-supply = <&vreg_l10c_0p88>;
vdda-pll-supply = <&vreg_l6b_1p2>;
phy@200 {
reg = <0x200 0x170>,
<0x400 0x200>,
<0xa00 0x1f0>,
<0x600 0x170>,
<0x800 0x200>,
<0xe00 0xf4>;
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
#clock-cells = <0>;
clock-output-names = "pcie_1_pipe_clk";
#phy-cells = <0>;
};
};

502
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
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240
Documentation/devicetree/bindings/phy/qcom,qmp-ufs-phy.yaml Normal file
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@@ -0,0 +1,240 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,qmp-ufs-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm QMP PHY controller (UFS)
maintainers:
- Vinod Koul <vkoul@kernel.org>
description:
QMP PHY controller supports physical layer functionality for a number of
controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
properties:
compatible:
enum:
- qcom,msm8996-qmp-ufs-phy
- qcom,msm8998-qmp-ufs-phy
- qcom,sc8180x-qmp-ufs-phy
- qcom,sc8280xp-qmp-ufs-phy
- qcom,sdm845-qmp-ufs-phy
- qcom,sm6115-qmp-ufs-phy
- qcom,sm6350-qmp-ufs-phy
- qcom,sm8150-qmp-ufs-phy
- qcom,sm8250-qmp-ufs-phy
- qcom,sm8350-qmp-ufs-phy
- qcom,sm8450-qmp-ufs-phy
reg:
items:
- description: serdes
"#address-cells":
enum: [ 1, 2 ]
"#size-cells":
enum: [ 1, 2 ]
ranges: true
clocks:
minItems: 1
maxItems: 3
clock-names:
minItems: 1
maxItems: 3
power-domains:
maxItems: 1
resets:
maxItems: 1
reset-names:
items:
- const: ufsphy
vdda-phy-supply: true
vdda-pll-supply: true
vddp-ref-clk-supply: true
patternProperties:
"^phy@[0-9a-f]+$":
type: object
description: single PHY-provider child node
properties:
reg:
minItems: 3
maxItems: 6
"#phy-cells":
const: 0
required:
- reg
- "#phy-cells"
additionalProperties: false
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
- ranges
- clocks
- clock-names
- resets
- reset-names
- vdda-phy-supply
- vdda-pll-supply
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8996-qmp-ufs-phy
then:
properties:
clocks:
maxItems: 1
clock-names:
items:
- const: ref
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8998-qmp-ufs-phy
- qcom,sc8180x-qmp-ufs-phy
- qcom,sc8280xp-qmp-ufs-phy
- qcom,sdm845-qmp-ufs-phy
- qcom,sm6115-qmp-ufs-phy
- qcom,sm6350-qmp-ufs-phy
- qcom,sm8150-qmp-ufs-phy
- qcom,sm8250-qmp-ufs-phy
then:
properties:
clocks:
maxItems: 2
clock-names:
items:
- const: ref
- const: ref_aux
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8450-qmp-ufs-phy
then:
properties:
clocks:
maxItems: 3
clock-names:
items:
- const: ref
- const: ref_aux
- const: qref
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8998-qmp-ufs-phy
- qcom,sc8280xp-qmp-ufs-phy
- qcom,sdm845-qmp-ufs-phy
- qcom,sm6350-qmp-ufs-phy
- qcom,sm8150-qmp-ufs-phy
- qcom,sm8250-qmp-ufs-phy
- qcom,sm8350-qmp-ufs-phy
- qcom,sm8450-qmp-ufs-phy
then:
patternProperties:
"^phy@[0-9a-f]+$":
properties:
reg:
items:
- description: TX lane 1
- description: RX lane 1
- description: PCS
- description: TX lane 2
- description: RX lane 2
- if:
properties:
compatible:
contains:
enum:
- qcom,sc8180x-qmp-ufs-phy
then:
patternProperties:
"^phy@[0-9a-f]+$":
properties:
reg:
items:
- description: TX
- description: RX
- description: PCS
- description: PCS_MISC
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8996-qmp-ufs-phy
- qcom,sm6115-qmp-ufs-phy
then:
patternProperties:
"^phy@[0-9a-f]+$":
properties:
reg:
items:
- description: TX
- description: RX
- description: PCS
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
#include <dt-bindings/clock/qcom,rpmh.h>
phy-wrapper@1d87000 {
compatible = "qcom,sc8280xp-qmp-ufs-phy";
reg = <0x01d87000 0xe10>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x01d87000 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
clock-names = "ref", "ref_aux";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
vdda-phy-supply = <&vreg_l6b>;
vdda-pll-supply = <&vreg_l3b>;
phy@400 {
reg = <0x400 0x108>,
<0x600 0x1e0>,
<0xc00 0x1dc>,
<0x800 0x108>,
<0xa00 0x1e0>;
#phy-cells = <0>;
};
};

401
Documentation/devicetree/bindings/phy/qcom,qmp-usb-phy.yaml Normal file
View File

@@ -0,0 +1,401 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,qmp-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm QMP PHY controller (USB)
maintainers:
- Vinod Koul <vkoul@kernel.org>
description:
QMP PHY controller supports physical layer functionality for a number of
controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
properties:
compatible:
enum:
- qcom,ipq6018-qmp-usb3-phy
- qcom,ipq8074-qmp-usb3-phy
- qcom,msm8996-qmp-usb3-phy
- qcom,msm8998-qmp-usb3-phy
- qcom,qcm2290-qmp-usb3-phy
- qcom,sc7180-qmp-usb3-phy
- qcom,sc8180x-qmp-usb3-phy
- qcom,sc8280xp-qmp-usb3-uni-phy
- qcom,sdm845-qmp-usb3-phy
- qcom,sdm845-qmp-usb3-uni-phy
- qcom,sdx55-qmp-usb3-uni-phy
- qcom,sdx65-qmp-usb3-uni-phy
- qcom,sm8150-qmp-usb3-phy
- qcom,sm8150-qmp-usb3-uni-phy
- qcom,sm8250-qmp-usb3-phy
- qcom,sm8250-qmp-usb3-uni-phy
- qcom,sm8350-qmp-usb3-phy
- qcom,sm8350-qmp-usb3-uni-phy
- qcom,sm8450-qmp-usb3-phy
reg:
minItems: 1
items:
- description: serdes
- description: DP_COM
"#address-cells":
enum: [ 1, 2 ]
"#size-cells":
enum: [ 1, 2 ]
ranges: true
clocks:
minItems: 3
maxItems: 4
clock-names:
minItems: 3
maxItems: 4
power-domains:
maxItems: 1
resets:
maxItems: 2
reset-names:
maxItems: 2
vdda-phy-supply: true
vdda-pll-supply: true
vddp-ref-clk-supply: true
patternProperties:
"^phy@[0-9a-f]+$":
type: object
description: single PHY-provider child node
properties:
reg:
minItems: 3
maxItems: 6
clocks:
items:
- description: PIPE clock
clock-names:
deprecated: true
items:
- const: pipe0
"#clock-cells":
const: 0
clock-output-names:
maxItems: 1
"#phy-cells":
const: 0
required:
- reg
- clocks
- "#clock-cells"
- clock-output-names
- "#phy-cells"
additionalProperties: false
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
- ranges
- clocks
- clock-names
- resets
- reset-names
- vdda-phy-supply
- vdda-pll-supply
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,sc7180-qmp-usb3-phy
then:
properties:
clocks:
maxItems: 4
clock-names:
items:
- const: aux
- const: cfg_ahb
- const: ref
- const: com_aux
resets:
maxItems: 1
reset-names:
items:
- const: phy
- if:
properties:
compatible:
contains:
enum:
- qcom,sdm845-qmp-usb3-uni-phy
then:
properties:
clocks:
maxItems: 4
clock-names:
items:
- const: aux
- const: cfg_ahb
- const: ref
- const: com_aux
resets:
maxItems: 2
reset-names:
items:
- const: phy
- const: common
- if:
properties:
compatible:
contains:
enum:
- qcom,ipq8074-qmp-usb3-phy
- qcom,msm8996-qmp-usb3-phy
- qcom,msm8998-qmp-usb3-phy
- qcom,sdx55-qmp-usb3-uni-phy
- qcom,sdx65-qmp-usb3-uni-phy
then:
properties:
clocks:
maxItems: 3
clock-names:
items:
- const: aux
- const: cfg_ahb
- const: ref
resets:
maxItems: 2
reset-names:
items:
- const: phy
- const: common
- if:
properties:
compatible:
contains:
enum:
- qcom,sc8280xp-qmp-usb3-uni-phy
- qcom,sm8150-qmp-usb3-phy
- qcom,sm8150-qmp-usb3-uni-phy
- qcom,sm8250-qmp-usb3-uni-phy
- qcom,sm8350-qmp-usb3-uni-phy
then:
properties:
clocks:
maxItems: 4
clock-names:
items:
- const: aux
- const: ref_clk_src
- const: ref
- const: com_aux
resets:
maxItems: 2
reset-names:
items:
- const: phy
- const: common
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8250-qmp-usb3-phy
- qcom,sm8350-qmp-usb3-phy
then:
properties:
clocks:
maxItems: 3
clock-names:
items:
- const: aux
- const: ref_clk_src
- const: com_aux
resets:
maxItems: 2
reset-names:
items:
- const: phy
- const: common
- if:
properties:
compatible:
contains:
enum:
- qcom,qcm2290-qmp-usb3-phy
then:
properties:
clocks:
maxItems: 3
clock-names:
items:
- const: cfg_ahb
- const: ref
- const: com_aux
resets:
maxItems: 2
reset-names:
items:
- const: phy_phy
- const: phy
- if:
properties:
compatible:
contains:
enum:
- qcom,sc8280xp-qmp-usb3-uni-phy
then:
required:
- power-domains
- if:
properties:
compatible:
contains:
enum:
- qcom,sdm845-qmp-usb3-phy
- qcom,sm8150-qmp-usb3-phy
- qcom,sm8350-qmp-usb3-phy
- qcom,sm8450-qmp-usb3-phy
then:
patternProperties:
"^phy@[0-9a-f]+$":
properties:
reg:
items:
- description: TX lane 1
- description: RX lane 1
- description: PCS
- description: TX lane 2
- description: RX lane 2
- description: PCS_MISC
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8998-qmp-usb3-phy
then:
patternProperties:
"^phy@[0-9a-f]+$":
properties:
reg:
items:
- description: TX lane 1
- description: RX lane 1
- description: PCS
- description: TX lane 2
- description: RX lane 2
- if:
properties:
compatible:
contains:
enum:
- qcom,ipq6018-qmp-usb3-phy
- qcom,ipq8074-qmp-usb3-phy
- qcom,qcm2290-qmp-usb3-phy
- qcom,sc7180-qmp-usb3-phy
- qcom,sc8180x-qmp-usb3-phy
- qcom,sdx55-qmp-usb3-uni-phy
- qcom,sdx65-qmp-usb3-uni-phy
- qcom,sm8150-qmp-usb3-uni-phy
- qcom,sm8250-qmp-usb3-phy
then:
patternProperties:
"^phy@[0-9a-f]+$":
properties:
reg:
items:
- description: TX
- description: RX
- description: PCS
- description: PCS_MISC
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8996-qmp-usb3-phy
- qcom,sc8280xp-qmp-usb3-uni-phy
- qcom,sm8250-qmp-usb3-uni-phy
- qcom,sm8350-qmp-usb3-uni-phy
then:
patternProperties:
"^phy@[0-9a-f]+$":
properties:
reg:
items:
- description: TX
- description: RX
- description: PCS
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
usb_2_qmpphy: phy-wrapper@88eb000 {
compatible = "qcom,sdm845-qmp-usb3-uni-phy";
reg = <0x088eb000 0x18c>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x088eb000 0x2000>;
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_CLK>,
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "com_aux";
resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
<&gcc GCC_USB3_PHY_SEC_BCR>;
reset-names = "phy", "common";
vdda-phy-supply = <&vdda_usb2_ss_1p2>;
vdda-pll-supply = <&vdda_usb2_ss_core>;
usb_2_ssphy: phy@200 {
reg = <0x200 0x128>,
<0x400 0x1fc>,
<0x800 0x218>,
<0x600 0x70>;
clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
#clock-cells = <0>;
clock-output-names = "usb3_uni_phy_pipe_clk_src";
#phy-cells = <0>;
};
};

25
Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
View File

@@ -16,6 +16,7 @@ properties:
- qcom,sc7180-qmp-usb3-dp-phy
- qcom,sc7280-qmp-usb3-dp-phy
- qcom,sc8180x-qmp-usb3-dp-phy
- qcom,sc8280xp-qmp-usb43dp-phy
- qcom,sdm845-qmp-usb3-dp-phy
- qcom,sm8250-qmp-usb3-dp-phy
reg:
@@ -30,9 +31,6 @@ properties:
- const: dp_com
- const: dp
"#clock-cells":
enum: [ 1, 2 ]
"#address-cells":
enum: [ 1, 2 ]
@@ -55,6 +53,9 @@ properties:
- const: ref
- const: com_aux
power-domains:
maxItems: 1
resets:
items:
- description: reset of phy block.
@@ -81,6 +82,7 @@ properties:
patternProperties:
"^usb3-phy@[0-9a-f]+$":
type: object
additionalProperties: false
description:
The USB3 PHY.
@@ -99,6 +101,7 @@ patternProperties:
- description: pipe clock
clock-names:
deprecated: true
items:
- const: pipe0
@@ -115,12 +118,12 @@ patternProperties:
required:
- reg
- clocks
- clock-names
- '#clock-cells'
- '#phy-cells'
"^dp-phy@[0-9a-f]+$":
type: object
additionalProperties: false
description:
The DP PHY.
@@ -147,7 +150,6 @@ patternProperties:
required:
- compatible
- reg
- "#clock-cells"
- "#address-cells"
- "#size-cells"
- ranges
@@ -160,6 +162,17 @@ required:
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,sc8280xp-qmp-usb43dp-phy
then:
required:
- power-domains
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
@@ -169,7 +182,6 @@ examples:
<0x088e8000 0x10>,
<0x088ea000 0x40>;
reg-names = "usb", "dp_com", "dp";
#clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x088e9000 0x2000>;
@@ -197,7 +209,6 @@ examples:
#clock-cells = <0>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
};

1
Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
View File

@@ -30,6 +30,7 @@ properties:
- items:
- enum:
- qcom,sc7180-qusb2-phy
- qcom,sdm670-qusb2-phy
- qcom,sdm845-qusb2-phy
- qcom,sm6350-qusb2-phy
- const: qcom,qusb2-v2-phy

89
Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml
View File

@@ -20,6 +20,7 @@ properties:
- qcom,sc7280-usb-hs-phy
- qcom,sc8180x-usb-hs-phy
- qcom,sc8280xp-usb-hs-phy
- qcom,sm6375-usb-hs-phy
- qcom,sm8150-usb-hs-phy
- qcom,sm8250-usb-hs-phy
- qcom,sm8350-usb-hs-phy
@@ -53,6 +54,94 @@ properties:
vdda33-supply:
description: phandle to the regulator 3.3V supply node.
qcom,hs-disconnect-bp:
description:
This adjusts the voltage level for the threshold used to
detect a disconnect event at the host.
The hardware accepts only discrete values. The value closest to the
provided input will be chosen as the override value for this param.
minimum: -272
maximum: 2156
qcom,squelch-detector-bp:
description:
This adjusts the voltage level for the threshold used to
detect valid high-speed data.
The hardware accepts only discrete values. The value closest to the
provided input will be chosen as the override value for this param.
minimum: -2090
maximum: 1590
qcom,hs-amplitude-bp:
description:
This adjusts the high-speed DC level voltage.
The hardware accepts only discrete values. The value closest to the
provided input will be chosen as the override value for this param.
minimum: -660
maximum: 2670
qcom,pre-emphasis-duration-bp:
description:
This signal controls the duration for which the
HS pre-emphasis current is sourced onto DP<#> or DM<#>.
The HS Transmitter pre-emphasis duration is defined in terms of
unit amounts. One unit of pre-emphasis duration is approximately
650 ps and is defined as 1X pre-emphasis duration.
The hardware accepts only discrete values. The value closest to the
provided input will be chosen as the override value for this param.
minimum: 10000
maximum: 20000
qcom,pre-emphasis-amplitude-bp:
description:
This signal controls the amount of current sourced to
DP<#> and DM<#> after a J-to-K or K-to-J transition.
The HS Transmitter pre-emphasis current is defined in terms of unit
amounts. One unit amount is approximately 2 mA and is defined as
1X pre-emphasis current.
The hardware accepts only discrete values. The value closest to the
provided input will be chosen as the override value for this param.
minimum: 10000
maximum: 40000
qcom,hs-rise-fall-time-bp:
description:
This adjusts the rise/fall times of the high-speed waveform.
The hardware accepts only discrete values. The value closest to the
provided input will be chosen as the override value for this param.
minimum: -4100
maximum: 5430
qcom,hs-crossover-voltage-microvolt:
description:
This adjusts the voltage at which the DP<#> and DM<#>
signals cross while transmitting in HS mode.
The hardware accepts only discrete values. The value closest to the
provided input will be chosen as the override value for this param.
minimum: -31000
maximum: 28000
qcom,hs-output-impedance-micro-ohms:
description:
In some applications, there can be significant series resistance
on the D+ and D- paths between the transceiver and cable. This adjusts
the driver source impedance to compensate for added series
resistance on the USB. The hardware accepts only discrete values. The
value closest to the provided input will be chosen as the override value
for this param.
minimum: -2300000
maximum: 6100000
qcom,ls-fs-output-impedance-bp:
description:
This adjusts the low- and full-speed single-ended source
impedance while driving high. The following adjustment values are based
on nominal process, voltage, and temperature.
The hardware accepts only discrete values. The value closest to the
provided input will be chosen as the override value for this param.
minimum: -1053
maximum: 1310
required:
- compatible
- reg

112
Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt
View File

@@ -1,112 +0,0 @@
* Renesas R-Car generation 2 USB PHY
This file provides information on what the device node for the R-Car generation
2 USB PHY contains.
Required properties:
- compatible: "renesas,usb-phy-r8a7742" if the device is a part of R8A7742 SoC.
"renesas,usb-phy-r8a7743" if the device is a part of R8A7743 SoC.
"renesas,usb-phy-r8a7744" if the device is a part of R8A7744 SoC.
"renesas,usb-phy-r8a7745" if the device is a part of R8A7745 SoC.
"renesas,usb-phy-r8a77470" if the device is a part of R8A77470 SoC.
"renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.
"renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC.
"renesas,usb-phy-r8a7794" if the device is a part of R8A7794 SoC.
"renesas,rcar-gen2-usb-phy" for a generic R-Car Gen2 or
RZ/G1 compatible device.
When compatible with the generic version, nodes must list the
SoC-specific version corresponding to the platform first
followed by the generic version.
- reg: offset and length of the register block.
- #address-cells: number of address cells for the USB channel subnodes, must
be <1>.
- #size-cells: number of size cells for the USB channel subnodes, must be <0>.
- clocks: clock phandle and specifier pair.
- clock-names: string, clock input name, must be "usbhs".
The USB PHY device tree node should have the subnodes corresponding to the USB
channels. These subnodes must contain the following properties:
- reg: the USB controller selector; see the table below for the values.
- #phy-cells: see phy-bindings.txt in the same directory, must be <1>.
The phandle's argument in the PHY specifier is the USB controller selector for
the USB channel other than r8a77470 SoC; see the selector meanings below:
+-----------+---------------+---------------+
|\ Selector | | |
+ --------- + 0 | 1 |
| Channel \| | |
+-----------+---------------+---------------+
| 0 | PCI EHCI/OHCI | HS-USB |
| 2 | PCI EHCI/OHCI | xHCI |
+-----------+---------------+---------------+
For r8a77470 SoC;see the selector meaning below:
+-----------+---------------+---------------+
|\ Selector | | |
+ --------- + 0 | 1 |
| Channel \| | |
+-----------+---------------+---------------+
| 0 | EHCI/OHCI | HS-USB |
+-----------+---------------+---------------+
Example (Lager board):
usb-phy@e6590100 {
compatible = "renesas,usb-phy-r8a7790", "renesas,rcar-gen2-usb-phy";
reg = <0 0xe6590100 0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cpg CPG_MOD 704>;
clock-names = "usbhs";
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 704>;
usb0: usb-channel@0 {
reg = <0>;
#phy-cells = <1>;
};
usb2: usb-channel@2 {
reg = <2>;
#phy-cells = <1>;
};
};
Example (iWave RZ/G1C sbc):
usbphy0: usb-phy0@e6590100 {
compatible = "renesas,usb-phy-r8a77470",
"renesas,rcar-gen2-usb-phy";
reg = <0 0xe6590100 0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cpg CPG_MOD 704>;
clock-names = "usbhs";
power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
resets = <&cpg 704>;
usb0: usb-channel@0 {
reg = <0>;
#phy-cells = <1>;
};
};
usbphy1: usb-phy@e6598100 {
compatible = "renesas,usb-phy-r8a77470",
"renesas,rcar-gen2-usb-phy";
reg = <0 0xe6598100 0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cpg CPG_MOD 706>;
clock-names = "usbhs";
power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
resets = <&cpg 706>;
usb1: usb-channel@0 {
reg = <0>;
#phy-cells = <1>;
};
};

123
Documentation/devicetree/bindings/phy/renesas,rcar-gen2-usb-phy.yaml Normal file
View File

@@ -0,0 +1,123 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/renesas,rcar-gen2-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas R-Car Gen2 USB PHY
maintainers:
- Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
properties:
compatible:
items:
- enum:
- renesas,usb-phy-r8a7742 # RZ/G1H
- renesas,usb-phy-r8a7743 # RZ/G1M
- renesas,usb-phy-r8a7744 # RZ/G1N
- renesas,usb-phy-r8a7745 # RZ/G1E
- renesas,usb-phy-r8a77470 # RZ/G1C
- renesas,usb-phy-r8a7790 # R-Car H2
- renesas,usb-phy-r8a7791 # R-Car M2-W
- renesas,usb-phy-r8a7794 # R-Car E2
- const: renesas,rcar-gen2-usb-phy # R-Car Gen2 or RZ/G1
reg:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
clocks:
maxItems: 1
clock-names:
items:
- const: usbhs
power-domains:
maxItems: 1
resets:
maxItems: 1
patternProperties:
"^usb-phy@[02]$":
type: object
description: Subnode corresponding to a USB channel.
properties:
reg:
description: FIXME RZ/G1C supports channel 0 only
enum: [0, 2]
'#phy-cells':
description: |
The phandle's argument in the PHY specifier is the USB controller
selector for the USB channel.
For RZ/G1C:
- 0 for EHCI/OHCI
- 1 for HS-USB
For all other SoCS:
- 0 for PCI EHCI/OHCI
- 1 for HS-USB (channel 0) or xHCI (channel 2)
const: 1
required:
- reg
- '#phy-cells'
additionalProperties: false
required:
- compatible
- reg
- '#address-cells'
- '#size-cells'
- clocks
- clock-names
- resets
- power-domains
- usb-phy@0
if:
properties:
compatible:
contains:
const: renesas,usb-phy-r8a77470
then:
properties:
usb-phy@2: false
else:
required:
- usb-phy@2
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
#include <dt-bindings/power/r8a7790-sysc.h>
usb-phy-controller@e6590100 {
compatible = "renesas,usb-phy-r8a7790", "renesas,rcar-gen2-usb-phy";
reg = <0xe6590100 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cpg CPG_MOD 704>;
clock-names = "usbhs";
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 704>;
usb0: usb-phy@0 {
reg = <0>;
#phy-cells = <1>;
};
usb2: usb-phy@2 {
reg = <2>;
#phy-cells = <1>;
};
};

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