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Merge tag 'media/v5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media

Browse Source 
Pull media updates from Mauro Carvalho Chehab:

 - a major reorg at platform Kconfig/Makefile files, organizing them per
   vendor. The other media Kconfig/Makefile files also sorted

 - New sensor drivers: hi847, isl7998x, ov08d10

 - New Amphion vpu decoder stateful driver

 - New Atmel microchip csi2dc driver

 - tegra-vde driver promoted from staging

 - atomisp: some fixes for it to work on BYT

 - imx7-mipi-csis driver promoted from staging and renamed

 - camss driver got initial support for VFE hardware version Titan 480

 - mtk-vcodec has gained support for MT8192

 - lots of driver changes, fixes and improvements

* tag 'media/v5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (417 commits)
  media: nxp: Restrict VIDEO_IMX_MIPI_CSIS to ARCH_MXC or COMPILE_TEST
  media: amphion: cleanup media device if register it fail
  media: amphion: fix some issues to improve robust
  media: amphion: fix some error related with undefined reference to __divdi3
  media: amphion: fix an issue that using pm_runtime_get_sync incorrectly
  media: vidtv: use vfree() for memory allocated with vzalloc()
  media: m5mols/m5mols.h: document new reset field
  media: pixfmt-yuv-planar.rst: fix PIX_FMT labels
  media: platform: Remove unnecessary print function dev_err()
  media: amphion: Add missing of_node_put() in vpu_core_parse_dt()
  media: mtk-vcodec: Add missing of_node_put() in mtk_vdec_hw_prob_done()
  media: platform: amphion: Fix build error without MAILBOX
  media: spi: Kconfig: Place SPI drivers on a single menu
  media: i2c: Kconfig: move camera drivers to the top
  media: atomisp: fix bad usage at error handling logic
  media: platform: rename mediatek/mtk-jpeg/ to mediatek/jpeg/
  media: media/*/Kconfig: sort entries
  media: Kconfig: cleanup VIDEO_DEV dependencies
  media: platform/*/Kconfig: make manufacturer menus more uniform
  media: platform: Create vendor/{Makefile,Kconfig} files
  ...
This commit is contained in:
Linus Torvalds
2022-03-23 14:51:35 -07:00
parent 9c4b86ebf5 ba2c670ae8
commit 182966e1cd
883 changed files with 34977 additions and 9130 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/admin-guide/media/fimc.rst
View File

@@ -14,7 +14,7 @@ data from LCD controller (FIMD) through the SoC internal writeback data
path. There are multiple FIMC instances in the SoCs (up to 4), having
slightly different capabilities, like pixel alignment constraints, rotator
availability, LCD writeback support, etc. The driver is located at
drivers/media/platform/exynos4-is directory.
drivers/media/platform/samsung/exynos4-is directory.
Supported SoCs
--------------

2
Documentation/admin-guide/media/i2c-cardlist.rst
View File

@@ -284,7 +284,7 @@ tda9887 TDA 9885/6/7 analog IF demodulator
tea5761 TEA 5761 radio tuner
tea5767 TEA 5767 radio tuner
tua9001 Infineon TUA9001 silicon tuner
tuner-xc2028 XCeive xc2028/xc3028 tuners
xc2028 XCeive xc2028/xc3028 tuners
xc4000 Xceive XC4000 silicon tuner
xc5000 Xceive XC5000 silicon tuner
============ ==================================================

2
Documentation/admin-guide/media/imx7.rst
View File

@@ -33,7 +33,7 @@ reference manual [#f1]_.
Entities
--------
imx7-mipi-csi2
imx-mipi-csi2
--------------
This is the MIPI CSI-2 receiver entity. It has one sink pad to receive the pixel

2
Documentation/admin-guide/media/omap3isp.rst
View File

@@ -17,7 +17,7 @@ Introduction
------------
This file documents the Texas Instruments OMAP 3 Image Signal Processor (ISP)
driver located under drivers/media/platform/omap3isp. The original driver was
driver located under drivers/media/platform/ti/omap3isp. The original driver was
written by Texas Instruments but since that it has been rewritten (twice) at
Nokia.

2
Documentation/admin-guide/media/omap4_camera.rst
View File

@@ -25,7 +25,7 @@ As of Revision AB, the ISS is described in detail in section 8.
This driver is supporting **only** the CSI2-A/B interfaces for now.
It makes use of the Media Controller framework [#f2]_, and inherited most of the
code from OMAP3 ISP driver (found under drivers/media/platform/omap3isp/\*),
code from OMAP3 ISP driver (found under drivers/media/platform/ti/omap3isp/\*),
except that it doesn't need an IOMMU now for ISS buffers memory mapping.
Supports usage of MMAP buffers only (for now).

13
Documentation/admin-guide/media/vimc.rst
View File

@@ -76,3 +76,16 @@ vimc-capture:
* 1 Pad sink
* 1 Pad source
Module options
--------------
Vimc has a module parameter to configure the driver.
* ``allocator=<unsigned int>``
memory allocator selection, default is 0. It specifies the way buffers
will be allocated.
- 0: vmalloc
- 1: dma-contig

9
Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
View File

@@ -61,8 +61,6 @@ Required properties (DMA function blocks):
"mediatek,<chip>-disp-rdma"
"mediatek,<chip>-disp-wdma"
the supported chips are mt2701, mt8167 and mt8173.
- larb: Should contain a phandle pointing to the local arbiter device as defined
in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
- iommus: Should point to the respective IOMMU block with master port as
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
for details.
@@ -91,7 +89,6 @@ ovl0: ovl@1400c000 {
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_OVL0>;
iommus = <&iommu M4U_PORT_DISP_OVL0>;
mediatek,larb = <&larb0>;
};
ovl1: ovl@1400d000 {
@@ -101,7 +98,6 @@ ovl1: ovl@1400d000 {
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_OVL1>;
iommus = <&iommu M4U_PORT_DISP_OVL1>;
mediatek,larb = <&larb4>;
};
rdma0: rdma@1400e000 {
@@ -111,7 +107,6 @@ rdma0: rdma@1400e000 {
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
mediatek,larb = <&larb0>;
mediatek,rdma-fifosize = <8192>;
};
@@ -122,7 +117,6 @@ rdma1: rdma@1400f000 {
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
iommus = <&iommu M4U_PORT_DISP_RDMA1>;
mediatek,larb = <&larb4>;
};
rdma2: rdma@14010000 {
@@ -132,7 +126,6 @@ rdma2: rdma@14010000 {
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA2>;
iommus = <&iommu M4U_PORT_DISP_RDMA2>;
mediatek,larb = <&larb4>;
};
wdma0: wdma@14011000 {
@@ -142,7 +135,6 @@ wdma0: wdma@14011000 {
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_WDMA0>;
iommus = <&iommu M4U_PORT_DISP_WDMA0>;
mediatek,larb = <&larb0>;
};
wdma1: wdma@14012000 {
@@ -152,7 +144,6 @@ wdma1: wdma@14012000 {
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_WDMA1>;
iommus = <&iommu M4U_PORT_DISP_WDMA1>;
mediatek,larb = <&larb4>;
};
color0: color@14013000 {

180
Documentation/devicetree/bindings/media/amphion,vpu.yaml Normal file
View File

@@ -0,0 +1,180 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/amphion,vpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amphion VPU codec IP
maintainers:
- Ming Qian <ming.qian@nxp.com>
- Shijie Qin <shijie.qin@nxp.com>
description: |-
The Amphion MXC video encoder(Windsor) and decoder(Malone) accelerators present
on NXP i.MX8Q SoCs.
properties:
$nodename:
pattern: "^vpu@[0-9a-f]+$"
compatible:
items:
- enum:
- nxp,imx8qm-vpu
- nxp,imx8qxp-vpu
reg:
maxItems: 1
power-domains:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
patternProperties:
"^mailbox@[0-9a-f]+$":
description:
Each vpu encoder or decoder correspond a MU, which used for communication
between driver and firmware. Implement via mailbox on driver.
$ref: ../mailbox/fsl,mu.yaml#
"^vpu_core@[0-9a-f]+$":
description:
Each core correspond a decoder or encoder, need to configure them
separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC
has one decoder and one encoder.
type: object
properties:
compatible:
items:
- enum:
- nxp,imx8q-vpu-decoder
- nxp,imx8q-vpu-encoder
reg:
maxItems: 1
power-domains:
maxItems: 1
mbox-names:
items:
- const: tx0
- const: tx1
- const: rx
mboxes:
description:
List of phandle of 2 MU channels for tx, 1 MU channel for rx.
maxItems: 3
memory-region:
description:
Phandle to the reserved memory nodes to be associated with the
remoteproc device. The reserved memory nodes should be carveout nodes,
and should be defined as per the bindings in
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
items:
- description: region reserved for firmware image sections.
- description: region used for RPC shared memory between firmware and
driver.
required:
- compatible
- reg
- power-domains
- mbox-names
- mboxes
- memory-region
additionalProperties: false
required:
- compatible
- reg
- power-domains
additionalProperties: false
examples:
# Device node example for i.MX8QM platform:
- |
#include <dt-bindings/firmware/imx/rsrc.h>
vpu: vpu@2c000000 {
compatible = "nxp,imx8qm-vpu";
ranges = <0x2c000000 0x2c000000 0x2000000>;
reg = <0x2c000000 0x1000000>;
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&pd IMX_SC_R_VPU>;
mu_m0: mailbox@2d000000 {
compatible = "fsl,imx6sx-mu";
reg = <0x2d000000 0x20000>;
interrupts = <0 472 4>;
#mbox-cells = <2>;
power-domains = <&pd IMX_SC_R_VPU_MU_0>;
};
mu1_m0: mailbox@2d020000 {
compatible = "fsl,imx6sx-mu";
reg = <0x2d020000 0x20000>;
interrupts = <0 473 4>;
#mbox-cells = <2>;
power-domains = <&pd IMX_SC_R_VPU_MU_1>;
};
mu2_m0: mailbox@2d040000 {
compatible = "fsl,imx6sx-mu";
reg = <0x2d040000 0x20000>;
interrupts = <0 474 4>;
#mbox-cells = <2>;
power-domains = <&pd IMX_SC_R_VPU_MU_2>;
};
vpu_core0: vpu_core@2d080000 {
compatible = "nxp,imx8q-vpu-decoder";
reg = <0x2d080000 0x10000>;
power-domains = <&pd IMX_SC_R_VPU_DEC_0>;
mbox-names = "tx0", "tx1", "rx";
mboxes = <&mu_m0 0 0>,
<&mu_m0 0 1>,
<&mu_m0 1 0>;
memory-region = <&decoder_boot>, <&decoder_rpc>;
};
vpu_core1: vpu_core@2d090000 {
compatible = "nxp,imx8q-vpu-encoder";
reg = <0x2d090000 0x10000>;
power-domains = <&pd IMX_SC_R_VPU_ENC_0>;
mbox-names = "tx0", "tx1", "rx";
mboxes = <&mu1_m0 0 0>,
<&mu1_m0 0 1>,
<&mu1_m0 1 0>;
memory-region = <&encoder1_boot>, <&encoder1_rpc>;
};
vpu_core2: vpu_core@2d0a0000 {
reg = <0x2d0a0000 0x10000>;
compatible = "nxp,imx8q-vpu-encoder";
power-domains = <&pd IMX_SC_R_VPU_ENC_1>;
mbox-names = "tx0", "tx1", "rx";
mboxes = <&mu2_m0 0 0>,
<&mu2_m0 0 1>,
<&mu2_m0 1 0>;
memory-region = <&encoder2_boot>, <&encoder2_rpc>;
};
};
...

6
Documentation/devicetree/bindings/media/i2c/hynix,hi846.yaml
View File

@@ -49,7 +49,8 @@ properties:
description: Definition of the regulator used for the VDDD power supply.
port:
$ref: /schemas/graph.yaml#/properties/port
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
properties:
endpoint:
@@ -68,8 +69,11 @@ properties:
- const: 1
- const: 2
link-frequencies: true
required:
- data-lanes
- link-frequencies
required:
- compatible

113
Documentation/devicetree/bindings/media/i2c/isil,isl79987.yaml Normal file
View File

@@ -0,0 +1,113 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/isil,isl79987.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intersil ISL79987 Analog to MIPI CSI-2 decoder
maintainers:
- Michael Tretter <m.tretter@pengutronix.de>
- Marek Vasut <marex@denx.de>
description:
The Intersil ISL79987 is an analog to MIPI CSI-2 decoder which is capable of
receiving up to four analog stream and multiplexing them into up to four MIPI
CSI-2 virtual channels, using one MIPI clock lane and 1/2 data lanes.
properties:
compatible:
enum:
- isil,isl79987
reg:
maxItems: 1
reset-gpios:
maxItems: 1
description:
A GPIO spec for the RSTB pin (active high)
powerdown-gpios:
maxItems: 1
description:
A GPIO spec for the Power Down pin (active high)
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: Output port
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
minItems: 1
maxItems: 2
required:
- data-lanes
patternProperties:
"^port@[1-4]$":
$ref: /schemas/graph.yaml#/properties/port
description: Input ports
required:
- port@0
additionalProperties: false
required:
- compatible
- reg
- ports
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
isl7998x_mipi@44 {
compatible = "isil,isl79987";
reg = <0x44>;
powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
isl79987_out: endpoint {
remote-endpoint = <&mipi_csi2_in>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
endpoint {
remote-endpoint = <&camera_0>;
};
};
port@2 {
reg = <2>;
endpoint {
remote-endpoint = <&camera_1>;
};
};
};
};
};

297
Documentation/devicetree/bindings/media/i2c/maxim,max9286.yaml
View File

@@ -70,6 +70,28 @@ properties:
a remote serializer whose high-threshold noise immunity is not enabled
is 100000 micro volts
maxim,gpio-poc:
$ref: '/schemas/types.yaml#/definitions/uint32-array'
minItems: 2
maxItems: 2
description: |
Index of the MAX9286 gpio output line (0 or 1) that controls Power over
Coax to the cameras and its associated polarity flag.
The property accepts an array of two unsigned integers, the first being
the gpio line index (0 or 1) and the second being the gpio line polarity
flag (GPIO_ACTIVE_HIGH or GPIO_ACTIVE_LOW) as defined in
<include/dt-bindings/gpio/gpio.h>.
When the remote cameras power is controlled by one of the MAX9286 gpio
lines, this property has to be used to specify which line among the two
available ones controls the remote camera power enablement.
When this property is used it is not possible to register a gpio
controller as the gpio lines are controlled directly by the MAX9286 and
not available for consumers, nor the 'poc-supply' property should be
specified.
ports:
$ref: /schemas/graph.yaml#/properties/ports
@@ -165,7 +187,16 @@ required:
- reg
- ports
- i2c-mux
- gpio-controller
# If 'maxim,gpio-poc' is present, then 'poc-supply' and 'gpio-controller'
# are not allowed.
if:
required:
- maxim,gpio-poc
then:
properties:
poc-supply: false
gpio-controller: false
additionalProperties: false
@@ -174,140 +205,174 @@ examples:
#include <dt-bindings/gpio/gpio.h>
i2c@e66d8000 {
#address-cells = <1>;
#size-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0xe66d8000>;
reg = <0 0xe66d8000>;
gmsl-deserializer@2c {
compatible = "maxim,max9286";
reg = <0x2c>;
poc-supply = <&camera_poc_12v>;
enable-gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
gmsl-deserializer@2c {
compatible = "maxim,max9286";
reg = <0x2c>;
poc-supply = <&camera_poc_12v>;
enable-gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
maxim,reverse-channel-microvolt = <170000>;
maxim,reverse-channel-microvolt = <170000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
port@0 {
reg = <0>;
max9286_in0: endpoint {
remote-endpoint = <&rdacm20_out0>;
max9286_in0: endpoint {
remote-endpoint = <&rdacm20_out0>;
};
};
port@1 {
reg = <1>;
max9286_in1: endpoint {
remote-endpoint = <&rdacm20_out1>;
};
};
port@2 {
reg = <2>;
max9286_in2: endpoint {
remote-endpoint = <&rdacm20_out2>;
};
};
port@3 {
reg = <3>;
max9286_in3: endpoint {
remote-endpoint = <&rdacm20_out3>;
};
};
port@4 {
reg = <4>;
max9286_out: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi40_in>;
};
};
};
};
port@1 {
reg = <1>;
i2c-mux {
#address-cells = <1>;
#size-cells = <0>;
max9286_in1: endpoint {
remote-endpoint = <&rdacm20_out1>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
camera@51 {
compatible = "imi,rdacm20";
reg = <0x51>, <0x61>;
port {
rdacm20_out0: endpoint {
remote-endpoint = <&max9286_in0>;
};
};
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
camera@52 {
compatible = "imi,rdacm20";
reg = <0x52>, <0x62>;
port {
rdacm20_out1: endpoint {
remote-endpoint = <&max9286_in1>;
};
};
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
camera@53 {
compatible = "imi,rdacm20";
reg = <0x53>, <0x63>;
port {
rdacm20_out2: endpoint {
remote-endpoint = <&max9286_in2>;
};
};
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
camera@54 {
compatible = "imi,rdacm20";
reg = <0x54>, <0x64>;
port {
rdacm20_out3: endpoint {
remote-endpoint = <&max9286_in3>;
};
};
};
};
};
};
port@2 {
reg = <2>;
max9286_in2: endpoint {
remote-endpoint = <&rdacm20_out2>;
};
};
port@3 {
reg = <3>;
max9286_in3: endpoint {
remote-endpoint = <&rdacm20_out3>;
};
};
port@4 {
reg = <4>;
max9286_out: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi40_in>;
};
};
};
i2c-mux {
#address-cells = <1>;
#size-cells = <0>;
/*
* Example of a deserializer that controls the camera Power over Coax
* through one of its gpio lines.
*/
gmsl-deserializer@6c {
compatible = "maxim,max9286";
reg = <0x6c>;
enable-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
/*
* The remote camera power is controlled by MAX9286 GPIO line #0.
* No 'poc-supply' nor 'gpio-controller' are specified.
*/
maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
camera@51 {
compatible = "imi,rdacm20";
reg = <0x51>, <0x61>;
/*
* Do not describe connections as they're the same as in the previous
* example.
*/
ports {
#address-cells = <1>;
#size-cells = <0>;
port {
rdacm20_out0: endpoint {
remote-endpoint = <&max9286_in0>;
port@4 {
reg = <4>;
};
};
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
camera@52 {
compatible = "imi,rdacm20";
reg = <0x52>, <0x62>;
port {
rdacm20_out1: endpoint {
remote-endpoint = <&max9286_in1>;
};
};
i2c-mux {
#address-cells = <1>;
#size-cells = <0>;
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
camera@53 {
compatible = "imi,rdacm20";
reg = <0x53>, <0x63>;
port {
rdacm20_out2: endpoint {
remote-endpoint = <&max9286_in2>;
};
};
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
camera@54 {
compatible = "imi,rdacm20";
reg = <0x54>, <0x64>;
port {
rdacm20_out3: endpoint {
remote-endpoint = <&max9286_in3>;
};
};
};
};
};
};
};

169
Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml Normal file
View File

@@ -0,0 +1,169 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,vcodec-decoder.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek Video Decode Accelerator
maintainers:
- Yunfei Dong <yunfei.dong@mediatek.com>
description: |+
Mediatek Video Decode is the video decode hardware present in Mediatek
SoCs which supports high resolution decoding functionalities.
properties:
compatible:
enum:
- mediatek,mt8173-vcodec-dec
- mediatek,mt8183-vcodec-dec
reg:
maxItems: 12
interrupts:
maxItems: 1
clocks:
maxItems: 8
clock-names:
items:
- const: vcodecpll
- const: univpll_d2
- const: clk_cci400_sel
- const: vdec_sel
- const: vdecpll
- const: vencpll
- const: venc_lt_sel
- const: vdec_bus_clk_src
assigned-clocks: true
assigned-clock-parents: true
assigned-clock-rates: true
power-domains:
maxItems: 1
iommus:
minItems: 1
maxItems: 32
description: |
List of the hardware port in respective IOMMU block for current Socs.
Refer to bindings/iommu/mediatek,iommu.yaml.
dma-ranges:
maxItems: 1
description: |
Describes the physical address space of IOMMU maps to memory.
mediatek,vpu:
$ref: /schemas/types.yaml#/definitions/phandle
maxItems: 1
description:
Describes point to vpu.
mediatek,scp:
$ref: /schemas/types.yaml#/definitions/phandle
maxItems: 1
description:
Describes point to scp.
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- iommus
- assigned-clocks
- assigned-clock-parents
allOf:
- if:
properties:
compatible:
contains:
enum:
- mediatek,mt8183-vcodec-dec
then:
required:
- mediatek,scp
- if:
properties:
compatible:
contains:
enum:
- mediatek,mt8173-vcodec-dec
then:
required:
- mediatek,vpu
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/memory/mt8173-larb-port.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mt8173-power.h>
vcodec_dec: vcodec@16000000 {
compatible = "mediatek,mt8173-vcodec-dec";
reg = <0x16000000 0x100>, /*VDEC_SYS*/
<0x16020000 0x1000>, /*VDEC_MISC*/
<0x16021000 0x800>, /*VDEC_LD*/
<0x16021800 0x800>, /*VDEC_TOP*/
<0x16022000 0x1000>, /*VDEC_CM*/
<0x16023000 0x1000>, /*VDEC_AD*/
<0x16024000 0x1000>, /*VDEC_AV*/
<0x16025000 0x1000>, /*VDEC_PP*/
<0x16026800 0x800>, /*VP8_VD*/
<0x16027000 0x800>, /*VP6_VD*/
<0x16027800 0x800>, /*VP8_VL*/
<0x16028400 0x400>; /*VP9_VD*/
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
<&iommu M4U_PORT_HW_VDEC_PP_EXT>,
<&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
<&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
<&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
<&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
<&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
<&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
mediatek,vpu = <&vpu>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
<&topckgen CLK_TOP_UNIVPLL_D2>,
<&topckgen CLK_TOP_CCI400_SEL>,
<&topckgen CLK_TOP_VDEC_SEL>,
<&topckgen CLK_TOP_VCODECPLL>,
<&apmixedsys CLK_APMIXED_VENCPLL>,
<&topckgen CLK_TOP_VENC_LT_SEL>,
<&topckgen CLK_TOP_VCODECPLL_370P5>;
clock-names = "vcodecpll",
"univpll_d2",
"clk_cci400_sel",
"vdec_sel",
"vdecpll",
"vencpll",
"venc_lt_sel",
"vdec_bus_clk_src";
assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
<&topckgen CLK_TOP_CCI400_SEL>,
<&topckgen CLK_TOP_VDEC_SEL>,
<&apmixedsys CLK_APMIXED_VCODECPLL>,
<&apmixedsys CLK_APMIXED_VENCPLL>;
assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
<&topckgen CLK_TOP_UNIVPLL_D2>,
<&topckgen CLK_TOP_VCODECPLL>;
assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,vcodec-encoder.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek Video Encode Accelerator
maintainers:
- Yunfei Dong <yunfei.dong@mediatek.com>
description: |+
Mediatek Video Encode is the video encode hardware present in Mediatek
SoCs which supports high resolution encoding functionalities.
properties:
compatible:
enum:
- mediatek,mt8173-vcodec-enc-vp8
- mediatek,mt8173-vcodec-enc
- mediatek,mt8183-vcodec-enc
- mediatek,mt8192-vcodec-enc
- mediatek,mt8195-vcodec-enc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 1
maxItems: 5
clock-names:
minItems: 1
maxItems: 5
assigned-clocks: true
assigned-clock-parents: true
iommus:
minItems: 1
maxItems: 32
description: |
List of the hardware port in respective IOMMU block for current Socs.
Refer to bindings/iommu/mediatek,iommu.yaml.
dma-ranges:
maxItems: 1
description: |
Describes the physical address space of IOMMU maps to memory.
mediatek,vpu:
$ref: /schemas/types.yaml#/definitions/phandle
maxItems: 1
description:
Describes point to vpu.
mediatek,scp:
$ref: /schemas/types.yaml#/definitions/phandle
maxItems: 1
description:
Describes point to scp.
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- iommus
- assigned-clocks
- assigned-clock-parents
allOf:
- if:
properties:
compatible:
contains:
enum:
- mediatek,mt8183-vcodec-enc
- mediatek,mt8192-vcodec-enc
then:
required:
- mediatek,scp
- if:
properties:
compatible:
contains:
enum:
- mediatek,mt8173-vcodec-enc-vp8
- mediatek,mt8173-vcodec-enc
then:
required:
- mediatek,vpu
- if:
properties:
compatible:
enum:
- mediatek,mt8173-vcodec-enc
- mediatek,mt8192-vcodec-enc
- mediatek,mt8173-vcodec-enc
then:
properties:
clock:
items:
minItems: 1
maxItems: 1
clock-names:
items:
- const: venc_sel
else: # for vp8 hw decoder
properties:
clock:
items:
minItems: 1
maxItems: 1
clock-names:
items:
- const: venc_lt_sel
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/memory/mt8173-larb-port.h>
#include <dt-bindings/interrupt-controller/irq.h>
vcodec_enc_avc: vcodec@18002000 {
compatible = "mediatek,mt8173-vcodec-enc";
reg = <0x18002000 0x1000>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
iommus = <&iommu M4U_PORT_VENC_RCPU>,
<&iommu M4U_PORT_VENC_REC>,
<&iommu M4U_PORT_VENC_BSDMA>,
<&iommu M4U_PORT_VENC_SV_COMV>,
<&iommu M4U_PORT_VENC_RD_COMV>,
<&iommu M4U_PORT_VENC_CUR_LUMA>,
<&iommu M4U_PORT_VENC_CUR_CHROMA>,
<&iommu M4U_PORT_VENC_REF_LUMA>,
<&iommu M4U_PORT_VENC_REF_CHROMA>,
<&iommu M4U_PORT_VENC_NBM_RDMA>,
<&iommu M4U_PORT_VENC_NBM_WDMA>;
mediatek,vpu = <&vpu>;
clocks = <&topckgen CLK_TOP_VENC_SEL>;
clock-names = "venc_sel";
assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
};
vcodec_enc_vp8: vcodec@19002000 {
compatible = "mediatek,mt8173-vcodec-enc-vp8";
reg = <0x19002000 0x1000>; /* VENC_LT_SYS */
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
<&iommu M4U_PORT_VENC_REC_FRM_SET2>,
<&iommu M4U_PORT_VENC_BSDMA_SET2>,
<&iommu M4U_PORT_VENC_SV_COMA_SET2>,
<&iommu M4U_PORT_VENC_RD_COMA_SET2>,
<&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
<&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
<&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
<&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
mediatek,vpu = <&vpu>;
clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
clock-names = "venc_lt_sel";
assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Mediatek Video Decode Accelerator With Multi Hardware
maintainers:
- Yunfei Dong <yunfei.dong@mediatek.com>
description: |
Mediatek Video Decode is the video decode hardware present in Mediatek
SoCs which supports high resolution decoding functionalities. Required
parent and child device node.
About the Decoder Hardware Block Diagram, please check below:
+---------------------------------+------------------------------------+
| | |
| input -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output |
| || | || |
+------------||-------------------+---------------------||-------------+
lat workqueue | core workqueue <parent>
-------------||-----------------------------------------||------------------
|| || <child>
\/ <----------------HW index-------------->\/
+------------------------------------------------------+
| enable/disable |
| clk power irq iommu |
| (lat/lat soc/core0/core1) |
+------------------------------------------------------+
As above, there are parent and child devices, child mean each hardware. The child device
controls the information of each hardware independent which include clk/power/irq.
There are two workqueues in parent device: lat workqueue and core workqueue. They are used
to lat and core hardware deocder. Lat workqueue need to get input bitstream and lat buffer,
then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode
done. Core workqueue need to get lat buffer and output buffer, then enable core to decode,
writing the result to output buffer, disable hardware when core decode done. These two
hardwares will decode each frame cyclically.
For the smi common may not the same for each hardware, can't combine all hardware in one node,
or leading to iommu fault when access dram data.
properties:
compatible:
const: mediatek,mt8192-vcodec-dec
reg:
maxItems: 1
iommus:
minItems: 1
maxItems: 32
description: |
List of the hardware port in respective IOMMU block for current Socs.
Refer to bindings/iommu/mediatek,iommu.yaml.
mediatek,scp:
$ref: /schemas/types.yaml#/definitions/phandle
maxItems: 1
description: |
The node of system control processor (SCP), using
the remoteproc & rpmsg framework.
dma-ranges:
maxItems: 1
description: |
Describes the physical address space of IOMMU maps to memory.
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
# Required child node:
patternProperties:
'^vcodec-lat@[0-9a-f]+$':
type: object
properties:
compatible:
const: mediatek,mtk-vcodec-lat
reg:
maxItems: 1
interrupts:
maxItems: 1
iommus:
minItems: 1
maxItems: 32
description: |
List of the hardware port in respective IOMMU block for current Socs.
Refer to bindings/iommu/mediatek,iommu.yaml.
clocks:
maxItems: 5
clock-names:
items:
- const: sel
- const: soc-vdec
- const: soc-lat
- const: vdec
- const: top
assigned-clocks:
maxItems: 1
assigned-clock-parents:
maxItems: 1
power-domains:
maxItems: 1
required:
- compatible
- reg
- interrupts
- iommus
- clocks
- clock-names
- assigned-clocks
- assigned-clock-parents
- power-domains
additionalProperties: false
'^vcodec-core@[0-9a-f]+$':
type: object
properties:
compatible:
const: mediatek,mtk-vcodec-core
reg:
maxItems: 1
interrupts:
maxItems: 1
iommus:
minItems: 1
maxItems: 32
description: |
List of the hardware port in respective IOMMU block for current Socs.
Refer to bindings/iommu/mediatek,iommu.yaml.
clocks:
maxItems: 5
clock-names:
items:
- const: sel
- const: soc-vdec
- const: soc-lat
- const: vdec
- const: top
assigned-clocks:
maxItems: 1
assigned-clock-parents:
maxItems: 1
power-domains:
maxItems: 1
required:
- compatible
- reg
- interrupts
- iommus
- clocks
- clock-names
- assigned-clocks
- assigned-clock-parents
- power-domains
additionalProperties: false
required:
- compatible
- reg
- iommus
- mediatek,scp
- dma-ranges
- ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/mt8192-larb-port.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/mt8192-clk.h>
#include <dt-bindings/power/mt8192-power.h>
video-codec@16000000 {
compatible = "mediatek,mt8192-vcodec-dec";
mediatek,scp = <&scp>;
iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x16000000 0x40000>;
reg = <0x16000000 0x1000>; /* VDEC_SYS */
vcodec-lat@10000 {
compatible = "mediatek,mtk-vcodec-lat";
reg = <0x10000 0x800>;
interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
clocks = <&topckgen CLK_TOP_VDEC_SEL>,
<&vdecsys_soc CLK_VDEC_SOC_VDEC>,
<&vdecsys_soc CLK_VDEC_SOC_LAT>,
<&vdecsys_soc CLK_VDEC_SOC_LARB1>,
<&topckgen CLK_TOP_MAINPLL_D4>;
clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
};
vcodec-core@25000 {
compatible = "mediatek,mtk-vcodec-core";
reg = <0x25000 0x1000>;
interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
clocks = <&topckgen CLK_TOP_VDEC_SEL>,
<&vdecsys CLK_VDEC_VDEC>,
<&vdecsys CLK_VDEC_LAT>,
<&vdecsys CLK_VDEC_LARB1>,
<&topckgen CLK_TOP_MAINPLL_D4>;
clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
};
};

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* Mediatek JPEG Decoder
Mediatek JPEG Decoder is the JPEG decode hardware present in Mediatek SoCs
Required properties:
- compatible : must be one of the following string:
"mediatek,mt8173-jpgdec"
"mediatek,mt7623-jpgdec", "mediatek,mt2701-jpgdec"
"mediatek,mt2701-jpgdec"
- reg : physical base address of the jpeg decoder registers and length of
memory mapped region.
- interrupts : interrupt number to the interrupt controller.
- clocks: device clocks, see
Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
- clock-names: must contain "jpgdec-smi" and "jpgdec".
- power-domains: a phandle to the power domain, see
Documentation/devicetree/bindings/power/power_domain.txt for details.
- mediatek,larb: must contain the local arbiters in the current Socs, see
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
for details.
- iommus: should point to the respective IOMMU block with master port as
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
for details.
Example:
jpegdec: jpegdec@15004000 {
compatible = "mediatek,mt2701-jpgdec";
reg = <0 0x15004000 0 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
<&imgsys CLK_IMG_JPGDEC>;
clock-names = "jpgdec-smi",
"jpgdec";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
mediatek,larb = <&larb2>;
iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek-jpeg-decoder.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek JPEG Decoder Device Tree Bindings
maintainers:
- Xia Jiang <xia.jiang@mediatek.com>
description: |-
Mediatek JPEG Decoder is the JPEG decode hardware present in Mediatek SoCs
properties:
compatible:
oneOf:
- items:
- enum:
- mediatek,mt8173-jpgdec
- mediatek,mt2701-jpgdec
- items:
- enum:
- mediatek,mt7623-jpgdec
- const: mediatek,mt2701-jpgdec
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 2
minItems: 2
clock-names:
items:
- const: jpgdec-smi
- const: jpgdec
power-domains:
maxItems: 1
iommus:
maxItems: 2
description: |
Points to the respective IOMMU block with master port as argument, see
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
Ports are according to the HW.
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- power-domains
- iommus
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt2701-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/mt2701-larb-port.h>
#include <dt-bindings/power/mt2701-power.h>
jpegdec: jpegdec@15004000 {
compatible = "mediatek,mt2701-jpgdec";
reg = <0x15004000 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
<&imgsys CLK_IMG_JPGDEC>;
clock-names = "jpgdec-smi",
"jpgdec";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
};

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* MediaTek JPEG Encoder
MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs
Required properties:
- compatible : "mediatek,mt2701-jpgenc"
followed by "mediatek,mtk-jpgenc"
- reg : physical base address of the JPEG encoder registers and length of
memory mapped region.
- interrupts : interrupt number to the interrupt controller.
- clocks: device clocks, see
Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
- clock-names: must contain "jpgenc". It is the clock of JPEG encoder.
- power-domains: a phandle to the power domain, see
Documentation/devicetree/bindings/power/power_domain.txt for details.
- mediatek,larb: must contain the local arbiters in the current SoCs, see
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
for details.
- iommus: should point to the respective IOMMU block with master port as
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
for details.
Example:
jpegenc: jpegenc@1500a000 {
compatible = "mediatek,mt2701-jpgenc",
"mediatek,mtk-jpgenc";
reg = <0 0x1500a000 0 0x1000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
clocks = <&imgsys CLK_IMG_VENC>;
clock-names = "jpgenc";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
mediatek,larb = <&larb2>;
iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
<&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek-jpeg-encoder.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek JPEG Encoder Device Tree Bindings
maintainers:
- Xia Jiang <xia.jiang@mediatek.com>
description: |-
MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs
properties:
compatible:
items:
- enum:
- mediatek,mt2701-jpgenc
- mediatek,mt8183-jpgenc
- const: mediatek,mtk-jpgenc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: jpgenc
power-domains:
maxItems: 1
iommus:
maxItems: 2
description: |
Points to the respective IOMMU block with master port as argument, see
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
Ports are according to the HW.
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- power-domains
- iommus
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt2701-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/mt2701-larb-port.h>
#include <dt-bindings/power/mt2701-power.h>
jpegenc: jpegenc@1500a000 {
compatible = "mediatek,mt2701-jpgenc",
"mediatek,mtk-jpgenc";
reg = <0x1500a000 0x1000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
clocks = <&imgsys CLK_IMG_VENC>;
clock-names = "jpgenc";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
<&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;
};

8
Documentation/devicetree/bindings/media/mediatek-mdp.txt
View File

@@ -27,9 +27,6 @@ Required properties (DMA function blocks, child node):
- iommus: should point to the respective IOMMU block with master port as
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
for details.
- mediatek,larb: must contain the local arbiters in the current Socs, see
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
for details.
Example:
mdp_rdma0: rdma@14001000 {
@@ -40,7 +37,6 @@ Example:
<&mmsys CLK_MM_MUTEX_32K>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_RDMA0>;
mediatek,larb = <&larb0>;
mediatek,vpu = <&vpu>;
};
@@ -51,7 +47,6 @@ Example:
<&mmsys CLK_MM_MUTEX_32K>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_RDMA1>;
mediatek,larb = <&larb4>;
};
mdp_rsz0: rsz@14003000 {
@@ -81,7 +76,6 @@ Example:
clocks = <&mmsys CLK_MM_MDP_WDMA>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_WDMA>;
mediatek,larb = <&larb0>;
};
mdp_wrot0: wrot@14007000 {
@@ -90,7 +84,6 @@ Example:
clocks = <&mmsys CLK_MM_MDP_WROT0>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_WROT0>;
mediatek,larb = <&larb0>;
};
mdp_wrot1: wrot@14008000 {
@@ -99,5 +92,4 @@ Example:
clocks = <&mmsys CLK_MM_MDP_WROT1>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_WROT1>;
mediatek,larb = <&larb4>;
};

131
Documentation/devicetree/bindings/media/mediatek-vcodec.txt
View File

@@ -1,131 +0,0 @@
Mediatek Video Codec
Mediatek Video Codec is the video codec hw present in Mediatek SoCs which
supports high resolution encoding and decoding functionalities.
Required properties:
- compatible : must be one of the following string:
"mediatek,mt8173-vcodec-enc-vp8" for mt8173 vp8 encoder.
"mediatek,mt8173-vcodec-enc" for mt8173 avc encoder.
"mediatek,mt8183-vcodec-enc" for MT8183 encoder.
"mediatek,mt8173-vcodec-dec" for MT8173 decoder.
"mediatek,mt8192-vcodec-enc" for MT8192 encoder.
"mediatek,mt8183-vcodec-dec" for MT8183 decoder.
"mediatek,mt8195-vcodec-enc" for MT8195 encoder.
- reg : Physical base address of the video codec registers and length of
memory mapped region.
- interrupts : interrupt number to the cpu.
- mediatek,larb : must contain the local arbiters in the current Socs.
- clocks : list of clock specifiers, corresponding to entries in
the clock-names property.
- clock-names: avc encoder must contain "venc_sel", vp8 encoder must
contain "venc_lt_sel", decoder must contain "vcodecpll", "univpll_d2",
"clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll", "venc_lt_sel",
"vdec_bus_clk_src".
- iommus : should point to the respective IOMMU block with master port as
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
for details.
- dma-ranges : describes the dma address range space that the codec hw access.
One of the two following nodes:
- mediatek,vpu : the node of the video processor unit, if using VPU.
- mediatek,scp : the node of the SCP unit, if using SCP.
Example:
vcodec_dec: vcodec@16000000 {
compatible = "mediatek,mt8173-vcodec-dec";
reg = <0 0x16000000 0 0x100>, /*VDEC_SYS*/
<0 0x16020000 0 0x1000>, /*VDEC_MISC*/
<0 0x16021000 0 0x800>, /*VDEC_LD*/
<0 0x16021800 0 0x800>, /*VDEC_TOP*/
<0 0x16022000 0 0x1000>, /*VDEC_CM*/
<0 0x16023000 0 0x1000>, /*VDEC_AD*/
<0 0x16024000 0 0x1000>, /*VDEC_AV*/
<0 0x16025000 0 0x1000>, /*VDEC_PP*/
<0 0x16026800 0 0x800>, /*VP8_VD*/
<0 0x16027000 0 0x800>, /*VP6_VD*/
<0 0x16027800 0 0x800>, /*VP8_VL*/
<0 0x16028400 0 0x400>; /*VP9_VD*/
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
mediatek,larb = <&larb1>;
iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
<&iommu M4U_PORT_HW_VDEC_PP_EXT>,
<&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
<&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
<&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
<&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
<&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
<&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
mediatek,vpu = <&vpu>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
<&topckgen CLK_TOP_UNIVPLL_D2>,
<&topckgen CLK_TOP_CCI400_SEL>,
<&topckgen CLK_TOP_VDEC_SEL>,
<&topckgen CLK_TOP_VCODECPLL>,
<&apmixedsys CLK_APMIXED_VENCPLL>,
<&topckgen CLK_TOP_VENC_LT_SEL>,
<&topckgen CLK_TOP_VCODECPLL_370P5>;
clock-names = "vcodecpll",
"univpll_d2",
"clk_cci400_sel",
"vdec_sel",
"vdecpll",
"vencpll",
"venc_lt_sel",
"vdec_bus_clk_src";
assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
<&topckgen CLK_TOP_CCI400_SEL>,
<&topckgen CLK_TOP_VDEC_SEL>,
<&apmixedsys CLK_APMIXED_VCODECPLL>,
<&apmixedsys CLK_APMIXED_VENCPLL>;
assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
<&topckgen CLK_TOP_UNIVPLL_D2>,
<&topckgen CLK_TOP_VCODECPLL>;
assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
};
vcodec_enc_avc: vcodec@18002000 {
compatible = "mediatek,mt8173-vcodec-enc";
reg = <0 0x18002000 0 0x1000>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
iommus = <&iommu M4U_PORT_VENC_RCPU>,
<&iommu M4U_PORT_VENC_REC>,
<&iommu M4U_PORT_VENC_BSDMA>,
<&iommu M4U_PORT_VENC_SV_COMV>,
<&iommu M4U_PORT_VENC_RD_COMV>,
<&iommu M4U_PORT_VENC_CUR_LUMA>,
<&iommu M4U_PORT_VENC_CUR_CHROMA>,
<&iommu M4U_PORT_VENC_REF_LUMA>,
<&iommu M4U_PORT_VENC_REF_CHROMA>,
<&iommu M4U_PORT_VENC_NBM_RDMA>,
<&iommu M4U_PORT_VENC_NBM_WDMA>;
mediatek,larb = <&larb3>;
mediatek,vpu = <&vpu>;
clocks = <&topckgen CLK_TOP_VENC_SEL>;
clock-names = "venc_sel";
assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
};
vcodec_enc_vp8: vcodec@19002000 {
compatible = "mediatek,mt8173-vcodec-enc-vp8";
reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
<&iommu M4U_PORT_VENC_REC_FRM_SET2>,
<&iommu M4U_PORT_VENC_BSDMA_SET2>,
<&iommu M4U_PORT_VENC_SV_COMA_SET2>,
<&iommu M4U_PORT_VENC_RD_COMA_SET2>,
<&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
<&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
<&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
<&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
mediatek,larb = <&larb5>;
mediatek,vpu = <&vpu>;
clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
clock-names = "venc_lt_sel";
assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
};

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