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Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and 'clk-rockchip' into clk-next

Browse Source 
- Add Versa3 clk generator to support 48KHz playback/record with audio
   codec on RZ/G2L SMARC EVK
 - Introduce kstrdup_and_replace() and use it

* clk-versa:
  clk: vc7: Use i2c_get_match_data() instead of device_get_match_data()
  clk: vc5: Use i2c_get_match_data() instead of device_get_match_data()
  clk: versaclock3: Switch to use i2c_driver's probe callback
  clk: Add support for versa3 clock driver
  dt-bindings: clock: Add Renesas versa3 clock generator bindings

* clk-strdup:
  clk: ti: Replace kstrdup() + strreplace() with kstrdup_and_replace()
  clk: tegra: Replace kstrdup() + strreplace() with kstrdup_and_replace()
  driver core: Replace kstrdup() + strreplace() with kstrdup_and_replace()
  lib/string_helpers: Add kstrdup_and_replace() helper

* clk-amlogic: (22 commits)
  dt-bindings: soc: amlogic: document System Control registers
  dt-bindings: clock: amlogic: convert amlogic,gxbb-aoclkc.txt to dt-schema
  dt-bindings: clock: amlogic: convert amlogic,gxbb-clkc.txt to dt-schema
  clk: meson: axg-audio: move bindings include to main driver
  clk: meson: meson8b: move bindings include to main driver
  clk: meson: a1: move bindings include to main driver
  clk: meson: eeclk: move bindings include to main driver
  clk: meson: aoclk: move bindings include to main driver
  dt-bindings: clk: axg-audio-clkc: expose all clock ids
  dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids
  dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock ids
  dt-bindings: clk: meson8b-clkc: expose all clock ids
  dt-bindings: clk: g12a-aoclkc: expose all clock ids
  dt-bindings: clk: g12a-clks: expose all clock ids
  dt-bindings: clk: axg-clkc: expose all clock ids
  dt-bindings: clk: gxbb-clkc: expose all clock ids
  clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS
  clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKS
  clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS
  clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS
  ...

* clk-allwinner:
  clk: sunxi-ng: nkm: Prefer current parent rate
  clk: sunxi-ng: a64: select closest rate for pll-video0
  clk: sunxi-ng: div: Support finding closest rate
  clk: sunxi-ng: mux: Support finding closest rate
  clk: sunxi-ng: nkm: Support finding closest rate
  clk: sunxi-ng: nm: Support finding closest rate
  clk: sunxi-ng: Add helper function to find closest rate
  clk: sunxi-ng: Add feature to find closest rate
  clk: sunxi-ng: a64: allow pll-mipi to set parent's rate
  clk: sunxi-ng: nkm: consider alternative parent rates when determining rate
  clk: sunxi-ng: nkm: Use correct parameter name for parent HW
  clk: sunxi-ng: Modify mismatched function name
  clk: sunxi: sun9i-mmc: Use devm_platform_get_and_ioremap_resource()

* clk-rockchip:
  clk: rockchip: rv1126: Add PD_VO clock tree
  clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
  clk: rockchip: rk3568: Add PLL rate for 101MHz
This commit is contained in:
Stephen Boyd
2023-08-30 14:38:19 -07:00
parent d10ebc7c64 fccd617f65 bb362d0e91 caf0dcedf9 364a609dc3 438c61a790
commit 032bcf783e
66 changed files with 5000 additions and 3463 deletions
Download Patch File Download Diff File Expand all files Collapse all files

64
Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
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@@ -1,64 +0,0 @@
* Amlogic GXBB AO Clock and Reset Unit
The Amlogic GXBB AO clock controller generates and supplies clock to various
controllers within the Always-On part of the SoC.
Required Properties:
- compatible: value should be different for each SoC family as :
- GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
- GXM (S912) : "amlogic,meson-gxm-aoclkc"
- AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
- G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc"
followed by the common "amlogic,meson-gx-aoclkc"
- clocks: list of clock phandle, one for each entry clock-names.
- clock-names: should contain the following:
* "xtal" : the platform xtal
* "mpeg-clk" : the main clock controller mother clock (aka clk81)
* "ext-32k-0" : external 32kHz reference #0 if any (optional)
* "ext-32k-1" : external 32kHz reference #1 if any (optional - gx only)
* "ext-32k-2" : external 32kHz reference #2 if any (optional - gx only)
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/gxbb-aoclkc.h header and can be
used in device tree sources.
- #reset-cells: should be 1.
Each reset is assigned an identifier and client nodes can use this identifier
to specify the reset which they consume. All available resets are defined as
preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be
used in device tree sources.
Parent node should have the following properties :
- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
- reg: base address and size of the AO system control register space.
Example: AO Clock controller node:
ao_sysctrl: sys-ctrl@0 {
compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
reg = <0x0 0x0 0x0 0x100>;
clkc_AO: clock-controller {
compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&xtal>, <&clkc CLKID_CLK81>;
clock-names = "xtal", "mpeg-clk";
};
Example: UART controller node that consumes the clock and reset generated
by the clock controller:
uart_AO: serial@4c0 {
compatible = "amlogic,meson-uart";
reg = <0x4c0 0x14>;
interrupts = <0 90 1>;
clocks = <&clkc_AO CLKID_AO_UART1>;
resets = <&clkc_AO RESET_AO_UART1>;
};

85
Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.yaml Normal file
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@@ -0,0 +1,85 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,gxbb-aoclkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Always-On Clock Controller
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
properties:
compatible:
oneOf:
- items:
- enum:
- amlogic,meson-gxbb-aoclkc
- amlogic,meson-gxl-aoclkc
- amlogic,meson-gxm-aoclkc
- amlogic,meson-axg-aoclkc
- const: amlogic,meson-gx-aoclkc
- enum:
- amlogic,meson-axg-aoclkc
- amlogic,meson-g12a-aoclkc
clocks:
minItems: 2
maxItems: 5
clock-names:
minItems: 2
items:
- const: xtal
- const: mpeg-clk
- const: ext-32k-0
- const: ext-32k-1
- const: ext-32k-2
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
allOf:
- if:
properties:
compatible:
enum:
- amlogic,meson-g12a-aoclkc
then:
properties:
clocks:
minItems: 2
maxItems: 3
clock-names:
minItems: 2
maxItems: 3
- if:
properties:
compatible:
enum:
- amlogic,meson-gxl-aoclkc
- amlogic,meson-gxm-aoclkc
- amlogic,meson-axg-aoclkc
then:
properties:
clocks:
maxItems: 2
clock-names:
maxItems: 2
additionalProperties: false

53
Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
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@@ -1,53 +0,0 @@
* Amlogic GXBB Clock and Reset Unit
The Amlogic GXBB clock controller generates and supplies clock to various
controllers within the SoC.
Required Properties:
- compatible: should be:
"amlogic,gxbb-clkc" for GXBB SoC,
"amlogic,gxl-clkc" for GXL and GXM SoC,
"amlogic,axg-clkc" for AXG SoC.
"amlogic,g12a-clkc" for G12A SoC.
"amlogic,g12b-clkc" for G12B SoC.
"amlogic,sm1-clkc" for SM1 SoC.
- clocks : list of clock phandle, one for each entry clock-names.
- clock-names : should contain the following:
* "xtal": the platform xtal
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be
used in device tree sources.
Parent node should have the following properties :
- compatible: "syscon", "simple-mfd, and "amlogic,meson-gx-hhi-sysctrl" or
"amlogic,meson-axg-hhi-sysctrl"
- reg: base address and size of the HHI system control register space.
Example: Clock controller node:
sysctrl: system-controller@0 {
compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
reg = <0 0 0 0x400>;
clkc: clock-controller {
#clock-cells = <1>;
compatible = "amlogic,gxbb-clkc";
clocks = <&xtal>;
clock-names = "xtal";
};
};
Example: UART controller node that consumes the clock generated by the clock
controller:
uart_AO: serial@c81004c0 {
compatible = "amlogic,meson-uart";
reg = <0xc81004c0 0x14>;
interrupts = <0 90 1>;
clocks = <&clkc CLKID_CLK81>;
};

37
Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.yaml Normal file
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@@ -0,0 +1,37 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,gxbb-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Clock Controller
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
properties:
compatible:
enum:
- amlogic,gxbb-clkc
- amlogic,gxl-clkc
- amlogic,axg-clkc
- amlogic,g12a-clkc
- amlogic,g12b-clkc
- amlogic,sm1-clkc
clocks:
maxItems: 1
clock-names:
const: xtal
'#clock-cells':
const: 1
required:
- compatible
- clocks
- clock-names
- '#clock-cells'
additionalProperties: false

86
Documentation/devicetree/bindings/clock/renesas,5p35023.yaml Normal file
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@@ -0,0 +1,86 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/renesas,5p35023.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas 5p35023 VersaClock 3 programmable I2C clock generator
maintainers:
- Biju Das <biju.das.jz@bp.renesas.com>
description: |
The 5P35023 is a VersaClock programmable clock generator and
is designed for low-power, consumer, and high-performance PCI
express applications. The 5P35023 device is a three PLL
architecture design, and each PLL is individually programmable
and allowing for up to 6 unique frequency outputs.
An internal OTP memory allows the user to store the configuration
in the device. After power up, the user can change the device register
settings through the I2C interface when I2C mode is selected.
The driver can read a full register map from the DT, and will use that
register map to initialize the attached part (via I2C) when the system
boots. Any configuration not supported by the common clock framework
must be done via the full register map, including optimized settings.
Link to datasheet:
https://www.renesas.com/us/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3s-programmable-clock-generator
properties:
compatible:
enum:
- renesas,5p35023
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
maxItems: 1
renesas,settings:
description: Optional, complete register map of the device.
Optimized settings for the device must be provided in full
and are written during initialization.
$ref: /schemas/types.yaml#/definitions/uint8-array
maxItems: 37
required:
- compatible
- reg
- '#clock-cells'
- clocks
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
versa3: clock-generator@68 {
compatible = "renesas,5p35023";
reg = <0x68>;
#clock-cells = <1>;
clocks = <&x1_x2>;
renesas,settings = [
80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
80 b0 45 c4 95
];
assigned-clocks = <&versa3 0>, <&versa3 1>,
<&versa3 2>, <&versa3 3>,
<&versa3 4>, <&versa3 5>;
assigned-clock-rates = <12288000>, <25000000>,
<12000000>, <11289600>,
<11289600>, <24000000>;
};
};

160
Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml Normal file
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@@ -0,0 +1,160 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Meson System Control registers
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
properties:
compatible:
items:
- enum:
- amlogic,meson-gx-hhi-sysctrl
- amlogic,meson-gx-ao-sysctrl
- amlogic,meson-axg-hhi-sysctrl
- amlogic,meson-axg-ao-sysctrl
- const: simple-mfd
- const: syscon
reg:
maxItems: 1
clock-controller:
type: object
power-controller:
$ref: /schemas/power/amlogic,meson-ee-pwrc.yaml
pinctrl:
type: object
phy:
type: object
allOf:
- if:
properties:
compatible:
enum:
- amlogic,meson-gx-hhi-sysctrl
- amlogic,meson-axg-hhi-sysctrl
then:
properties:
clock-controller:
$ref: /schemas/clock/amlogic,gxbb-clkc.yaml#
required:
- power-controller
- if:
properties:
compatible:
enum:
- amlogic,meson-gx-ao-sysctrl
- amlogic,meson-axg-ao-sysctrl
then:
properties:
clock-controller:
$ref: /schemas/clock/amlogic,gxbb-aoclkc.yaml#
power-controller: false
phy: false
- if:
properties:
compatible:
enum:
- amlogic,meson-gx-hhi-sysctrl
then:
properties:
phy: false
- if:
properties:
compatible:
enum:
- amlogic,meson-axg-hhi-sysctrl
then:
properties:
phy:
oneOf:
- $ref: /schemas/phy/amlogic,g12a-mipi-dphy-analog.yaml
- $ref: /schemas/phy/amlogic,meson-axg-mipi-pcie-analog.yaml
required:
- compatible
- reg
- clock-controller
additionalProperties: false
examples:
- |
bus@c883c000 {
compatible = "simple-bus";
reg = <0xc883c000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xc883c000 0x2000>;
sysctrl: system-controller@0 {
compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon";
reg = <0 0x400>;
clock-controller {
compatible = "amlogic,gxbb-clkc";
#clock-cells = <1>;
clocks = <&xtal>;
clock-names = "xtal";
};
power-controller {
compatible = "amlogic,meson-gxbb-pwrc";
#power-domain-cells = <1>;
amlogic,ao-sysctrl = <&sysctrl_AO>;
resets = <&reset_viu>,
<&reset_venc>,
<&reset_vcbus>,
<&reset_bt656>,
<&reset_dvin>,
<&reset_rdma>,
<&reset_venci>,
<&reset_vencp>,
<&reset_vdac>,
<&reset_vdi6>,
<&reset_vencl>,
<&reset_vid_lock>;
reset-names = "viu", "venc", "vcbus", "bt656", "dvin",
"rdma", "venci", "vencp", "vdac", "vdi6",
"vencl", "vid_lock";
clocks = <&clk_vpu>, <&clk_vapb>;
clock-names = "vpu", "vapb";
};
};
};
bus@c8100000 {
compatible = "simple-bus";
reg = <0xc8100000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xc8100000 0x100000>;
sysctrl_AO: system-controller@0 {
compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon";
reg = <0 0x100>;
clock-controller {
compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&xtal>, <&clk81>;
clock-names = "xtal", "mpeg-clk";
};
};
};

5
drivers/base/core.c
View File

@@ -17,7 +17,6 @@
#include <linux/kstrtox.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/kdev_t.h>
#include <linux/notifier.h>
#include <linux/of.h>
@@ -28,6 +27,7 @@
#include <linux/netdevice.h>
#include <linux/sched/signal.h>
#include <linux/sched/mm.h>
#include <linux/string_helpers.h>
#include <linux/swiotlb.h>
#include <linux/sysfs.h>
#include <linux/dma-map-ops.h> /* for dma_default_coherent */
@@ -3910,10 +3910,9 @@ const char *device_get_devnode(const struct device *dev,
return dev_name(dev);
/* replace '!' in the name with '/' */
s = kstrdup(dev_name(dev), GFP_KERNEL);
s = kstrdup_and_replace(dev_name(dev), '!', '/', GFP_KERNEL);
if (!s)
return NULL;
strreplace(s, '!', '/');
return *tmp = s;
}

9
drivers/clk/Kconfig
View File

@@ -378,6 +378,15 @@ config COMMON_CLK_SI521XX
This driver supports the SkyWorks Si521xx PCIe clock generator
models Si52144/Si52146/Si52147.
config COMMON_CLK_VC3
tristate "Clock driver for Renesas VersaClock 3 devices"
depends on I2C
depends on OF
select REGMAP_I2C
help
This driver supports the Renesas VersaClock 3 programmable clock
generators.
config COMMON_CLK_VC5
tristate "Clock driver for IDT VersaClock 5,6 devices"
depends on I2C

1
drivers/clk/Makefile
View File

@@ -75,6 +75,7 @@ obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
obj-$(CONFIG_COMMON_CLK_RS9_PCIE) += clk-renesas-pcie.o
obj-$(CONFIG_COMMON_CLK_SI521XX) += clk-si521xx.o
obj-$(CONFIG_COMMON_CLK_VC3) += clk-versaclock3.o
obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o
obj-$(CONFIG_COMMON_CLK_VC7) += clk-versaclock7.o
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o

1143
drivers/clk/clk-versaclock3.c Normal file
View File

File diff suppressed because it is too large Load Diff

2
drivers/clk/clk-versaclock5.c
View File

@@ -955,7 +955,7 @@ static int vc5_probe(struct i2c_client *client)
i2c_set_clientdata(client, vc5);
vc5->client = client;
vc5->chip_info = device_get_match_data(&client->dev);
vc5->chip_info = i2c_get_match_data(client);
vc5->pin_xin = devm_clk_get(&client->dev, "xin");
if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER)

2
drivers/clk/clk-versaclock7.c
View File

@@ -1108,7 +1108,7 @@ static int vc7_probe(struct i2c_client *client)
i2c_set_clientdata(client, vc7);
vc7->client = client;
vc7->chip_info = device_get_match_data(&client->dev);
vc7->chip_info = i2c_get_match_data(client);
vc7->pin_xin = devm_clk_get(&client->dev, "xin");
if (PTR_ERR(vc7->pin_xin) == -EPROBE_DEFER) {

9
drivers/clk/meson/Kconfig
View File

@@ -30,14 +30,19 @@ config COMMON_CLK_MESON_VID_PLL_DIV
tristate
select COMMON_CLK_MESON_REGMAP
config COMMON_CLK_MESON_CLKC_UTILS
tristate
config COMMON_CLK_MESON_AO_CLKC
tristate
select COMMON_CLK_MESON_REGMAP
select COMMON_CLK_MESON_CLKC_UTILS
select RESET_CONTROLLER
config COMMON_CLK_MESON_EE_CLKC
tristate
select COMMON_CLK_MESON_REGMAP
select COMMON_CLK_MESON_CLKC_UTILS
config COMMON_CLK_MESON_CPU_DYNDIV
tristate
@@ -48,6 +53,7 @@ config COMMON_CLK_MESON8B
depends on ARM
default y
select COMMON_CLK_MESON_REGMAP
select COMMON_CLK_MESON_CLKC_UTILS
select COMMON_CLK_MESON_MPLL
select COMMON_CLK_MESON_PLL
select MFD_SYSCON
@@ -94,6 +100,7 @@ config COMMON_CLK_AXG_AUDIO
select COMMON_CLK_MESON_REGMAP
select COMMON_CLK_MESON_PHASE
select COMMON_CLK_MESON_SCLK_DIV
select COMMON_CLK_MESON_CLKC_UTILS
select REGMAP_MMIO
help
Support for the audio clock controller on AmLogic A113D devices,
@@ -103,6 +110,7 @@ config COMMON_CLK_A1_PLL
tristate "Amlogic A1 SoC PLL controller support"
depends on ARM64
select COMMON_CLK_MESON_REGMAP
select COMMON_CLK_MESON_CLKC_UTILS
select COMMON_CLK_MESON_PLL
help
Support for the PLL clock controller on Amlogic A113L based
@@ -114,6 +122,7 @@ config COMMON_CLK_A1_PERIPHERALS
depends on ARM64
select COMMON_CLK_MESON_DUALDIV
select COMMON_CLK_MESON_REGMAP
select COMMON_CLK_MESON_CLKC_UTILS
help
Support for the Peripherals clock controller on Amlogic A113L based
device, A1 SoC Family. Say Y if you want A1 Peripherals clock

1
drivers/clk/meson/Makefile
View File

@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
# Amlogic clock drivers
obj-$(CONFIG_COMMON_CLK_MESON_CLKC_UTILS) += meson-clkc-utils.o
obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o
obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o

325
drivers/clk/meson/a1-peripherals.c
View File

@@ -13,6 +13,9 @@
#include "a1-peripherals.h"
#include "clk-dualdiv.h"
#include "clk-regmap.h"
#include "meson-clkc-utils.h"
#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
static struct clk_regmap xtal_in = {
.data = &(struct clk_regmap_gate_data){
@@ -1866,165 +1869,161 @@ static MESON_GATE(rom, AXI_CLK_EN, 11);
static MESON_GATE(prod_i2c, AXI_CLK_EN, 12);
/* Array of all clocks registered by this provider */
static struct clk_hw_onecell_data a1_periphs_clks = {
.hws = {
[CLKID_XTAL_IN] = &xtal_in.hw,
[CLKID_FIXPLL_IN] = &fixpll_in.hw,
[CLKID_USB_PHY_IN] = &usb_phy_in.hw,
[CLKID_USB_CTRL_IN] = &usb_ctrl_in.hw,
[CLKID_HIFIPLL_IN] = &hifipll_in.hw,
[CLKID_SYSPLL_IN] = &syspll_in.hw,
[CLKID_DDS_IN] = &dds_in.hw,
[CLKID_SYS] = &sys.hw,
[CLKID_CLKTREE] = &clktree.hw,
[CLKID_RESET_CTRL] = &reset_ctrl.hw,
[CLKID_ANALOG_CTRL] = &analog_ctrl.hw,
[CLKID_PWR_CTRL] = &pwr_ctrl.hw,
[CLKID_PAD_CTRL] = &pad_ctrl.hw,
[CLKID_SYS_CTRL] = &sys_ctrl.hw,
[CLKID_TEMP_SENSOR] = &temp_sensor.hw,
[CLKID_AM2AXI_DIV] = &am2axi_dev.hw,
[CLKID_SPICC_B] = &spicc_b.hw,
[CLKID_SPICC_A] = &spicc_a.hw,
[CLKID_MSR] = &msr.hw,
[CLKID_AUDIO] = &audio.hw,
[CLKID_JTAG_CTRL] = &jtag_ctrl.hw,
[CLKID_SARADC_EN] = &saradc_en.hw,
[CLKID_PWM_EF] = &pwm_ef.hw,
[CLKID_PWM_CD] = &pwm_cd.hw,
[CLKID_PWM_AB] = &pwm_ab.hw,
[CLKID_CEC] = &cec.hw,
[CLKID_I2C_S] = &i2c_s.hw,
[CLKID_IR_CTRL] = &ir_ctrl.hw,
[CLKID_I2C_M_D] = &i2c_m_d.hw,
[CLKID_I2C_M_C] = &i2c_m_c.hw,
[CLKID_I2C_M_B] = &i2c_m_b.hw,
[CLKID_I2C_M_A] = &i2c_m_a.hw,
[CLKID_ACODEC] = &acodec.hw,
[CLKID_OTP] = &otp.hw,
[CLKID_SD_EMMC_A] = &sd_emmc_a.hw,
[CLKID_USB_PHY] = &usb_phy.hw,
[CLKID_USB_CTRL] = &usb_ctrl.hw,
[CLKID_SYS_DSPB] = &sys_dspb.hw,
[CLKID_SYS_DSPA] = &sys_dspa.hw,
[CLKID_DMA] = &dma.hw,
[CLKID_IRQ_CTRL] = &irq_ctrl.hw,
[CLKID_NIC] = &nic.hw,
[CLKID_GIC] = &gic.hw,
[CLKID_UART_C] = &uart_c.hw,
[CLKID_UART_B] = &uart_b.hw,
[CLKID_UART_A] = &uart_a.hw,
[CLKID_SYS_PSRAM] = &sys_psram.hw,
[CLKID_RSA] = &rsa.hw,
[CLKID_CORESIGHT] = &coresight.hw,
[CLKID_AM2AXI_VAD] = &am2axi_vad.hw,
[CLKID_AUDIO_VAD] = &audio_vad.hw,
[CLKID_AXI_DMC] = &axi_dmc.hw,
[CLKID_AXI_PSRAM] = &axi_psram.hw,
[CLKID_RAMB] = &ramb.hw,
[CLKID_RAMA] = &rama.hw,
[CLKID_AXI_SPIFC] = &axi_spifc.hw,
[CLKID_AXI_NIC] = &axi_nic.hw,
[CLKID_AXI_DMA] = &axi_dma.hw,
[CLKID_CPU_CTRL] = &cpu_ctrl.hw,
[CLKID_ROM] = &rom.hw,
[CLKID_PROC_I2C] = &prod_i2c.hw,
[CLKID_DSPA_SEL] = &dspa_sel.hw,
[CLKID_DSPB_SEL] = &dspb_sel.hw,
[CLKID_DSPA_EN] = &dspa_en.hw,
[CLKID_DSPA_EN_NIC] = &dspa_en_nic.hw,
[CLKID_DSPB_EN] = &dspb_en.hw,
[CLKID_DSPB_EN_NIC] = &dspb_en_nic.hw,
[CLKID_RTC] = &rtc.hw,
[CLKID_CECA_32K] = &ceca_32k_out.hw,
[CLKID_CECB_32K] = &cecb_32k_out.hw,
[CLKID_24M] = &clk_24m.hw,
[CLKID_12M] = &clk_12m.hw,
[CLKID_FCLK_DIV2_DIVN] = &fclk_div2_divn.hw,
[CLKID_GEN] = &gen.hw,
[CLKID_SARADC_SEL] = &saradc_sel.hw,
[CLKID_SARADC] = &saradc.hw,
[CLKID_PWM_A] = &pwm_a.hw,
[CLKID_PWM_B] = &pwm_b.hw,
[CLKID_PWM_C] = &pwm_c.hw,
[CLKID_PWM_D] = &pwm_d.hw,
[CLKID_PWM_E] = &pwm_e.hw,
[CLKID_PWM_F] = &pwm_f.hw,
[CLKID_SPICC] = &spicc.hw,
[CLKID_TS] = &ts.hw,
[CLKID_SPIFC] = &spifc.hw,
[CLKID_USB_BUS] = &usb_bus.hw,
[CLKID_SD_EMMC] = &sd_emmc.hw,
[CLKID_PSRAM] = &psram.hw,
[CLKID_DMC] = &dmc.hw,
[CLKID_SYS_A_SEL] = &sys_a_sel.hw,
[CLKID_SYS_A_DIV] = &sys_a_div.hw,
[CLKID_SYS_A] = &sys_a.hw,
[CLKID_SYS_B_SEL] = &sys_b_sel.hw,
[CLKID_SYS_B_DIV] = &sys_b_div.hw,
[CLKID_SYS_B] = &sys_b.hw,
[CLKID_DSPA_A_SEL] = &dspa_a_sel.hw,
[CLKID_DSPA_A_DIV] = &dspa_a_div.hw,
[CLKID_DSPA_A] = &dspa_a.hw,
[CLKID_DSPA_B_SEL] = &dspa_b_sel.hw,
[CLKID_DSPA_B_DIV] = &dspa_b_div.hw,
[CLKID_DSPA_B] = &dspa_b.hw,
[CLKID_DSPB_A_SEL] = &dspb_a_sel.hw,
[CLKID_DSPB_A_DIV] = &dspb_a_div.hw,
[CLKID_DSPB_A] = &dspb_a.hw,
[CLKID_DSPB_B_SEL] = &dspb_b_sel.hw,
[CLKID_DSPB_B_DIV] = &dspb_b_div.hw,
[CLKID_DSPB_B] = &dspb_b.hw,
[CLKID_RTC_32K_IN] = &rtc_32k_in.hw,
[CLKID_RTC_32K_DIV] = &rtc_32k_div.hw,
[CLKID_RTC_32K_XTAL] = &rtc_32k_xtal.hw,
[CLKID_RTC_32K_SEL] = &rtc_32k_sel.hw,
[CLKID_CECB_32K_IN] = &cecb_32k_in.hw,
[CLKID_CECB_32K_DIV] = &cecb_32k_div.hw,
[CLKID_CECB_32K_SEL_PRE] = &cecb_32k_sel_pre.hw,
[CLKID_CECB_32K_SEL] = &cecb_32k_sel.hw,
[CLKID_CECA_32K_IN] = &ceca_32k_in.hw,
[CLKID_CECA_32K_DIV] = &ceca_32k_div.hw,
[CLKID_CECA_32K_SEL_PRE] = &ceca_32k_sel_pre.hw,
[CLKID_CECA_32K_SEL] = &ceca_32k_sel.hw,
[CLKID_DIV2_PRE] = &fclk_div2_divn_pre.hw,
[CLKID_24M_DIV2] = &clk_24m_div2.hw,
[CLKID_GEN_SEL] = &gen_sel.hw,
[CLKID_GEN_DIV] = &gen_div.hw,
[CLKID_SARADC_DIV] = &saradc_div.hw,
[CLKID_PWM_A_SEL] = &pwm_a_sel.hw,
[CLKID_PWM_A_DIV] = &pwm_a_div.hw,
[CLKID_PWM_B_SEL] = &pwm_b_sel.hw,
[CLKID_PWM_B_DIV] = &pwm_b_div.hw,
[CLKID_PWM_C_SEL] = &pwm_c_sel.hw,
[CLKID_PWM_C_DIV] = &pwm_c_div.hw,
[CLKID_PWM_D_SEL] = &pwm_d_sel.hw,
[CLKID_PWM_D_DIV] = &pwm_d_div.hw,
[CLKID_PWM_E_SEL] = &pwm_e_sel.hw,
[CLKID_PWM_E_DIV] = &pwm_e_div.hw,
[CLKID_PWM_F_SEL] = &pwm_f_sel.hw,
[CLKID_PWM_F_DIV] = &pwm_f_div.hw,
[CLKID_SPICC_SEL] = &spicc_sel.hw,
[CLKID_SPICC_DIV] = &spicc_div.hw,
[CLKID_SPICC_SEL2] = &spicc_sel2.hw,
[CLKID_TS_DIV] = &ts_div.hw,
[CLKID_SPIFC_SEL] = &spifc_sel.hw,
[CLKID_SPIFC_DIV] = &spifc_div.hw,
[CLKID_SPIFC_SEL2] = &spifc_sel2.hw,
[CLKID_USB_BUS_SEL] = &usb_bus_sel.hw,
[CLKID_USB_BUS_DIV] = &usb_bus_div.hw,
[CLKID_SD_EMMC_SEL] = &sd_emmc_sel.hw,
[CLKID_SD_EMMC_DIV] = &sd_emmc_div.hw,
[CLKID_SD_EMMC_SEL2] = &sd_emmc_sel2.hw,
[CLKID_PSRAM_SEL] = &psram_sel.hw,
[CLKID_PSRAM_DIV] = &psram_div.hw,
[CLKID_PSRAM_SEL2] = &psram_sel2.hw,
[CLKID_DMC_SEL] = &dmc_sel.hw,
[CLKID_DMC_DIV] = &dmc_div.hw,
[CLKID_DMC_SEL2] = &dmc_sel2.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
static struct clk_hw *a1_periphs_hw_clks[] = {
[CLKID_XTAL_IN] = &xtal_in.hw,
[CLKID_FIXPLL_IN] = &fixpll_in.hw,
[CLKID_USB_PHY_IN] = &usb_phy_in.hw,
[CLKID_USB_CTRL_IN] = &usb_ctrl_in.hw,
[CLKID_HIFIPLL_IN] = &hifipll_in.hw,
[CLKID_SYSPLL_IN] = &syspll_in.hw,
[CLKID_DDS_IN] = &dds_in.hw,
[CLKID_SYS] = &sys.hw,
[CLKID_CLKTREE] = &clktree.hw,
[CLKID_RESET_CTRL] = &reset_ctrl.hw,
[CLKID_ANALOG_CTRL] = &analog_ctrl.hw,
[CLKID_PWR_CTRL] = &pwr_ctrl.hw,
[CLKID_PAD_CTRL] = &pad_ctrl.hw,
[CLKID_SYS_CTRL] = &sys_ctrl.hw,
[CLKID_TEMP_SENSOR] = &temp_sensor.hw,
[CLKID_AM2AXI_DIV] = &am2axi_dev.hw,
[CLKID_SPICC_B] = &spicc_b.hw,
[CLKID_SPICC_A] = &spicc_a.hw,
[CLKID_MSR] = &msr.hw,
[CLKID_AUDIO] = &audio.hw,
[CLKID_JTAG_CTRL] = &jtag_ctrl.hw,
[CLKID_SARADC_EN] = &saradc_en.hw,
[CLKID_PWM_EF] = &pwm_ef.hw,
[CLKID_PWM_CD] = &pwm_cd.hw,
[CLKID_PWM_AB] = &pwm_ab.hw,
[CLKID_CEC] = &cec.hw,
[CLKID_I2C_S] = &i2c_s.hw,
[CLKID_IR_CTRL] = &ir_ctrl.hw,
[CLKID_I2C_M_D] = &i2c_m_d.hw,
[CLKID_I2C_M_C] = &i2c_m_c.hw,
[CLKID_I2C_M_B] = &i2c_m_b.hw,
[CLKID_I2C_M_A] = &i2c_m_a.hw,
[CLKID_ACODEC] = &acodec.hw,
[CLKID_OTP] = &otp.hw,
[CLKID_SD_EMMC_A] = &sd_emmc_a.hw,
[CLKID_USB_PHY] = &usb_phy.hw,
[CLKID_USB_CTRL] = &usb_ctrl.hw,
[CLKID_SYS_DSPB] = &sys_dspb.hw,
[CLKID_SYS_DSPA] = &sys_dspa.hw,
[CLKID_DMA] = &dma.hw,
[CLKID_IRQ_CTRL] = &irq_ctrl.hw,
[CLKID_NIC] = &nic.hw,
[CLKID_GIC] = &gic.hw,
[CLKID_UART_C] = &uart_c.hw,
[CLKID_UART_B] = &uart_b.hw,
[CLKID_UART_A] = &uart_a.hw,
[CLKID_SYS_PSRAM] = &sys_psram.hw,
[CLKID_RSA] = &rsa.hw,
[CLKID_CORESIGHT] = &coresight.hw,
[CLKID_AM2AXI_VAD] = &am2axi_vad.hw,
[CLKID_AUDIO_VAD] = &audio_vad.hw,
[CLKID_AXI_DMC] = &axi_dmc.hw,
[CLKID_AXI_PSRAM] = &axi_psram.hw,
[CLKID_RAMB] = &ramb.hw,
[CLKID_RAMA] = &rama.hw,
[CLKID_AXI_SPIFC] = &axi_spifc.hw,
[CLKID_AXI_NIC] = &axi_nic.hw,
[CLKID_AXI_DMA] = &axi_dma.hw,
[CLKID_CPU_CTRL] = &cpu_ctrl.hw,
[CLKID_ROM] = &rom.hw,
[CLKID_PROC_I2C] = &prod_i2c.hw,
[CLKID_DSPA_SEL] = &dspa_sel.hw,
[CLKID_DSPB_SEL] = &dspb_sel.hw,
[CLKID_DSPA_EN] = &dspa_en.hw,
[CLKID_DSPA_EN_NIC] = &dspa_en_nic.hw,
[CLKID_DSPB_EN] = &dspb_en.hw,
[CLKID_DSPB_EN_NIC] = &dspb_en_nic.hw,
[CLKID_RTC] = &rtc.hw,
[CLKID_CECA_32K] = &ceca_32k_out.hw,
[CLKID_CECB_32K] = &cecb_32k_out.hw,
[CLKID_24M] = &clk_24m.hw,
[CLKID_12M] = &clk_12m.hw,
[CLKID_FCLK_DIV2_DIVN] = &fclk_div2_divn.hw,
[CLKID_GEN] = &gen.hw,
[CLKID_SARADC_SEL] = &saradc_sel.hw,
[CLKID_SARADC] = &saradc.hw,
[CLKID_PWM_A] = &pwm_a.hw,
[CLKID_PWM_B] = &pwm_b.hw,
[CLKID_PWM_C] = &pwm_c.hw,
[CLKID_PWM_D] = &pwm_d.hw,
[CLKID_PWM_E] = &pwm_e.hw,
[CLKID_PWM_F] = &pwm_f.hw,
[CLKID_SPICC] = &spicc.hw,
[CLKID_TS] = &ts.hw,
[CLKID_SPIFC] = &spifc.hw,
[CLKID_USB_BUS] = &usb_bus.hw,
[CLKID_SD_EMMC] = &sd_emmc.hw,
[CLKID_PSRAM] = &psram.hw,
[CLKID_DMC] = &dmc.hw,
[CLKID_SYS_A_SEL] = &sys_a_sel.hw,
[CLKID_SYS_A_DIV] = &sys_a_div.hw,
[CLKID_SYS_A] = &sys_a.hw,
[CLKID_SYS_B_SEL] = &sys_b_sel.hw,
[CLKID_SYS_B_DIV] = &sys_b_div.hw,
[CLKID_SYS_B] = &sys_b.hw,
[CLKID_DSPA_A_SEL] = &dspa_a_sel.hw,
[CLKID_DSPA_A_DIV] = &dspa_a_div.hw,
[CLKID_DSPA_A] = &dspa_a.hw,
[CLKID_DSPA_B_SEL] = &dspa_b_sel.hw,
[CLKID_DSPA_B_DIV] = &dspa_b_div.hw,
[CLKID_DSPA_B] = &dspa_b.hw,
[CLKID_DSPB_A_SEL] = &dspb_a_sel.hw,
[CLKID_DSPB_A_DIV] = &dspb_a_div.hw,
[CLKID_DSPB_A] = &dspb_a.hw,
[CLKID_DSPB_B_SEL] = &dspb_b_sel.hw,
[CLKID_DSPB_B_DIV] = &dspb_b_div.hw,
[CLKID_DSPB_B] = &dspb_b.hw,
[CLKID_RTC_32K_IN] = &rtc_32k_in.hw,
[CLKID_RTC_32K_DIV] = &rtc_32k_div.hw,
[CLKID_RTC_32K_XTAL] = &rtc_32k_xtal.hw,
[CLKID_RTC_32K_SEL] = &rtc_32k_sel.hw,
[CLKID_CECB_32K_IN] = &cecb_32k_in.hw,
[CLKID_CECB_32K_DIV] = &cecb_32k_div.hw,
[CLKID_CECB_32K_SEL_PRE] = &cecb_32k_sel_pre.hw,
[CLKID_CECB_32K_SEL] = &cecb_32k_sel.hw,
[CLKID_CECA_32K_IN] = &ceca_32k_in.hw,
[CLKID_CECA_32K_DIV] = &ceca_32k_div.hw,
[CLKID_CECA_32K_SEL_PRE] = &ceca_32k_sel_pre.hw,
[CLKID_CECA_32K_SEL] = &ceca_32k_sel.hw,
[CLKID_DIV2_PRE] = &fclk_div2_divn_pre.hw,
[CLKID_24M_DIV2] = &clk_24m_div2.hw,
[CLKID_GEN_SEL] = &gen_sel.hw,
[CLKID_GEN_DIV] = &gen_div.hw,
[CLKID_SARADC_DIV] = &saradc_div.hw,
[CLKID_PWM_A_SEL] = &pwm_a_sel.hw,
[CLKID_PWM_A_DIV] = &pwm_a_div.hw,
[CLKID_PWM_B_SEL] = &pwm_b_sel.hw,
[CLKID_PWM_B_DIV] = &pwm_b_div.hw,
[CLKID_PWM_C_SEL] = &pwm_c_sel.hw,
[CLKID_PWM_C_DIV] = &pwm_c_div.hw,
[CLKID_PWM_D_SEL] = &pwm_d_sel.hw,
[CLKID_PWM_D_DIV] = &pwm_d_div.hw,
[CLKID_PWM_E_SEL] = &pwm_e_sel.hw,
[CLKID_PWM_E_DIV] = &pwm_e_div.hw,
[CLKID_PWM_F_SEL] = &pwm_f_sel.hw,
[CLKID_PWM_F_DIV] = &pwm_f_div.hw,
[CLKID_SPICC_SEL] = &spicc_sel.hw,
[CLKID_SPICC_DIV] = &spicc_div.hw,
[CLKID_SPICC_SEL2] = &spicc_sel2.hw,
[CLKID_TS_DIV] = &ts_div.hw,
[CLKID_SPIFC_SEL] = &spifc_sel.hw,
[CLKID_SPIFC_DIV] = &spifc_div.hw,
[CLKID_SPIFC_SEL2] = &spifc_sel2.hw,
[CLKID_USB_BUS_SEL] = &usb_bus_sel.hw,
[CLKID_USB_BUS_DIV] = &usb_bus_div.hw,
[CLKID_SD_EMMC_SEL] = &sd_emmc_sel.hw,
[CLKID_SD_EMMC_DIV] = &sd_emmc_div.hw,
[CLKID_SD_EMMC_SEL2] = &sd_emmc_sel2.hw,
[CLKID_PSRAM_SEL] = &psram_sel.hw,
[CLKID_PSRAM_DIV] = &psram_div.hw,
[CLKID_PSRAM_SEL2] = &psram_sel2.hw,
[CLKID_DMC_SEL] = &dmc_sel.hw,
[CLKID_DMC_DIV] = &dmc_div.hw,
[CLKID_DMC_SEL2] = &dmc_sel2.hw,
};
/* Convenience table to populate regmap in .probe */
@@ -2190,6 +2189,11 @@ static struct regmap_config a1_periphs_regmap_cfg = {
.reg_stride = 4,
};
static struct meson_clk_hw_data a1_periphs_clks = {
.hws = a1_periphs_hw_clks,
.num = ARRAY_SIZE(a1_periphs_hw_clks),
};
static int meson_a1_periphs_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -2219,8 +2223,7 @@ static int meson_a1_periphs_probe(struct platform_device *pdev)
clkid);
}
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
&a1_periphs_clks);
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &a1_periphs_clks);
}
static const struct of_device_id a1_periphs_clkc_match_table[] = {

67
drivers/clk/meson/a1-peripherals.h
View File

@@ -43,71 +43,4 @@
#define PSRAM_CLK_CTRL 0xf4
#define DMC_CLK_CTRL 0xf8
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
/*
* CLKID index values for internal clocks
*
* These indices are entirely contrived and do not map onto the hardware.
* It has now been decided to expose everything by default in the DT header:
* include/dt-bindings/clock/a1-peripherals-clkc.h.
* Only the clocks ids we don't want to expose, such as the internal muxes and
* dividers of composite clocks, will remain defined here.
*/
#define CLKID_XTAL_IN 0
#define CLKID_DSPA_SEL 61
#define CLKID_DSPB_SEL 62
#define CLKID_SARADC_SEL 74
#define CLKID_SYS_A_SEL 89
#define CLKID_SYS_A_DIV 90
#define CLKID_SYS_A 91
#define CLKID_SYS_B_SEL 92
#define CLKID_SYS_B_DIV 93
#define CLKID_SYS_B 94
#define CLKID_DSPA_A_DIV 96
#define CLKID_DSPA_A 97
#define CLKID_DSPA_B_DIV 99
#define CLKID_DSPA_B 100
#define CLKID_DSPB_A_DIV 102
#define CLKID_DSPB_A 103
#define CLKID_DSPB_B_DIV 105
#define CLKID_DSPB_B 106
#define CLKID_RTC_32K_IN 107
#define CLKID_RTC_32K_DIV 108
#define CLKID_RTC_32K_XTAL 109
#define CLKID_RTC_32K_SEL 110
#define CLKID_CECB_32K_IN 111
#define CLKID_CECB_32K_DIV 112
#define CLKID_CECA_32K_IN 115
#define CLKID_CECA_32K_DIV 116
#define CLKID_DIV2_PRE 119
#define CLKID_24M_DIV2 120
#define CLKID_GEN_DIV 122
#define CLKID_SARADC_DIV 123
#define CLKID_PWM_A_DIV 125
#define CLKID_PWM_B_DIV 127
#define CLKID_PWM_C_DIV 129
#define CLKID_PWM_D_DIV 131
#define CLKID_PWM_E_DIV 133
#define CLKID_PWM_F_DIV 135
#define CLKID_SPICC_SEL 136
#define CLKID_SPICC_DIV 137
#define CLKID_SPICC_SEL2 138
#define CLKID_TS_DIV 139
#define CLKID_SPIFC_SEL 140
#define CLKID_SPIFC_DIV 141
#define CLKID_SPIFC_SEL2 142
#define CLKID_USB_BUS_SEL 143
#define CLKID_USB_BUS_DIV 144
#define CLKID_SD_EMMC_SEL 145
#define CLKID_SD_EMMC_DIV 146
#define CLKID_PSRAM_SEL 148
#define CLKID_PSRAM_DIV 149
#define CLKID_PSRAM_SEL2 150
#define CLKID_DMC_SEL 151
#define CLKID_DMC_DIV 152
#define CLKID_DMC_SEL2 153
#define NR_CLKS 154
#endif /* __A1_PERIPHERALS_H */

38
drivers/clk/meson/a1-pll.c
View File

@@ -12,6 +12,9 @@
#include <linux/platform_device.h>
#include "a1-pll.h"
#include "clk-regmap.h"
#include "meson-clkc-utils.h"
#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
static struct clk_regmap fixed_pll_dco = {
.data = &(struct meson_clk_pll_data){
@@ -268,22 +271,18 @@ static struct clk_regmap fclk_div7 = {
};
/* Array of all clocks registered by this provider */
static struct clk_hw_onecell_data a1_pll_clks = {
.hws = {
[CLKID_FIXED_PLL_DCO] = &fixed_pll_dco.hw,
[CLKID_FIXED_PLL] = &fixed_pll.hw,
[CLKID_FCLK_DIV2_DIV] = &fclk_div2_div.hw,
[CLKID_FCLK_DIV3_DIV] = &fclk_div3_div.hw,
[CLKID_FCLK_DIV5_DIV] = &fclk_div5_div.hw,
[CLKID_FCLK_DIV7_DIV] = &fclk_div7_div.hw,
[CLKID_FCLK_DIV2] = &fclk_div2.hw,
[CLKID_FCLK_DIV3] = &fclk_div3.hw,
[CLKID_FCLK_DIV5] = &fclk_div5.hw,
[CLKID_FCLK_DIV7] = &fclk_div7.hw,
[CLKID_HIFI_PLL] = &hifi_pll.hw,
[NR_PLL_CLKS] = NULL,
},
.num = NR_PLL_CLKS,
static struct clk_hw *a1_pll_hw_clks[] = {
[CLKID_FIXED_PLL_DCO] = &fixed_pll_dco.hw,
[CLKID_FIXED_PLL] = &fixed_pll.hw,
[CLKID_FCLK_DIV2_DIV] = &fclk_div2_div.hw,
[CLKID_FCLK_DIV3_DIV] = &fclk_div3_div.hw,
[CLKID_FCLK_DIV5_DIV] = &fclk_div5_div.hw,
[CLKID_FCLK_DIV7_DIV] = &fclk_div7_div.hw,
[CLKID_FCLK_DIV2] = &fclk_div2.hw,
[CLKID_FCLK_DIV3] = &fclk_div3.hw,
[CLKID_FCLK_DIV5] = &fclk_div5.hw,
[CLKID_FCLK_DIV7] = &fclk_div7.hw,
[CLKID_HIFI_PLL] = &hifi_pll.hw,
};
static struct clk_regmap *const a1_pll_regmaps[] = {
@@ -302,6 +301,11 @@ static struct regmap_config a1_pll_regmap_cfg = {
.reg_stride = 4,
};
static struct meson_clk_hw_data a1_pll_clks = {
.hws = a1_pll_hw_clks,
.num = ARRAY_SIZE(a1_pll_hw_clks),
};
static int meson_a1_pll_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -332,7 +336,7 @@ static int meson_a1_pll_probe(struct platform_device *pdev)
clkid);
}
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get,
&a1_pll_clks);
}

19
drivers/clk/meson/a1-pll.h
View File

@@ -25,23 +25,4 @@
#define ANACTRL_HIFIPLL_CTRL4 0xd0
#define ANACTRL_HIFIPLL_STS 0xd4
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
/*
* CLKID index values for internal clocks
*
* These indices are entirely contrived and do not map onto the hardware.
* It has now been decided to expose everything by default in the DT header:
* include/dt-bindings/clock/a1-pll-clkc.h. Only the clocks ids we don't want
* to expose, such as the internal muxes and dividers of composite clocks,
* will remain defined here.
*/
#define CLKID_FIXED_PLL_DCO 0
#define CLKID_FCLK_DIV2_DIV 2
#define CLKID_FCLK_DIV3_DIV 3
#define CLKID_FCLK_DIV5_DIV 4
#define CLKID_FCLK_DIV7_DIV 5
#define NR_PLL_CLKS 11
#endif /* __A1_PLL_H */

48
drivers/clk/meson/axg-aoclk.c
View File

@@ -14,11 +14,13 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include "meson-aoclk.h"
#include "axg-aoclk.h"
#include "clk-regmap.h"
#include "clk-dualdiv.h"
#include <dt-bindings/clock/axg-aoclkc.h>
#include <dt-bindings/reset/axg-aoclkc.h>
/*
* AO Configuration Clock registers offsets
* Register offsets from the data sheet must be multiplied by 4.
@@ -288,27 +290,24 @@ static struct clk_regmap *axg_aoclk_regmap[] = {
&axg_aoclk_saradc_gate,
};
static const struct clk_hw_onecell_data axg_aoclk_onecell_data = {
.hws = {
[CLKID_AO_REMOTE] = &axg_aoclk_remote.hw,
[CLKID_AO_I2C_MASTER] = &axg_aoclk_i2c_master.hw,
[CLKID_AO_I2C_SLAVE] = &axg_aoclk_i2c_slave.hw,
[CLKID_AO_UART1] = &axg_aoclk_uart1.hw,
[CLKID_AO_UART2] = &axg_aoclk_uart2.hw,
[CLKID_AO_IR_BLASTER] = &axg_aoclk_ir_blaster.hw,
[CLKID_AO_SAR_ADC] = &axg_aoclk_saradc.hw,
[CLKID_AO_CLK81] = &axg_aoclk_clk81.hw,
[CLKID_AO_SAR_ADC_SEL] = &axg_aoclk_saradc_mux.hw,
[CLKID_AO_SAR_ADC_DIV] = &axg_aoclk_saradc_div.hw,
[CLKID_AO_SAR_ADC_CLK] = &axg_aoclk_saradc_gate.hw,
[CLKID_AO_CTS_OSCIN] = &axg_aoclk_cts_oscin.hw,
[CLKID_AO_32K_PRE] = &axg_aoclk_32k_pre.hw,
[CLKID_AO_32K_DIV] = &axg_aoclk_32k_div.hw,
[CLKID_AO_32K_SEL] = &axg_aoclk_32k_sel.hw,
[CLKID_AO_32K] = &axg_aoclk_32k.hw,
[CLKID_AO_CTS_RTC_OSCIN] = &axg_aoclk_cts_rtc_oscin.hw,
},
.num = NR_CLKS,
static struct clk_hw *axg_aoclk_hw_clks[] = {
[CLKID_AO_REMOTE] = &axg_aoclk_remote.hw,
[CLKID_AO_I2C_MASTER] = &axg_aoclk_i2c_master.hw,
[CLKID_AO_I2C_SLAVE] = &axg_aoclk_i2c_slave.hw,
[CLKID_AO_UART1] = &axg_aoclk_uart1.hw,
[CLKID_AO_UART2] = &axg_aoclk_uart2.hw,
[CLKID_AO_IR_BLASTER] = &axg_aoclk_ir_blaster.hw,
[CLKID_AO_SAR_ADC] = &axg_aoclk_saradc.hw,
[CLKID_AO_CLK81] = &axg_aoclk_clk81.hw,
[CLKID_AO_SAR_ADC_SEL] = &axg_aoclk_saradc_mux.hw,
[CLKID_AO_SAR_ADC_DIV] = &axg_aoclk_saradc_div.hw,
[CLKID_AO_SAR_ADC_CLK] = &axg_aoclk_saradc_gate.hw,
[CLKID_AO_CTS_OSCIN] = &axg_aoclk_cts_oscin.hw,
[CLKID_AO_32K_PRE] = &axg_aoclk_32k_pre.hw,
[CLKID_AO_32K_DIV] = &axg_aoclk_32k_div.hw,
[CLKID_AO_32K_SEL] = &axg_aoclk_32k_sel.hw,
[CLKID_AO_32K] = &axg_aoclk_32k.hw,
[CLKID_AO_CTS_RTC_OSCIN] = &axg_aoclk_cts_rtc_oscin.hw,
};
static const struct meson_aoclk_data axg_aoclkc_data = {
@@ -317,7 +316,10 @@ static const struct meson_aoclk_data axg_aoclkc_data = {
.reset = axg_aoclk_reset,
.num_clks = ARRAY_SIZE(axg_aoclk_regmap),
.clks = axg_aoclk_regmap,
.hw_data = &axg_aoclk_onecell_data,
.hw_clks = {
.hws = axg_aoclk_hw_clks,
.num = ARRAY_SIZE(axg_aoclk_hw_clks),
},
};
static const struct of_device_id axg_aoclkc_match_table[] = {

18
drivers/clk/meson/axg-aoclk.h
View File

@@ -1,18 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2017 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*
* Copyright (c) 2018 Amlogic, inc.
* Author: Qiufang Dai <qiufang.dai@amlogic.com>
*/
#ifndef __AXG_AOCLKC_H
#define __AXG_AOCLKC_H
#define NR_CLKS 17
#include <dt-bindings/clock/axg-aoclkc.h>
#include <dt-bindings/reset/axg-aoclkc.h>
#endif /* __AXG_AOCLKC_H */

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