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meson64: 6.18: drop cacheref S922X fix patch as it landed on 6.18.2 (#9100)

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This commit is contained in:
Ricardo Pardini
2025-12-18 19:08:41 +01:00
committed by GitHub
parent 13c79f67fe
commit de044ed362
1 changed files with 0 additions and 44 deletions
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44
patch/kernel/archive/meson64-6.18/x-PATCH-arm64-dts-amlogic-meson-g12b-Fix-L2-cache-reference-for-S922X-CPUs.patch
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@@ -1,44 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Guillaume La Roque <glaroque@baylibre.com>
Date: Sun, 23 Nov 2025 18:14:10 +0100
Subject: [PATCH] arm64: dts: amlogic: meson-g12b: Fix L2 cache reference
for S922X CPUs
The original addition of cache information for the Amlogic S922X SoC
used the wrong next-level cache node for CPU cores 100 and 101,
incorrectly referencing `l2_cache_l`. These cores actually belong to
the big cluster and should reference `l2_cache_b`. Update the device
tree accordingly.
Fixes: e7f85e6c155a ("arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC")
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
index f04efa828256..23358d94844c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
@@ -87,7 +87,7 @@ cpu100: cpu@100 {
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
- next-level-cache = <&l2_cache_l>;
+ next-level-cache = <&l2_cache_b>;
#cooling-cells = <2>;
};
@@ -103,7 +103,7 @@ cpu101: cpu@101 {
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
- next-level-cache = <&l2_cache_l>;
+ next-level-cache = <&l2_cache_b>;
#cooling-cells = <2>;
};
--
2.34.1