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rockchip-rk3588-edge: refresh HDMI TX & RX patches from Collabora and add Hantro VPU back

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This commit is contained in:
Muhammed Efe Cetin
2024-07-29 16:16:06 +03:00
committed by Igor
parent 53396d202c
commit b9d7bd9e5b
17 changed files with 4859 additions and 7795 deletions
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8
config/kernel/linux-rockchip-rk3588-6.11.config
View File

@@ -4404,6 +4404,7 @@ CONFIG_HW_RANDOM_VIRTIO=m
CONFIG_HW_RANDOM_OPTEE=m
# CONFIG_HW_RANDOM_CCTRNG is not set
# CONFIG_HW_RANDOM_XIPHERA is not set
CONFIG_HW_RANDOM_ROCKCHIP=m
CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m
CONFIG_HW_RANDOM_CN10K=y
# CONFIG_APPLICOM is not set
@@ -5909,6 +5910,8 @@ CONFIG_VIDEO_ROCKCHIP_ISP1=m
#
# Sunxi media platform drivers
#
CONFIG_VIDEO_SYNOPSYS_HDMIRX=m
CONFIG_HDMIRX_LOAD_DEFAULT_EDID=y
#
# Texas Instruments drivers
@@ -6490,6 +6493,7 @@ CONFIG_ROCKCHIP_VOP2=y
CONFIG_ROCKCHIP_ANALOGIX_DP=y
CONFIG_ROCKCHIP_CDN_DP=y
CONFIG_ROCKCHIP_DW_HDMI=y
CONFIG_ROCKCHIP_DW_HDMI_QP=y
CONFIG_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_ROCKCHIP_INNO_HDMI=y
CONFIG_ROCKCHIP_LVDS=y
@@ -6660,6 +6664,7 @@ CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set
CONFIG_DRM_DW_HDMI_CEC=m
CONFIG_DRM_DW_HDMI_QP=m
CONFIG_DRM_DW_MIPI_DSI=m
# end of Display Interface Bridges
@@ -8472,6 +8477,7 @@ CONFIG_DVB_AV7110_OSD=y
CONFIG_DVB_SP8870=m
# CONFIG_VIDEO_MAX96712 is not set
CONFIG_VIDEO_ROCKCHIP_VDEC=m
CONFIG_VIDEO_ROCKCHIP_VDEC2=m
#
# StarFive media platform drivers
@@ -10443,6 +10449,8 @@ CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m
CONFIG_CRYPTO_DEV_CAVIUM_ZIP=m
CONFIG_CRYPTO_DEV_ROCKCHIP=m
# CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG is not set
CONFIG_CRYPTO_DEV_ROCKCHIP2=m
# CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG is not set
CONFIG_CRYPTO_DEV_VIRTIO=m
CONFIG_CRYPTO_DEV_SAFEXCEL=m
CONFIG_CRYPTO_DEV_CCREE=m

76
patch/kernel/archive/rockchip-rk3588-6.11/0024-RK3588-Add-Crypto-Support.patch
View File

@@ -1,19 +1,21 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From a0ba8a456c62483e2b8fbbf021fd5ca4ffa07fe8 Mon Sep 17 00:00:00 2001
From: Corentin Labbe <clabbe@baylibre.com>
Date: Tue, 7 Nov 2023 15:55:27 +0000
Subject: dt-bindings: crypto: add support for rockchip,crypto-rk3588
Subject: [PATCH 1/4] dt-bindings: crypto: add support for
rockchip,crypto-rk3588
Add device tree binding documentation for the Rockchip cryptographic
offloader V2.
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
---
Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml | 65 ++++++++++
.../crypto/rockchip,rk3588-crypto.yaml | 65 +++++++++++++++++++
1 file changed, 65 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml
diff --git a/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml b/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml
new file mode 100644
index 000000000000..111111111111
index 000000000000..c01963413260
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml
@@ -0,0 +1,65 @@
@@ -83,12 +85,13 @@ index 000000000000..111111111111
+ reset-names = "core";
+ };
--
Armbian
2.45.2
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From b9c55c60a732b7d05b6344289091218f7dcb9208 Mon Sep 17 00:00:00 2001
From: Corentin Labbe <clabbe@baylibre.com>
Date: Tue, 7 Nov 2023 15:55:30 +0000
Subject: ARM64: dts: rk356x: add crypto node
Subject: [PATCH 2/4] ARM64: dts: rk356x: add crypto node
Both RK3566 and RK3568 have a crypto IP handled by the rk3588 crypto driver so adds a
node for it.
@@ -96,11 +99,11 @@ node for it.
Tested-by: Ricardo Pardini <ricardo@pardini.net>
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 12 ++++++++++
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 111111111111..222222222222 100644
index 4690be841a1c..50d1c42b6740 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -1113,6 +1113,18 @@ sdhci: mmc@fe310000 {
@@ -123,12 +126,13 @@ index 111111111111..222222222222 100644
compatible = "rockchip,rk3568-i2s-tdm";
reg = <0x0 0xfe400000 0x0 0x1000>;
--
Armbian
2.45.2
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From 9e082adac7e03d2ffe78b49f92e556a4a70e0ee8 Mon Sep 17 00:00:00 2001
From: Corentin Labbe <clabbe@baylibre.com>
Date: Tue, 7 Nov 2023 15:55:31 +0000
Subject: reset: rockchip: secure reset must be used by SCMI
Subject: [PATCH 3/4] reset: rockchip: secure reset must be used by SCMI
While working on the rk3588 crypto driver, I loose lot of time
understanding why resetting the IP failed.
@@ -138,12 +142,12 @@ All resets in this block must be handled via SCMI call.
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
---
drivers/clk/rockchip/rst-rk3588.c | 42 ------
include/dt-bindings/reset/rockchip,rk3588-cru.h | 68 +++++-----
drivers/clk/rockchip/rst-rk3588.c | 42 ------------
.../dt-bindings/reset/rockchip,rk3588-cru.h | 68 +++++++++----------
2 files changed, 34 insertions(+), 76 deletions(-)
diff --git a/drivers/clk/rockchip/rst-rk3588.c b/drivers/clk/rockchip/rst-rk3588.c
index 111111111111..222222222222 100644
index c4ebc01f1c9c..7a856de64d9e 100644
--- a/drivers/clk/rockchip/rst-rk3588.c
+++ b/drivers/clk/rockchip/rst-rk3588.c
@@ -16,9 +16,6 @@
@@ -203,7 +207,7 @@ index 111111111111..222222222222 100644
void rk3588_rst_init(struct device_node *np, void __iomem *reg_base)
diff --git a/include/dt-bindings/reset/rockchip,rk3588-cru.h b/include/dt-bindings/reset/rockchip,rk3588-cru.h
index 111111111111..222222222222 100644
index e2fe4bd5f7f0..b74f1046f5a5 100644
--- a/include/dt-bindings/reset/rockchip,rk3588-cru.h
+++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h
@@ -716,40 +716,40 @@
@@ -282,12 +286,13 @@ index 111111111111..222222222222 100644
#define SRST_A_HDMIRX_BIU 660
--
Armbian
2.45.2
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From 8e6f2d80ad933db9d542a9d08a9f733341e65b90 Mon Sep 17 00:00:00 2001
From: Corentin Labbe <clabbe@baylibre.com>
Date: Tue, 7 Nov 2023 15:55:32 +0000
Subject: crypto: rockchip: add rk3588 driver
Subject: [PATCH 4/4] crypto: rockchip: add rk3588 driver
RK3588 have a new crypto IP, this patch adds basic support for it.
Only hashes and cipher are handled for the moment.
@@ -296,14 +301,18 @@ Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
---
drivers/crypto/Kconfig | 29 +
drivers/crypto/rockchip/Makefile | 5 +
drivers/crypto/rockchip/rk2_crypto.c | 739 ++++++++++
drivers/crypto/rockchip/rk2_crypto.h | 246 +++
drivers/crypto/rockchip/rk2_crypto_ahash.c | 344 +++++
drivers/crypto/rockchip/rk2_crypto_skcipher.c | 576 ++++++++
6 files changed, 1939 insertions(+)
drivers/crypto/rockchip/rk2_crypto.c | 738 ++++++++++++++++++
drivers/crypto/rockchip/rk2_crypto.h | 246 ++++++
drivers/crypto/rockchip/rk2_crypto_ahash.c | 344 ++++++++
drivers/crypto/rockchip/rk2_crypto_skcipher.c | 576 ++++++++++++++
6 files changed, 1938 insertions(+)
create mode 100644 drivers/crypto/rockchip/rk2_crypto.c
create mode 100644 drivers/crypto/rockchip/rk2_crypto.h
create mode 100644 drivers/crypto/rockchip/rk2_crypto_ahash.c
create mode 100644 drivers/crypto/rockchip/rk2_crypto_skcipher.c
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 111111111111..222222222222 100644
index 94f23c6fc93b..95d700c88161 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -653,6 +653,35 @@ config CRYPTO_DEV_TEGRA
@@ -343,7 +352,7 @@ index 111111111111..222222222222 100644
tristate "Support for Xilinx ZynqMP AES hw accelerator"
depends on ZYNQMP_FIRMWARE || COMPILE_TEST
diff --git a/drivers/crypto/rockchip/Makefile b/drivers/crypto/rockchip/Makefile
index 111111111111..222222222222 100644
index 785277aca71e..452a12ff6538 100644
--- a/drivers/crypto/rockchip/Makefile
+++ b/drivers/crypto/rockchip/Makefile
@@ -3,3 +3,8 @@ obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rk_crypto.o
@@ -357,10 +366,10 @@ index 111111111111..222222222222 100644
+ rk2_crypto_ahash.o
diff --git a/drivers/crypto/rockchip/rk2_crypto.c b/drivers/crypto/rockchip/rk2_crypto.c
new file mode 100644
index 000000000000..111111111111
index 000000000000..bac7cc39c403
--- /dev/null
+++ b/drivers/crypto/rockchip/rk2_crypto.c
@@ -0,0 +1,739 @@
@@ -0,0 +1,738 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * hardware cryptographic offloader for RK3568/RK3588 SoC
@@ -1063,7 +1072,7 @@ index 000000000000..111111111111
+ return err;
+}
+
+static int rk2_crypto_remove(struct platform_device *pdev)
+static void rk2_crypto_remove(struct platform_device *pdev)
+{
+ struct rk2_crypto_dev *rkc = platform_get_drvdata(pdev);
+ struct rk2_crypto_dev *first;
@@ -1082,7 +1091,6 @@ index 000000000000..111111111111
+ }
+ rk2_crypto_pm_exit(rkc);
+ crypto_engine_exit(rkc->engine);
+ return 0;
+}
+
+static struct platform_driver crypto_driver = {
@@ -1102,7 +1110,7 @@ index 000000000000..111111111111
+MODULE_AUTHOR("Corentin Labbe <clabbe@baylibre.com>");
diff --git a/drivers/crypto/rockchip/rk2_crypto.h b/drivers/crypto/rockchip/rk2_crypto.h
new file mode 100644
index 000000000000..111111111111
index 000000000000..59cd8be59f70
--- /dev/null
+++ b/drivers/crypto/rockchip/rk2_crypto.h
@@ -0,0 +1,246 @@
@@ -1354,7 +1362,7 @@ index 000000000000..111111111111
+void rk2_hash_exit_tfm(struct crypto_ahash *tfm);
diff --git a/drivers/crypto/rockchip/rk2_crypto_ahash.c b/drivers/crypto/rockchip/rk2_crypto_ahash.c
new file mode 100644
index 000000000000..111111111111
index 000000000000..75b8d9893447
--- /dev/null
+++ b/drivers/crypto/rockchip/rk2_crypto_ahash.c
@@ -0,0 +1,344 @@
@@ -1704,7 +1712,7 @@ index 000000000000..111111111111
+}
diff --git a/drivers/crypto/rockchip/rk2_crypto_skcipher.c b/drivers/crypto/rockchip/rk2_crypto_skcipher.c
new file mode 100644
index 000000000000..111111111111
index 000000000000..3e8e44d84b47
--- /dev/null
+++ b/drivers/crypto/rockchip/rk2_crypto_skcipher.c
@@ -0,0 +1,576 @@
@@ -2285,5 +2293,5 @@ index 000000000000..111111111111
+ crypto_free_skcipher(ctx->fallback_tfm);
+}
--
Armbian
2.45.2

317
patch/kernel/archive/rockchip-rk3588-6.11/0026-RK3588-Add-VPU121-H.264-Decoder-Support.patch
View File

@@ -1,9 +1,7 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 13 Jun 2024 15:48:42 +0200
Subject: media: dt-bindings: rk3568-vepu: Add RK3588 VEPU121
From 74ffd5840cdacdb030246e79a2485016296d73f5 Mon Sep 17 00:00:00 2001
From: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
Date: Thu, 18 Apr 2024 16:15:05 +0200
Subject: [PATCH 1/7] media: dt-bindings: rk3568-vepu: Add RK3588 VEPU121
This encoder-only device is present four times on this SoC, and should
support everything the rk3568 vepu supports (so JPEG, H.264 and VP8
@@ -12,13 +10,14 @@ systems might already support RK3568 VEPU and want to avoid registering
four of them separately considering they can be used as a cluster.
Signed-off-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml | 1 +
.../devicetree/bindings/media/rockchip,rk3568-vepu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml b/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml
index 111111111111..222222222222 100644
index 9d90d8d0565a..947ad699cc5e 100644
--- a/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml
+++ b/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml
@@ -17,6 +17,7 @@ properties:
@@ -30,12 +29,49 @@ index 111111111111..222222222222 100644
reg:
maxItems: 1
--
Armbian
2.46.0
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From 936c9b832deddee07a229c3ad19d0e284d2b7d4a Mon Sep 17 00:00:00 2001
From: Jianfeng Liu <liujianfeng1994@gmail.com>
Date: Tue, 30 Apr 2024 10:40:01 +0800
Subject: [PATCH 2/7] media: dt-bindings: rockchip-vpu: Add RK3588 VPU121
RK3588 has four Hantro H1 VEPUs (encoder-only) modules and one combined
Hantro H1/G1 VPU (decoder and encoder). These are not described as
separate IP, since they are sharing an internal cache. This adds the
RK3588 specific compatible string for the combined VPU, which seems to
be identical to the version found in the RK3568.
Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
Documentation/devicetree/bindings/media/rockchip-vpu.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
index c57e1f488895..2710bb2fb0d1 100644
--- a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
+++ b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
@@ -31,6 +31,9 @@ properties:
- items:
- const: rockchip,rk3228-vpu
- const: rockchip,rk3399-vpu
+ - items:
+ - const: rockchip,rk3588-vpu121
+ - const: rockchip,rk3568-vpu
reg:
maxItems: 1
--
2.46.0
From 5199fc492e1d0d8ce04ffd251cdf0af87f02fbf3 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 13 Jun 2024 15:48:44 +0200
Subject: media: hantro: Disable multicore support
Date: Thu, 13 Jun 2024 14:29:55 +0200
Subject: [PATCH 3/7] media: hantro: Disable multicore support
Avoid exposing equal Hantro video codecs to userspace. Equal video
codecs allow scheduling work between the cores. For that kernel support
@@ -48,14 +84,14 @@ cores), but applies to all SoCs.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/media/platform/verisilicon/hantro_drv.c | 37 ++++++++++
1 file changed, 37 insertions(+)
.../media/platform/verisilicon/hantro_drv.c | 47 +++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c
index 111111111111..222222222222 100644
index 34b123dafd89..748187623990 100644
--- a/drivers/media/platform/verisilicon/hantro_drv.c
+++ b/drivers/media/platform/verisilicon/hantro_drv.c
@@ -992,6 +992,39 @@ static const struct media_device_ops hantro_m2m_media_ops = {
@@ -992,6 +992,49 @@ static const struct media_device_ops hantro_m2m_media_ops = {
.req_queue = v4l2_m2m_request_queue,
};
@@ -70,8 +106,9 @@ index 111111111111..222222222222 100644
+ */
+static int hantro_disable_multicore(struct hantro_dev *vpu)
+{
+ struct device_node *node = NULL;
+ const char *compatible;
+ struct device_node *node;
+ bool is_main_core;
+ int ret;
+
+ /* Intentionally ignores the fallback strings */
@@ -79,12 +116,21 @@ index 111111111111..222222222222 100644
+ if (ret)
+ return ret;
+
+ /* first compatible node found from the root node is considered the main core */
+ node = of_find_compatible_node(NULL, NULL, compatible);
+ if (!node)
+ return -EINVAL; /* broken DT? */
+ /* The first compatible and available node found is considered the main core */
+ do {
+ node = of_find_compatible_node(node, NULL, compatible);
+ if (of_device_is_available(node))
+ break;
+ } while (node);
+
+ if (vpu->dev->of_node != node) {
+ if (!node)
+ return -EINVAL;
+
+ is_main_core = (vpu->dev->of_node == node);
+
+ of_node_put(node);
+
+ if (!is_main_core) {
+ dev_info(vpu->dev, "missing multi-core support, ignoring this instance\n");
+ return -ENODEV;
+ }
@@ -95,7 +141,7 @@ index 111111111111..222222222222 100644
static int hantro_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
@@ -1011,6 +1044,10 @@ static int hantro_probe(struct platform_device *pdev)
@@ -1011,6 +1054,10 @@ static int hantro_probe(struct platform_device *pdev)
match = of_match_node(of_hantro_match, pdev->dev.of_node);
vpu->variant = match->data;
@@ -107,12 +153,13 @@ index 111111111111..222222222222 100644
* Support for nxp,imx8mq-vpu is kept for backwards compatibility
* but it's deprecated. Please update your DTS file to use
--
Armbian
2.46.0
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From bb294970b29147116b8d6699c05e1c51f9b3a746 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Thu, 13 Jun 2024 15:48:45 +0200
Subject: media: hantro: Add RK3588 VEPU121
Date: Thu, 13 Jun 2024 14:48:43 +0200
Subject: [PATCH 4/7] media: hantro: Add RK3588 VEPU121
RK3588 handling is exactly the same as RK3568. This is not
handled using fallback compatibles to avoid exposing multiple
@@ -125,7 +172,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
1 file changed, 1 insertion(+)
diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c
index 111111111111..222222222222 100644
index 748187623990..05bbac853c4f 100644
--- a/drivers/media/platform/verisilicon/hantro_drv.c
+++ b/drivers/media/platform/verisilicon/hantro_drv.c
@@ -722,6 +722,7 @@ static const struct of_device_id of_hantro_match[] = {
@@ -137,5 +184,219 @@ index 111111111111..222222222222 100644
#endif
#ifdef CONFIG_VIDEO_HANTRO_IMX8M
--
Armbian
2.46.0
From 9820579abb632ea927e6e693ea8f9ea9fc2a90c5 Mon Sep 17 00:00:00 2001
From: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
Date: Wed, 5 Jun 2024 15:28:33 +0200
Subject: [PATCH 5/7] arm64: dts: rockchip: Add VEPU121 to RK3588
RK3588 has 4 Hantro G1 encoder-only cores. They are all independent IP,
but can be used as a cluster (i.e. sharing work between the cores).
These cores are called VEPU121 in the TRM. The TRM describes one more
VEPU121, but that is combined with a Hantro H1. That one will be handled
using the VPU binding instead.
Signed-off-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 80 +++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index b6e4df180f0b..595f129a2d8c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1122,6 +1122,86 @@ power-domain@RK3588_PD_SDMMC {
};
};
+ vepu121_0: video-codec@fdba0000 {
+ compatible = "rockchip,rk3588-vepu121";
+ reg = <0x0 0xfdba0000 0x0 0x800>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vepu121_0_mmu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ };
+
+ vepu121_0_mmu: iommu@fdba0800 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdba0800 0x0 0x40>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ };
+
+ vepu121_1: video-codec@fdba4000 {
+ compatible = "rockchip,rk3588-vepu121";
+ reg = <0x0 0xfdba4000 0x0 0x800>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vepu121_1_mmu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ };
+
+ vepu121_1_mmu: iommu@fdba4800 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdba4800 0x0 0x40>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ };
+
+ vepu121_2: video-codec@fdba8000 {
+ compatible = "rockchip,rk3588-vepu121";
+ reg = <0x0 0xfdba8000 0x0 0x800>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vepu121_2_mmu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ };
+
+ vepu121_2_mmu: iommu@fdba8800 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdba8800 0x0 0x40>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ };
+
+ vepu121_3: video-codec@fdbac000 {
+ compatible = "rockchip,rk3588-vepu121";
+ reg = <0x0 0xfdbac000 0x0 0x800>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vepu121_3_mmu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ };
+
+ vepu121_3_mmu: iommu@fdbac800 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdbac800 0x0 0x40>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ };
+
av1d: video-codec@fdc70000 {
compatible = "rockchip,rk3588-av1-vpu";
reg = <0x0 0xfdc70000 0x0 0x800>;
--
2.46.0
From 9abdf23677ceaf0f2b2984ba4adf8105dbd2df25 Mon Sep 17 00:00:00 2001
From: Jianfeng Liu <liujianfeng1994@gmail.com>
Date: Tue, 30 Apr 2024 10:40:02 +0800
Subject: [PATCH 6/7] arm64: dts: rockchip: Add VPU121 support for RK3588
Enable Hantro G1 video decoder in RK3588's devicetree.
Tested with FFmpeg v4l2_request code taken from [1]
with MPEG2, H.264 and VP8 samples.
[1] https://github.com/LibreELEC/LibreELEC.tv/blob/master/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch
Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
Tested-by: Hugh Cole-Baker <sigmaris@gmail.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 595f129a2d8c..14b8d8691255 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1122,6 +1122,27 @@ power-domain@RK3588_PD_SDMMC {
};
};
+ vpu121: video-codec@fdb50000 {
+ compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu";
+ reg = <0x0 0xfdb50000 0x0 0x800>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vdpu";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vpu121_mmu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ };
+
+ vpu121_mmu: iommu@fdb50800 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdb50800 0x0 0x40>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-names = "aclk", "iface";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ };
+
vepu121_0: video-codec@fdba0000 {
compatible = "rockchip,rk3588-vepu121";
reg = <0x0 0xfdba0000 0x0 0x800>;
--
2.46.0
From 64cf83f3ee9ac0a7987e2354d6b4a6875be6b7dc Mon Sep 17 00:00:00 2001
From: Muhammed Efe Cetin <efectn@protonmail.com>
Date: Mon, 29 Jul 2024 23:21:19 +0300
Subject: [PATCH 7/7] arm64: dts: rockchip: rk3588: disable H264 decoding on
Hantro decoder
---
Documentation/devicetree/bindings/media/rockchip-vpu.yaml | 2 +-
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 7 ++++---
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
index 2710bb2fb0d1..1da7700e4a55 100644
--- a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
+++ b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
@@ -33,7 +33,7 @@ properties:
- const: rockchip,rk3399-vpu
- items:
- const: rockchip,rk3588-vpu121
- - const: rockchip,rk3568-vpu
+ - const: rockchip,rk3399-vpu
reg:
maxItems: 1
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 14b8d8691255..ee5e6c45f601 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1123,10 +1123,11 @@ power-domain@RK3588_PD_SDMMC {
};
vpu121: video-codec@fdb50000 {
- compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu";
+ compatible = "rockchip,rk3588-vpu121", "rockchip,rk3399-vpu";
reg = <0x0 0xfdb50000 0x0 0x800>;
- interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vdpu";
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vepu", "vdpu";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "hclk";
iommus = <&vpu121_mmu>;
--
2.46.0

1492
patch/kernel/archive/rockchip-rk3588-6.11/0027-RK3588-Add-rkvdec2-Support-v3.patch
View File

File diff suppressed because it is too large Load Diff

0
patch/kernel/archive/rockchip-rk3588-6.11/0147-arm64-dts-rockchip-rk3588-add-RGA2-node.patch → patch/kernel/archive/rockchip-rk3588-6.11/0029-arm64-dts-rockchip-rk3588-add-RGA2-node.patch
View File

445
patch/kernel/archive/rockchip-rk3588-6.11/0113-add-synopsys-designware-hdmi-rx-controller.patch
View File

File diff suppressed because it is too large Load Diff

126
patch/kernel/archive/rockchip-rk3588-6.11/0130-phy-phy-rockchip-samsung-hdptx-Enable-runtime-PM.patch Normal file
View File

@@ -0,0 +1,126 @@
From 851c498258fab10b2176df6f237e147b3aa18556 Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Tue, 11 Jun 2024 02:06:10 +0300
Subject: [PATCH 1/2] phy: phy-rockchip-samsung-hdptx: Explicitly include
pm_runtime.h
Driver makes use of helpers from pm_runtime.h, but relies on the header
file being implicitly included.
Explicitly pull the header in to avoid potential build failures in some
configurations.
Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver")
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index 946c01210ac8..3bd9b62b23dc 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -15,6 +15,7 @@
#include <linux/of_platform.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/rational.h>
#include <linux/regmap.h>
#include <linux/reset.h>
--
2.45.2
From 4cff4539ae49d68bdbf005b9b66c62cf0174df13 Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Tue, 11 Jun 2024 02:28:26 +0300
Subject: [PATCH 2/2] phy: phy-rockchip-samsung-hdptx: Enable runtime PM at PHY
core level
When a new PHY is created via [devm_]phy_create(), the runtime PM for it
is not enabled unless the parent device (which creates the PHY) has its
own runtime PM already enabled.
Move the call to devm_pm_runtime_enable() before devm_phy_create() to
enable runtime PM at PHY core level.
With this change the ->power_on() and ->power_off() callbacks do not
require explicit runtime PM management anymore, since the PHY core
handles that via phy_pm_runtime_{get,put}_sync() when phy_power_on() and
phy_power_off() are invoked.
Hence drop the now unnecessary calls to pm_runtime_resume_and_get() and
pm_runtime_put() helpers.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
.../phy/rockchip/phy-rockchip-samsung-hdptx.c | 24 +++++--------------
1 file changed, 6 insertions(+), 18 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index 3bd9b62b23dc..72de287282eb 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -860,7 +860,7 @@ static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx,
static int rk_hdptx_phy_power_on(struct phy *phy)
{
struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
- int ret, bus_width = phy_get_bus_width(hdptx->phy);
+ int bus_width = phy_get_bus_width(hdptx->phy);
/*
* FIXME: Temporary workaround to pass pixel_clk_rate
* from the HDMI bridge driver until phy_configure_opts_hdmi
@@ -871,17 +871,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy)
dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n",
__func__, bus_width, rate);
- ret = pm_runtime_resume_and_get(hdptx->dev);
- if (ret) {
- dev_err(hdptx->dev, "Failed to resume phy: %d\n", ret);
- return ret;
- }
-
- ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
- if (ret)
- pm_runtime_put(hdptx->dev);
-
- return ret;
+ return rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
}
static int rk_hdptx_phy_power_off(struct phy *phy)
@@ -894,8 +884,6 @@ static int rk_hdptx_phy_power_off(struct phy *phy)
if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE))
rk_hdptx_phy_disable(hdptx);
- pm_runtime_put(hdptx->dev);
-
return ret;
}
@@ -977,6 +965,10 @@ static int rk_hdptx_phy_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(hdptx->grf),
"Could not get GRF syscon\n");
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to enable runtime PM\n");
+
hdptx->phy = devm_phy_create(dev, NULL, &rk_hdptx_phy_ops);
if (IS_ERR(hdptx->phy))
return dev_err_probe(dev, PTR_ERR(hdptx->phy),
@@ -986,10 +978,6 @@ static int rk_hdptx_phy_probe(struct platform_device *pdev)
phy_set_drvdata(hdptx->phy, hdptx);
phy_set_bus_width(hdptx->phy, 8);
- ret = devm_pm_runtime_enable(dev);
- if (ret)
- return dev_err_probe(dev, ret, "Failed to enable runtime PM\n");
-
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
if (IS_ERR(phy_provider))
return dev_err_probe(dev, PTR_ERR(phy_provider),
--
2.45.2

326
patch/kernel/archive/rockchip-rk3588-6.11/0131-phy-phy-rockchip-samsung-hdptx-Add-clock-provider.patch Normal file
View File

@@ -0,0 +1,326 @@
From 2ed8602d4c0c5d211163ad1727fd2d76e20407af Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Mon, 19 Feb 2024 21:53:24 +0200
Subject: [PATCH 1/2] dt-bindings: phy: rockchip,rk3588-hdptx-phy: Add
#clock-cells
The HDMI PHY can be used as a clock provider on RK3588 SoC, hence add
the necessary '#clock-cells' property.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
.../devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml
index 54e822c715f3..84fe59dbcf48 100644
--- a/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml
@@ -27,6 +27,9 @@ properties:
- const: ref
- const: apb
+ "#clock-cells":
+ const: 0
+
"#phy-cells":
const: 0
--
2.45.2
From 50108aebe8997fcb0c61e81363024ca8f2ae1fcd Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Tue, 16 Jan 2024 19:27:40 +0200
Subject: [PATCH 2/2] phy: phy-rockchip-samsung-hdptx: Add clock provider
support
The HDMI PHY PLL can be used as an alternative dclk source to RK3588 SoC
CRU. It provides more accurate clock rates required by VOP2 to improve
existing support for display modes handling, which is known to be
problematic when dealing with non-integer refresh rates, among others.
It is worth noting this only works for HDMI 2.0 or below, e.g. cannot be
used to support HDMI 2.1 4K@120Hz mode.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
.../phy/rockchip/phy-rockchip-samsung-hdptx.c | 195 ++++++++++++++++--
1 file changed, 173 insertions(+), 22 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index 72de287282eb..9f084697dd05 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -8,6 +8,7 @@
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
+#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
@@ -191,6 +192,8 @@
#define LN3_TX_SER_RATE_SEL_HBR2 BIT(3)
#define LN3_TX_SER_RATE_SEL_HBR3 BIT(2)
+#define HDMI20_MAX_RATE 600000000
+
struct lcpll_config {
u32 bit_rate;
u8 lcvco_mode_en;
@@ -273,6 +276,12 @@ struct rk_hdptx_phy {
struct clk_bulk_data *clks;
int nr_clks;
struct reset_control_bulk_data rsts[RST_MAX];
+
+ /* clk provider */
+ struct clk_hw hw;
+ unsigned long rate;
+
+ atomic_t usage_count;
};
static const struct ropll_config ropll_tmds_cfg[] = {
@@ -760,6 +769,8 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
struct ropll_config rc = {0};
int i;
+ hdptx->rate = rate * 100;
+
for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
if (rate == ropll_tmds_cfg[i].bit_rate) {
cfg = &ropll_tmds_cfg[i];
@@ -823,19 +834,6 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx,
unsigned int rate)
{
- u32 val;
- int ret;
-
- ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val);
- if (ret)
- return ret;
-
- if (!(val & HDPTX_O_PLL_LOCK_DONE)) {
- ret = rk_hdptx_ropll_tmds_cmn_config(hdptx, rate);
- if (ret)
- return ret;
- }
-
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq);
regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06);
@@ -857,10 +855,68 @@ static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx,
return rk_hdptx_post_enable_lane(hdptx);
}
+static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx,
+ unsigned int rate)
+{
+ u32 status;
+ int ret;
+
+ if (atomic_inc_return(&hdptx->usage_count) > 1)
+ return 0;
+
+ ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status);
+ if (ret)
+ goto dec_usage;
+
+ if (status & HDPTX_O_PLL_LOCK_DONE)
+ dev_warn(hdptx->dev, "PLL locked by unknown consumer!\n");
+
+ if (rate) {
+ ret = rk_hdptx_ropll_tmds_cmn_config(hdptx, rate);
+ if (ret)
+ goto dec_usage;
+ }
+
+ return 0;
+
+dec_usage:
+ atomic_dec(&hdptx->usage_count);
+ return ret;
+}
+
+static int rk_hdptx_phy_consumer_put(struct rk_hdptx_phy *hdptx, bool force)
+{
+ u32 status;
+ int ret;
+
+ ret = atomic_dec_return(&hdptx->usage_count);
+ if (ret > 0)
+ return 0;
+
+ if (ret < 0) {
+ dev_warn(hdptx->dev, "Usage count underflow!\n");
+ ret = -EINVAL;
+ } else {
+ ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status);
+ if (!ret) {
+ if (status & HDPTX_O_PLL_LOCK_DONE)
+ rk_hdptx_phy_disable(hdptx);
+ return 0;
+ } else if (force) {
+ return 0;
+ }
+ }
+
+ atomic_inc(&hdptx->usage_count);
+ return ret;
+}
+
static int rk_hdptx_phy_power_on(struct phy *phy)
{
struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
int bus_width = phy_get_bus_width(hdptx->phy);
+ int ret;
+
/*
* FIXME: Temporary workaround to pass pixel_clk_rate
* from the HDMI bridge driver until phy_configure_opts_hdmi
@@ -871,20 +927,22 @@ static int rk_hdptx_phy_power_on(struct phy *phy)
dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n",
__func__, bus_width, rate);
- return rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
+ ret = rk_hdptx_phy_consumer_get(hdptx, rate);
+ if (ret)
+ return ret;
+
+ ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
+ if (ret)
+ rk_hdptx_phy_consumer_put(hdptx, true);
+
+ return ret;
}
static int rk_hdptx_phy_power_off(struct phy *phy)
{
struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
- u32 val;
- int ret;
- ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val);
- if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE))
- rk_hdptx_phy_disable(hdptx);
-
- return ret;
+ return rk_hdptx_phy_consumer_put(hdptx, false);
}
static const struct phy_ops rk_hdptx_phy_ops = {
@@ -893,6 +951,99 @@ static const struct phy_ops rk_hdptx_phy_ops = {
.owner = THIS_MODULE,
};
+static struct rk_hdptx_phy *to_rk_hdptx_phy(struct clk_hw *hw)
+{
+ return container_of(hw, struct rk_hdptx_phy, hw);
+}
+
+static int rk_hdptx_phy_clk_prepare(struct clk_hw *hw)
+{
+ struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
+
+ return rk_hdptx_phy_consumer_get(hdptx, hdptx->rate / 100);
+}
+
+static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw)
+{
+ struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
+
+ rk_hdptx_phy_consumer_put(hdptx, true);
+}
+
+static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
+
+ return hdptx->rate;
+}
+
+static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ u32 bit_rate = rate / 100;
+ int i;
+
+ if (rate > HDMI20_MAX_RATE)
+ return rate;
+
+ for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
+ if (bit_rate == ropll_tmds_cfg[i].bit_rate)
+ break;
+
+ if (i == ARRAY_SIZE(ropll_tmds_cfg) &&
+ !rk_hdptx_phy_clk_pll_calc(bit_rate, NULL))
+ return -EINVAL;
+
+ return rate;
+}
+
+static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
+
+ return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate / 100);
+}
+
+static const struct clk_ops hdptx_phy_clk_ops = {
+ .prepare = rk_hdptx_phy_clk_prepare,
+ .unprepare = rk_hdptx_phy_clk_unprepare,
+ .recalc_rate = rk_hdptx_phy_clk_recalc_rate,
+ .round_rate = rk_hdptx_phy_clk_round_rate,
+ .set_rate = rk_hdptx_phy_clk_set_rate,
+};
+
+static int rk_hdptx_phy_clk_register(struct rk_hdptx_phy *hdptx)
+{
+ struct device *dev = hdptx->dev;
+ const char *name, *pname;
+ struct clk *refclk;
+ int ret, id;
+
+ refclk = devm_clk_get(dev, "ref");
+ if (IS_ERR(refclk))
+ return dev_err_probe(dev, PTR_ERR(refclk),
+ "Failed to get ref clock\n");
+
+ id = of_alias_get_id(dev->of_node, "hdptxphy");
+ name = id > 0 ? "clk_hdmiphy_pixel1" : "clk_hdmiphy_pixel0";
+ pname = __clk_get_name(refclk);
+
+ hdptx->hw.init = CLK_HW_INIT(name, pname, &hdptx_phy_clk_ops,
+ CLK_GET_RATE_NOCACHE);
+
+ ret = devm_clk_hw_register(dev, &hdptx->hw);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to register clock\n");
+
+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &hdptx->hw);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to register clk provider\n");
+ return 0;
+}
+
static int rk_hdptx_phy_runtime_suspend(struct device *dev)
{
struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev);
@@ -987,7 +1138,7 @@ static int rk_hdptx_phy_probe(struct platform_device *pdev)
reset_control_deassert(hdptx->rsts[RST_CMN].rstc);
reset_control_deassert(hdptx->rsts[RST_INIT].rstc);
- return 0;
+ return rk_hdptx_phy_clk_register(hdptx);
}
static const struct dev_pm_ops rk_hdptx_phy_pm_ops = {
--
2.45.2

81
patch/kernel/archive/rockchip-rk3588-6.11/0144-phy-phy-rockchip-samsung-hdptx-Add-FRL-EARC-support.patch → patch/kernel/archive/rockchip-rk3588-6.11/0132-phy-phy-rockchip-samsung-hdptx-Add-FRL-EARC-support.patch
View File

@@ -1,7 +1,8 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From 07fd1529770701e8c18d9030cd70344b8e2472a5 Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Mon, 5 Feb 2024 01:38:48 +0200
Subject: phy: phy-rockchip-samsung-hdptx: Add FRL & EARC support
Subject: [PATCH 2/2] [WIP] phy: phy-rockchip-samsung-hdptx: Add FRL & EARC
support
For upstreaming, this requires extending the standard PHY API to support
HDMI configuration options [1].
@@ -10,37 +11,40 @@ Currently, the bus_width PHY attribute is used to pass clock rate and
flags for 10-bit color depth, FRL and EARC. This is done by the HDMI
bridge driver via phy_set_bus_width().
[1]: https://lore.kernel.org/all/59d5595a24bbcca897e814440179fa2caf3dff38.1707040881.git.Sandor.yu@nxp.com/
[1]: https://lore.kernel.org/all/20240306101625.795732-3-alexander.stein@ew.tq-group.com/
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 434 +++++++++-
1 file changed, 431 insertions(+), 3 deletions(-)
.../phy/rockchip/phy-rockchip-samsung-hdptx.c | 428 +++++++++++++++++-
1 file changed, 426 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index 111111111111..222222222222 100644
index 9f084697dd05..45db96be3f64 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -190,6 +190,12 @@
#define LN3_TX_SER_RATE_SEL_HBR2 BIT(3)
@@ -193,6 +193,10 @@
#define LN3_TX_SER_RATE_SEL_HBR3 BIT(2)
+#define HDMI20_MAX_RATE 600000000
#define HDMI20_MAX_RATE 600000000
+#define DATA_RATE_MASK 0xFFFFFFF
+#define COLOR_DEPTH_MASK BIT(31)
+#define HDMI_MODE_MASK BIT(30)
+#define HDMI_EARC_MASK BIT(29)
+
struct lcpll_config {
u32 bit_rate;
u8 lcvco_mode_en;
@@ -272,6 +278,25 @@ struct rk_hdptx_phy {
@@ -276,6 +280,7 @@ struct rk_hdptx_phy {
struct clk_bulk_data *clks;
int nr_clks;
struct reset_control_bulk_data rsts[RST_MAX];
+ bool earc_en;
+};
+
/* clk provider */
struct clk_hw hw;
@@ -284,6 +289,24 @@ struct rk_hdptx_phy {
atomic_t usage_count;
};
+static const struct lcpll_config lcpll_cfg[] = {
+ { 48000000, 1, 0, 0, 0x7d, 0x7d, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 2,
+ 0, 0x13, 0x18, 1, 0, 0x20, 0x0c, 1, 0, },
@@ -57,10 +61,12 @@ index 111111111111..222222222222 100644
+ 0, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
+ { 9000000, 0x7d, 0x7d, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1,
+ 0, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
};
+};
+
static const struct ropll_config ropll_tmds_cfg[] = {
@@ -449,6 +474,73 @@ static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = {
{ 5940000, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
@@ -459,6 +482,73 @@ static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = {
REG_SEQ0(CMN_REG(009b), 0x00),
};
@@ -134,7 +140,7 @@ index 111111111111..222222222222 100644
static const struct reg_sequence rk_hdtpx_common_sb_init_seq[] = {
REG_SEQ0(SB_REG(0114), 0x00),
REG_SEQ0(SB_REG(0115), 0x00),
@@ -472,6 +564,17 @@ static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] = {
@@ -482,6 +572,17 @@ static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] = {
REG_SEQ0(LNTOP_REG(0205), 0x1f),
};
@@ -152,7 +158,7 @@ index 111111111111..222222222222 100644
static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] = {
REG_SEQ0(LANE_REG(0303), 0x0c),
REG_SEQ0(LANE_REG(0307), 0x20),
@@ -550,6 +653,40 @@ static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] = {
@@ -560,6 +661,40 @@ static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] = {
REG_SEQ0(LANE_REG(0606), 0x1c),
};
@@ -193,7 +199,7 @@ index 111111111111..222222222222 100644
static bool rk_hdptx_phy_is_rw_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
@@ -651,6 +788,47 @@ static int rk_hdptx_post_enable_pll(struct rk_hdptx_phy *hdptx)
@@ -661,6 +796,47 @@ static int rk_hdptx_post_enable_pll(struct rk_hdptx_phy *hdptx)
return 0;
}
@@ -241,7 +247,7 @@ index 111111111111..222222222222 100644
static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx)
{
u32 val;
@@ -680,6 +858,99 @@ static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx)
@@ -690,6 +866,99 @@ static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx)
regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
}
@@ -341,7 +347,7 @@ index 111111111111..222222222222 100644
static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate,
struct ropll_config *cfg)
{
@@ -755,9 +1026,13 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate,
@@ -765,9 +1034,13 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate,
static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
unsigned int rate)
{
@@ -354,9 +360,9 @@ index 111111111111..222222222222 100644
+ if (color_depth)
+ rate = rate * 10 / 8;
for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
if (rate == ropll_tmds_cfg[i].bit_rate) {
@@ -813,6 +1088,9 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
hdptx->rate = rate * 100;
@@ -825,6 +1098,9 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK,
FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv));
@@ -366,7 +372,7 @@ index 111111111111..222222222222 100644
regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN,
PLL_PCG_CLK_EN);
@@ -853,9 +1131,146 @@ static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx,
@@ -852,9 +1128,146 @@ static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx,
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq);
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lane_init_seq);
@@ -510,10 +516,10 @@ index 111111111111..222222222222 100644
+ return rk_hdptx_post_power_up(hdptx);
+}
+
static int rk_hdptx_phy_power_on(struct phy *phy)
static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx,
unsigned int rate)
{
struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
@@ -865,7 +1280,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy)
@@ -922,11 +1335,22 @@ static int rk_hdptx_phy_power_on(struct phy *phy)
* from the HDMI bridge driver until phy_configure_opts_hdmi
* becomes available in the PHY API.
*/
@@ -522,11 +528,7 @@ index 111111111111..222222222222 100644
dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n",
__func__, bus_width, rate);
@@ -876,7 +1291,20 @@ static int rk_hdptx_phy_power_on(struct phy *phy)
return ret;
}
- ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
+ if (bus_width & HDMI_EARC_MASK)
+ hdptx->earc_en = true;
+ else
@@ -534,16 +536,13 @@ index 111111111111..222222222222 100644
+
+ if (bus_width & HDMI_MODE_MASK) {
+ if (rate > 24000000)
+ ret = rk_hdptx_lcpll_frl_mode_config(hdptx, bus_width);
+ else
+ ret = rk_hdptx_ropll_frl_mode_config(hdptx, bus_width);
+ } else {
+ ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
+ return rk_hdptx_lcpll_frl_mode_config(hdptx, bus_width);
+ return rk_hdptx_ropll_frl_mode_config(hdptx, bus_width);
+ }
+
ret = rk_hdptx_phy_consumer_get(hdptx, rate);
if (ret)
pm_runtime_put(hdptx->dev);
return ret;
--
Armbian
2.45.2

48
patch/kernel/archive/rockchip-rk3588-6.11/0146-drm-rockchip-vop2-Improve-display-modes-handling-on-.patch → patch/kernel/archive/rockchip-rk3588-6.11/0133-drm-rockchip-vop2-Improve-display-modes-handling.patch
View File

@@ -1,7 +1,45 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From 511586733f05f9d62c86a7f077d0a8104a9e1e01 Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Wed, 27 Mar 2024 20:36:15 +0200
Subject: [PATCH 1/2] [WIP] dt-bindings: display: rockchip-drm: Add optional
clocks property
Allow using the clock provided by HDMI0 PHY PLL to improve HDMI output
support on RK3588 SoC.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
.../bindings/display/rockchip/rockchip-drm.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-drm.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-drm.yaml
index a8d18a37cb23..9d000760dd6e 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip-drm.yaml
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-drm.yaml
@@ -28,6 +28,14 @@ properties:
of vop devices. vop definitions as defined in
Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml
+ clocks:
+ maxItems: 1
+ description: Optional clock provided by HDMI0 PLL
+
+ clock-names:
+ items:
+ - const: hdmi0_phy_pll
+
required:
- compatible
- ports
--
2.45.2
From de09dc535799458e6be99ab62e86fd02525bbfe4 Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Fri, 3 Nov 2023 19:58:02 +0200
Subject: drm/rockchip: vop2: Improve display modes handling on rk3588
Subject: [PATCH 2/2] [WIP] drm/rockchip: vop2: Improve display modes handling
on rk3588
The initial vop2 support for rk3588 in mainline is not able to handle
all display modes supported by connected displays, e.g.
@@ -15,11 +53,11 @@ Improve HDMI0 clocking in order to support the additional display modes.
Fixes: 5a028e8f062f ("drm/rockchip: vop2: Add support for rk3588")
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 553 +++++++++-
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 553 ++++++++++++++++++-
1 file changed, 552 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
index 111111111111..222222222222 100644
index 9873172e3fd3..629f60184f66 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
@@ -5,6 +5,8 @@
@@ -675,5 +713,5 @@ index 111111111111..222222222222 100644
if (ret >= 0) {
vop2->rgb = rockchip_rgb_init(dev, &vop2->vps[ret].crtc,
--
Armbian
2.45.2

2665
patch/kernel/archive/rockchip-rk3588-6.11/0134-drm-bridge-synopsys-Add-initial-support-for-DW-HDMI-Controller.patch Normal file
View File

File diff suppressed because it is too large Load Diff

86
patch/kernel/archive/rockchip-rk3588-6.11/0138-arm64-dts-rockchip-Add-HDMI0-bridge-to-rk3588.patch → patch/kernel/archive/rockchip-rk3588-6.11/0135-arm64-dts-rockchip-Add-HDMI0-bridge-CLK-to-rk3588.patch
View File

@@ -1,68 +1,55 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From 719faa1ed1fbe8b998cd3c2d3f846503767bbf8c Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Mon, 15 Jan 2024 22:47:41 +0200
Subject: arm64: dts: rockchip: Add HDMI0 bridge to rk3588
Subject: [PATCH 1/6] arm64: dts: rockchip: Add HDMI0 bridge to rk3588
Add DT node for the HDMI0 bridge found on RK3588 SoC.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 55 ++++++++++
1 file changed, 55 insertions(+)
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 42 +++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 111111111111..222222222222 100644
index b6e4df180f0b..c24c042818d9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1254,6 +1254,61 @@ i2s9_8ch: i2s@fddfc000 {
@@ -1254,6 +1254,48 @@ i2s9_8ch: i2s@fddfc000 {
status = "disabled";
};
+ hdmi0: hdmi@fde80000 {
+ compatible = "rockchip,rk3588-dw-hdmi";
+ compatible = "rockchip,rk3588-dw-hdmi-qp";
+ reg = <0x0 0xfde80000 0x0 0x20000>;
+ clocks = <&cru PCLK_HDMITX0>,
+ <&cru CLK_HDMITX0_EARC>,
+ <&cru CLK_HDMITX0_REF>,
+ <&cru MCLK_I2S5_8CH_TX>,
+ <&cru CLK_HDMIHDP0>,
+ <&cru HCLK_VO1>;
+ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru PCLK_HDMITX0>,
+ <&cru CLK_HDMIHDP0>,
+ <&cru CLK_HDMITX0_EARC>,
+ <&cru CLK_HDMITX0_REF>,
+ <&cru MCLK_I2S5_8CH_TX>,
+ <&cru DCLK_VOP0>,
+ <&cru DCLK_VOP1>,
+ <&cru DCLK_VOP2>,
+ <&cru DCLK_VOP3>,
+ <&cru HCLK_VO1>;
+ clock-names = "pclk",
+ "hpd",
+ "earc",
+ "hdmitx_ref",
+ "aud",
+ "dclk_vp0",
+ "dclk_vp1",
+ "dclk_vp2",
+ "dclk_vp3",
+ "hclk_vo1";
+ resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
+ reset-names = "ref", "hdp";
+ power-domains = <&power RK3588_PD_VO1>;
+ interrupt-names = "avp", "cec", "earc", "main", "hpd";
+ phys = <&hdptxphy_hdmi0>;
+ phy-names = "hdmi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
+ &hdmim0_tx0_scl &hdmim0_tx0_sda>;
+ reg-io-width = <4>;
+ power-domains = <&power RK3588_PD_VO1>;
+ resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
+ reset-names = "ref", "hdp";
+ rockchip,grf = <&sys_grf>;
+ rockchip,vo1_grf = <&vo1_grf>;
+ phys = <&hdptxphy_hdmi0>;
+ phy-names = "hdmi";
+ status = "disabled";
+
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+
+ hdmi0_in: port@0 {
+ reg = <0>;
+ };
@@ -77,5 +64,32 @@ index 111111111111..222222222222 100644
compatible = "rockchip,rk3588-qos", "syscon";
reg = <0x0 0xfdf35000 0x0 0x20>;
--
Armbian
2.45.2
From fe5d3825918416dce3c060d0d8397a425e87d6f8 Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Tue, 16 Jan 2024 03:13:38 +0200
Subject: [PATCH 4/6] [WIP] arm64: dts: rockchip: Enable HDMI0 PHY clk provider
on rk3588
The HDMI0 PHY can be used as a clock provider on RK3588, hence add the
missing #clock-cells property.
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index c24c042818d9..90b4aa04ce1e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -2696,6 +2696,7 @@ hdptxphy_hdmi0: phy@fed60000 {
reg = <0x0 0xfed60000 0x0 0x2000>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
clock-names = "ref", "apb";
+ #clock-cells = <0>;
#phy-cells = <0>;
resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
<&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
--
2.45.2

26
patch/kernel/archive/rockchip-rk3588-6.11/0139-arm64-dts-rockchip-Enable-HDMI0-PHY-clk-provider-on-.patch
View File

@@ -1,26 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Tue, 16 Jan 2024 03:13:38 +0200
Subject: arm64: dts: rockchip: Enable HDMI0 PHY clk provider on rk3588
The HDMI0 PHY can be used as a clock provider on RK3588, hence add the
missing #clock-cells property.
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 111111111111..222222222222 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -2709,6 +2709,7 @@ hdptxphy_hdmi0: phy@fed60000 {
reg = <0x0 0xfed60000 0x0 0x2000>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
clock-names = "ref", "apb";
+ #clock-cells = <0>;
#phy-cells = <0>;
resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
<&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
--
Armbian

222
patch/kernel/archive/rockchip-rk3588-6.11/0145-phy-phy-rockchip-samsung-hdptx-Add-clock-provider.patch
View File

@@ -1,222 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Date: Tue, 16 Jan 2024 19:27:40 +0200
Subject: phy: phy-rockchip-samsung-hdptx: Add clock provider
The HDMI PHY PLL can be used as an alternative dclk source to SoC CRU.
It provides more accurate clock rates required to properly support
various display modes, e.g. those relying on non-integer refresh rates.
Also note this only works for HDMI 2.0 or bellow, e.g. cannot be used to
support HDMI 2.1 4K@120Hz mode.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 148 +++++++++-
1 file changed, 143 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index 111111111111..222222222222 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -8,6 +8,7 @@
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
+#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
@@ -279,6 +280,12 @@ struct rk_hdptx_phy {
int nr_clks;
struct reset_control_bulk_data rsts[RST_MAX];
bool earc_en;
+
+ /* clk provider */
+ struct clk_hw hw;
+ unsigned long rate;
+ int id;
+ int count;
};
static const struct lcpll_config lcpll_cfg[] = {
@@ -1031,6 +1038,8 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
const struct ropll_config *cfg = NULL;
struct ropll_config rc = {0};
+ hdptx->rate = rate * 100;
+
if (color_depth)
rate = rate * 10 / 8;
@@ -1315,11 +1324,13 @@ static int rk_hdptx_phy_power_off(struct phy *phy)
{
struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
u32 val;
- int ret;
+ int ret = 0;
- ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val);
- if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE))
- rk_hdptx_phy_disable(hdptx);
+ if (hdptx->count == 0) {
+ ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val);
+ if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE))
+ rk_hdptx_phy_disable(hdptx);
+ }
pm_runtime_put(hdptx->dev);
@@ -1332,6 +1343,129 @@ static const struct phy_ops rk_hdptx_phy_ops = {
.owner = THIS_MODULE,
};
+static struct rk_hdptx_phy *to_rk_hdptx_phy(struct clk_hw *hw)
+{
+ return container_of(hw, struct rk_hdptx_phy, hw);
+}
+
+static int rk_hdptx_phy_clk_prepare(struct clk_hw *hw)
+{
+ struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
+ int ret;
+
+ ret = pm_runtime_resume_and_get(hdptx->dev);
+ if (ret) {
+ dev_err(hdptx->dev, "Failed to resume phy clk: %d\n", ret);
+ return ret;
+ }
+
+ if (!hdptx->count && hdptx->rate) {
+ ret = rk_hdptx_ropll_tmds_cmn_config(hdptx, hdptx->rate / 100);
+ if (ret < 0) {
+ dev_err(hdptx->dev, "Failed to init PHY PLL: %d\n", ret);
+ pm_runtime_put(hdptx->dev);
+ return ret;
+ }
+ }
+
+ hdptx->count++;
+
+ return 0;
+}
+
+static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw)
+{
+ struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
+
+ if (hdptx->count == 1) {
+ u32 val;
+ int ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val);
+ if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE))
+ rk_hdptx_phy_disable(hdptx);
+ }
+
+ hdptx->count--;
+ pm_runtime_put(hdptx->dev);
+}
+
+static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
+
+ return hdptx->rate;
+}
+
+static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ const struct ropll_config *cfg = NULL;
+ u32 bit_rate = rate / 100;
+ int i;
+
+ if (rate > HDMI20_MAX_RATE)
+ return rate;
+
+ for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
+ if (bit_rate == ropll_tmds_cfg[i].bit_rate) {
+ cfg = &ropll_tmds_cfg[i];
+ break;
+ }
+
+ if (!cfg && !rk_hdptx_phy_clk_pll_calc(bit_rate, NULL))
+ return -EINVAL;
+
+ return rate;
+}
+
+static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
+ u32 val;
+ int ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val);
+ if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE))
+ rk_hdptx_phy_disable(hdptx);
+
+ return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate / 100);
+}
+
+static const struct clk_ops hdptx_phy_clk_ops = {
+ .prepare = rk_hdptx_phy_clk_prepare,
+ .unprepare = rk_hdptx_phy_clk_unprepare,
+ .recalc_rate = rk_hdptx_phy_clk_recalc_rate,
+ .round_rate = rk_hdptx_phy_clk_round_rate,
+ .set_rate = rk_hdptx_phy_clk_set_rate,
+};
+
+static int rk_hdptx_phy_clk_register(struct rk_hdptx_phy *hdptx)
+{
+ struct device *dev = hdptx->dev;
+ const char *name, *pname;
+ struct clk *refclk;
+ int ret;
+
+ refclk = devm_clk_get(dev, "ref");
+ if (IS_ERR(refclk))
+ return dev_err_probe(dev, PTR_ERR(refclk),
+ "Failed to get ref clock\n");
+
+ pname = __clk_get_name(refclk);
+ name = hdptx->id ? "clk_hdmiphy_pixel1" : "clk_hdmiphy_pixel0";
+ hdptx->hw.init = CLK_HW_INIT(name, pname, &hdptx_phy_clk_ops,
+ CLK_GET_RATE_NOCACHE);
+
+ ret = devm_clk_hw_register(dev, &hdptx->hw);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to register clock\n");
+
+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &hdptx->hw);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to register clk provider\n");
+ return 0;
+}
+
static int rk_hdptx_phy_runtime_suspend(struct device *dev)
{
struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev);
@@ -1367,6 +1501,10 @@ static int rk_hdptx_phy_probe(struct platform_device *pdev)
hdptx->dev = dev;
+ hdptx->id = of_alias_get_id(dev->of_node, "hdptxphy");
+ if (hdptx->id < 0)
+ hdptx->id = 0;
+
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return dev_err_probe(dev, PTR_ERR(regs),
@@ -1426,7 +1564,7 @@ static int rk_hdptx_phy_probe(struct platform_device *pdev)
reset_control_deassert(hdptx->rsts[RST_CMN].rstc);
reset_control_deassert(hdptx->rsts[RST_INIT].rstc);
- return 0;
+ return rk_hdptx_phy_clk_register(hdptx);
}
static const struct dev_pm_ops rk_hdptx_phy_pm_ops = {
--
Armbian

6616
patch/kernel/archive/rockchip-rk3588-6.11/0161-drm-bridge-synopsys-Add-initial-support-for-DW-HDMI-Controller.patch
View File

File diff suppressed because it is too large Load Diff

25
patch/kernel/archive/rockchip-rk3588-6.11/0162-drm-bridge-synopsys-Fix-HDMI-Controller.patch
View File

@@ -1,25 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: ColorfulRhino <unknown-email@domain.tld>
Date: Wed, 12 Jun 2024 12:17:18 +0200
Subject: Fix HDMI controller patch at
drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
index 111111111111..222222222222 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
@@ -5,6 +5,7 @@
* Algea Cao <algea.cao@rock-chips.com>
*/
#include <linux/clk.h>
+#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
--
Armbian

95
patch/kernel/archive/rockchip-rk3588-6.11/1021-arm64-dts-Add-missing-nodes-to-Orange-Pi-5-Plus.patch
View File

@@ -1,14 +1,14 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From 9e44204e18695761c90996a5031e50afa61420d3 Mon Sep 17 00:00:00 2001
From: Muhammed Efe Cetin <efectn@protonmail.com>
Date: Thu, 16 Nov 2023 18:15:09 +0300
Subject: arm64: dts: Add missing nodes to Orange Pi 5 Plus
Subject: [PATCH] arm64: dts: Add missing nodes to Orange Pi 5 Plus
---
arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 203 +++++++++-
1 file changed, 202 insertions(+), 1 deletion(-)
.../dts/rockchip/rk3588-orangepi-5-plus.dts | 217 +++++++++++++++++-
1 file changed, 216 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
index 111111111111..222222222222 100644
index e74871491ef5..72eb082732c6 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
@@ -10,6 +10,7 @@
@@ -19,7 +19,25 @@ index 111111111111..222222222222 100644
#include "rk3588.dtsi"
/ {
@@ -158,6 +159,20 @@ daicodec: simple-audio-card,codec {
@@ -85,6 +86,17 @@ led {
};
};
+ hdmi0-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi0_con_in: endpoint {
+ remote-endpoint = <&hdmi0_out_con>;
+ };
+ };
+ };
+
fan: pwm-fan {
compatible = "pwm-fan";
cooling-levels = <0 70 75 80 100>;
@@ -158,6 +170,20 @@ daicodec: simple-audio-card,codec {
};
};
@@ -40,7 +58,7 @@ index 111111111111..222222222222 100644
vcc3v3_pcie30: vcc3v3-pcie30-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -199,6 +214,18 @@ vcc5v0_sys: vcc5v0-sys-regulator {
@@ -199,6 +225,18 @@ vcc5v0_sys: vcc5v0-sys-regulator {
regulator-max-microvolt = <5000000>;
};
@@ -59,7 +77,7 @@ index 111111111111..222222222222 100644
vcc5v0_usb20: vcc5v0-usb20-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -311,6 +338,53 @@ hym8563: rtc@51 {
@@ -311,6 +349,53 @@ hym8563: rtc@51 {
pinctrl-0 = <&hym8563_int>;
wakeup-source;
};
@@ -113,13 +131,13 @@ index 111111111111..222222222222 100644
};
&i2c7 {
@@ -383,9 +457,15 @@ &pcie3x4 {
@@ -383,9 +468,15 @@ &pcie3x4 {
};
&pinctrl {
+ hdmirx {
+ hdmirx_5v_detection: hdmirx-5v-detection {
+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
@@ -130,7 +148,7 @@ index 111111111111..222222222222 100644
};
};
@@ -408,6 +488,14 @@ hp_detect: hp-detect {
@@ -408,6 +499,14 @@ hp_detect: hp-detect {
};
usb {
@@ -145,7 +163,7 @@ index 111111111111..222222222222 100644
vcc5v0_usb20_en: vcc5v0-usb20-en {
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
@@ -803,6 +891,22 @@ &tsadc {
@@ -803,6 +902,22 @@ &tsadc {
status = "okay";
};
@@ -168,7 +186,7 @@ index 111111111111..222222222222 100644
&u2phy2 {
status = "okay";
};
@@ -831,6 +935,35 @@ &uart9 {
@@ -831,6 +946,35 @@ &uart9 {
status = "okay";
};
@@ -204,12 +222,12 @@ index 111111111111..222222222222 100644
&usb_host0_ehci {
status = "okay";
};
@@ -839,6 +972,20 @@ &usb_host0_ohci {
@@ -839,6 +983,20 @@ &usb_host0_ohci {
status = "okay";
};
+&usb_host0_xhci {
+ dr_mode = "otg";
+ dr_mode = "host";
+ usb-role-switch;
+ status = "okay";
+
@@ -225,7 +243,7 @@ index 111111111111..222222222222 100644
&usb_host1_ehci {
status = "okay";
};
@@ -846,3 +993,57 @@ &usb_host1_ehci {
@@ -846,3 +1004,60 @@ &usb_host1_ehci {
&usb_host1_ohci {
status = "okay";
};
@@ -240,30 +258,12 @@ index 111111111111..222222222222 100644
+ status = "okay";
+};
+
+&hdmi0 {
+ status = "okay";
+ enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
+ cec-enable = "true";
+};
+
+&hdptxphy_hdmi0 {
+ status = "okay";
+};
+
+&hdmi_receiver {
+ status = "okay";
+ hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl
+ &hdmim1_rx_sda &hdmirx_5v_detection>;
+ pinctrl-names = "default";
+};
+
+&hdmi_receiver_cma {
+ status = "okay";
+};
+
+
+&vop_mmu {
+&hdmi0 {
+ enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
@@ -273,10 +273,31 @@ index 111111111111..222222222222 100644
+ };
+};
+
+&hdmi0_out {
+ hdmi0_out_con: endpoint {
+ remote-endpoint = <&hdmi0_con_in>;
+ };
+};
+
+&hdmi_receiver {
+ hpd = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_5v_detection>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&hdmi_receiver_cma {
+ status = "okay";
+};
+
+&vop {
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
@@ -284,5 +305,5 @@ index 111111111111..222222222222 100644
+ };
+};
--
Armbian
2.45.2