archr/Arch-R
0
0
Fork 0
mirror of https://github.com/archr-linux/Arch-R.git synced 2026-03-31 14:41:55 -07:00
Code Issues Packages Projects Releases Wiki Activity

linux/sm8550: restore kernel stuff

Browse Source
This commit is contained in:
Philippe Simons
2025-10-28 22:51:28 +01:00
parent 752e295e6d
commit f73fb9f640
9 changed files with 554 additions and 184 deletions
Download Patch File Download Diff File Expand all files Collapse all files

218
projects/ROCKNIX/devices/SM8550/patches/linux/0041-v6_20250908_quic_sartgarg_add_level_shifter_support_for_qualcomm_soc_s.patch Normal file
View File

@@ -0,0 +1,218 @@
From git@z Thu Jan 1 00:00:00 1970
Subject: [PATCH v6 1/4] mmc: sdhci-msm: Enable tuning for SDR50 mode for SD
card
From: Sarthak Garg <quic_sartgarg@quicinc.com>
Date: Mon, 08 Sep 2025 16:11:19 +0530
Message-Id: <20250908104122.2062653-2-quic_sartgarg@quicinc.com>
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 7bit
For Qualcomm SoCs which needs level shifter for SD card, extra delay is
seen on receiver data path.
To compensate this delay enable tuning for SDR50 mode for targets which
has level shifter. SDHCI_SDR50_NEEDS_TUNING caps will be set for targets
with level shifter on Qualcomm SOC's.
Signed-off-by: Sarthak Garg <quic_sartgarg@quicinc.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
---
drivers/mmc/host/sdhci-msm.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 66c0d1ba2a33..bf91cb96a0ea 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -81,6 +81,7 @@
#define CORE_IO_PAD_PWR_SWITCH_EN BIT(15)
#define CORE_IO_PAD_PWR_SWITCH BIT(16)
#define CORE_HC_SELECT_IN_EN BIT(18)
+#define CORE_HC_SELECT_IN_SDR50 (4 << 19)
#define CORE_HC_SELECT_IN_HS400 (6 << 19)
#define CORE_HC_SELECT_IN_MASK (7 << 19)
@@ -1133,6 +1134,10 @@ static bool sdhci_msm_is_tuning_needed(struct sdhci_host *host)
{
struct mmc_ios *ios = &host->mmc->ios;
+ if (ios->timing == MMC_TIMING_UHS_SDR50 &&
+ host->flags & SDHCI_SDR50_NEEDS_TUNING)
+ return true;
+
/*
* Tuning is required for SDR104, HS200 and HS400 cards and
* if clock frequency is greater than 100MHz in these modes.
@@ -1201,6 +1206,8 @@ static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
struct mmc_ios ios = host->mmc->ios;
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
+ const struct sdhci_msm_offset *msm_offset = msm_host->offset;
+ u32 config;
if (!sdhci_msm_is_tuning_needed(host)) {
msm_host->use_cdr = false;
@@ -1217,6 +1224,14 @@ static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
*/
msm_host->tuning_done = 0;
+ if (ios.timing == MMC_TIMING_UHS_SDR50 &&
+ host->flags & SDHCI_SDR50_NEEDS_TUNING) {
+ config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
+ config &= ~CORE_HC_SELECT_IN_MASK;
+ config |= CORE_HC_SELECT_IN_EN | CORE_HC_SELECT_IN_SDR50;
+ writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
+ }
+
/*
* For HS400 tuning in HS200 timing requires:
* - select MCLK/2 in VENDOR_SPEC
--
2.34.1
From git@z Thu Jan 1 00:00:00 1970
Subject: [PATCH v6 2/4] dt-bindings: mmc: controller: Add max-sd-hs-hz
property
From: Sarthak Garg <quic_sartgarg@quicinc.com>
Date: Mon, 08 Sep 2025 16:11:20 +0530
Message-Id: <20250908104122.2062653-3-quic_sartgarg@quicinc.com>
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 7bit
Introduce a new optional device tree property max-sd-hs-hz to
limit the maximum frequency (in Hz) used for SD cards operating in
High-Speed (HS) mode due to any board electrical limitations.
Signed-off-by: Sarthak Garg <quic_sartgarg@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../devicetree/bindings/mmc/mmc-controller-common.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml
index 9a7235439759..7414d5522dfe 100644
--- a/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml
+++ b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml
@@ -93,6 +93,14 @@ properties:
minimum: 400000
maximum: 384000000
+ max-sd-hs-hz:
+ description: |
+ Maximum frequency (in Hz) to be used for SD cards operating in
+ High-Speed (HS) mode.
+ minimum: 400000
+ maximum: 50000000
+ default: 50000000
+
disable-wp:
$ref: /schemas/types.yaml#/definitions/flag
description:
--
2.34.1
From git@z Thu Jan 1 00:00:00 1970
Subject: [PATCH v6 3/4] mmc: core: Introduce a new flag max-sd-hs-hz
From: Sarthak Garg <quic_sartgarg@quicinc.com>
Date: Mon, 08 Sep 2025 16:11:21 +0530
Message-Id: <20250908104122.2062653-4-quic_sartgarg@quicinc.com>
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 7bit
Introduce a new device tree flag to cap the maximum High-Speed (HS)
mode frequency for SD cards, accommodating board-specific
electrical limitations which cannot support the default 50Mhz HS
frequency and others.
Signed-off-by: Sarthak Garg <quic_sartgarg@quicinc.com>
---
drivers/mmc/core/host.c | 2 ++
drivers/mmc/core/sd.c | 2 +-
include/linux/mmc/host.h | 1 +
3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
index dacb5bd9bb71..3fe6ae56a6ae 100644
--- a/drivers/mmc/core/host.c
+++ b/drivers/mmc/core/host.c
@@ -302,6 +302,8 @@ int mmc_of_parse(struct mmc_host *host)
/* f_max is obtained from the optional "max-frequency" property */
device_property_read_u32(dev, "max-frequency", &host->f_max);
+ device_property_read_u32(dev, "max-sd-hs-hz", &host->max_sd_hs_hz);
+
/*
* Configure CD and WP pins. They are both by default active low to
* match the SDHCI spec. If GPIOs are provided for CD and / or WP, the
diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c
index ec02067f03c5..67cd63004829 100644
--- a/drivers/mmc/core/sd.c
+++ b/drivers/mmc/core/sd.c
@@ -359,7 +359,7 @@ static int mmc_read_switch(struct mmc_card *card)
}
if (status[13] & SD_MODE_HIGH_SPEED)
- card->sw_caps.hs_max_dtr = HIGH_SPEED_MAX_DTR;
+ card->sw_caps.hs_max_dtr = card->host->max_sd_hs_hz ?: HIGH_SPEED_MAX_DTR;
if (card->scr.sda_spec3) {
card->sw_caps.sd3_bus_mode = status[13];
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 68f09a955a90..a698b4b02d95 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -565,6 +565,7 @@ struct mmc_host {
int hsq_depth;
u32 err_stats[MMC_ERR_MAX];
+ unsigned int max_sd_hs_hz;
unsigned long private[] ____cacheline_aligned;
};
--
2.34.1
From git@z Thu Jan 1 00:00:00 1970
Subject: [PATCH v6 4/4] arm64: dts: qcom: sm8550: Limit max SD HS mode
frequency by default
From: Sarthak Garg <quic_sartgarg@quicinc.com>
Date: Mon, 08 Sep 2025 16:11:22 +0530
Message-Id: <20250908104122.2062653-5-quic_sartgarg@quicinc.com>
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 7bit
Due to an implementation detail in this SoC, additional passive
electrical components are required to achieve the maximum rated speed
of the SD controller when paired with a High-Speed SD Card. Without
them, the clock frequency must be limited to 37.5 MHz for link stability.
Because the reference design does not contain these components, most
(derivative) boards do not have them either. To accommodate for that,
apply the frequency limit by default and delegate lifting it to the
odd boards that do contain the necessary onboard hardware.
Signed-off-by: Sarthak Garg <quic_sartgarg@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 82cabf777cd2..3692a3a49634 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -3189,6 +3189,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
&config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "sdhc-ddr", "cpu-sdhc";
bus-width = <4>;
+ max-sd-hs-hz = <37500000>;
dma-coherent;
/* Forbid SDR104/SDR50 - broken hw! */
--
2.34.1

39
projects/ROCKNIX/devices/SM8550/patches/linux/0041_dt-bindings--mmc--qcom--Document-level-shifter-fla.patch
View File

@@ -1,39 +0,0 @@
From d4032ecdf370977142ae0754d2801c53fdc64b9c Mon Sep 17 00:00:00 2001
From: Sarthak Garg <quic_sartgarg@quicinc.com>
Date: Thu, 7 Nov 2024 13:35:03 +0530
Subject: [PATCH] dt-bindings: mmc: qcom: Document level shifter flag for SD
card
Introduce a flag to indicate if the Qualcomm platform has a level
shifter for SD cards. With level shifter addition some extra delay is
seen on RX data path leading to CRC errors. To compensate these delays
and avoid CRC errors below things needs to be done:
1) Enable tuning for SDR50 mode
2) Limit HS mode frequency to 37.5MHz from 50MHz
Add this flag for all targets with a level shifter to handle these
issues for SD card.
Signed-off-by: Sarthak Garg <quic_sartgarg@quicinc.com>
---
Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
index 8b393e26e025..064dd458ecbc 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
+++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
@@ -133,6 +133,9 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
description: platform specific settings for DLL_CONFIG reg.
+ qcom,use-level-shifter:
+ description: Flag to indicate if platform has level shifter for SD card.
+
iommus:
minItems: 1
maxItems: 8
--
2.34.1

67
projects/ROCKNIX/devices/SM8550/patches/linux/0042_mmc--sdhci-msm--Enable-tuning-for-SDR50-mode-for-S.patch
View File

@@ -1,67 +0,0 @@
From a655571f7eac983ad53b3f30f75270fb81aadb88 Mon Sep 17 00:00:00 2001
From: Sarthak Garg <quic_sartgarg@quicinc.com>
Date: Thu, 7 Nov 2024 13:35:04 +0530
Subject: [PATCH] mmc: sdhci-msm: Enable tuning for SDR50 mode for SD card
For Qualcomm SoCs which needs level shifter for SD card, extra delay is
seen on receiver data path.
To compensate this delay enable tuning for SDR50 mode for targets which
has level shifter.
Signed-off-by: Sarthak Garg <quic_sartgarg@quicinc.com>
---
drivers/mmc/host/sdhci-msm.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 1fcaaf683d68..a6c9e9b60812 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -81,6 +81,7 @@
#define CORE_IO_PAD_PWR_SWITCH_EN BIT(15)
#define CORE_IO_PAD_PWR_SWITCH BIT(16)
#define CORE_HC_SELECT_IN_EN BIT(18)
+#define CORE_HC_SELECT_IN_SDR50 (4 << 19)
#define CORE_HC_SELECT_IN_HS400 (6 << 19)
#define CORE_HC_SELECT_IN_MASK (7 << 19)
@@ -1133,6 +1134,10 @@ static bool sdhci_msm_is_tuning_needed(struct sdhci_host *host)
{
struct mmc_ios *ios = &host->mmc->ios;
+ if (ios->timing == MMC_TIMING_UHS_SDR50 &&
+ host->flags & SDHCI_SDR50_NEEDS_TUNING)
+ return true;
+
/*
* Tuning is required for SDR104, HS200 and HS400 cards and
* if clock frequency is greater than 100MHz in these modes.
@@ -1201,6 +1206,8 @@ static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
struct mmc_ios ios = host->mmc->ios;
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
+ const struct sdhci_msm_offset *msm_offset = msm_host->offset;
+ u32 config;
if (!sdhci_msm_is_tuning_needed(host)) {
msm_host->use_cdr = false;
@@ -1217,6 +1224,15 @@ static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
*/
msm_host->tuning_done = 0;
+ if (ios.timing == MMC_TIMING_UHS_SDR50 &&
+ host->flags & SDHCI_SDR50_NEEDS_TUNING) {
+ config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
+ config |= CORE_HC_SELECT_IN_EN;
+ config &= ~CORE_HC_SELECT_IN_MASK;
+ config |= CORE_HC_SELECT_IN_SDR50;
+ writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
+ }
+
/*
* For HS400 tuning in HS200 timing requires:
* - select MCLK/2 in VENDOR_SPEC
--
2.34.1

0
projects/ROCKNIX/devices/SM8550/patches/linux/0044_mmc--sdhci-msm--Toggle-the-FIFO-write-clock-after-.patch → projects/ROCKNIX/devices/SM8550/patches/linux/0042_mmc--sdhci-msm--Toggle-the-FIFO-write-clock-after-.patch
View File

62
projects/ROCKNIX/devices/SM8550/patches/linux/0043_mmc--sdhci-msm--Limit-HS-mode-frequency-to-37.5MHz.patch
View File

@@ -1,62 +0,0 @@
From 2ffae54825fb8a86d377c51632995e5cfadb2307 Mon Sep 17 00:00:00 2001
From: Sarthak Garg <quic_sartgarg@quicinc.com>
Date: Thu, 7 Nov 2024 13:35:05 +0530
Subject: [PATCH] mmc: sdhci-msm: Limit HS mode frequency to 37.5MHz
For Qualcomm SoCs with level shifter delays are seen on receivers data
path due to latency added by level shifter.
To bring these delays in normal range and avoid CMD CRC errors
reduce frequency for HS mode SD cards to 37.5MHz for targets which has
level shifter.
Signed-off-by: Sarthak Garg <quic_sartgarg@quicinc.com>
---
drivers/mmc/host/sdhci-msm.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index a6c9e9b60812..9473039ccb13 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -147,6 +147,8 @@
/* Max load for SD Vdd-io supply */
#define SD_VQMMC_MAX_LOAD_UA 22000
+#define LEVEL_SHIFTER_HIGH_SPEED_FREQ 37500000
+
#define msm_host_readl(msm_host, host, offset) \
msm_host->var_ops->msm_readl_relaxed(host, offset)
@@ -296,6 +298,7 @@ struct sdhci_msm_host {
bool use_cdr;
u32 transfer_mode;
bool updated_ddr_cfg;
+ bool uses_level_shifter;
bool uses_tassadar_dll;
u32 dll_config;
u32 ddr_config;
@@ -375,6 +378,11 @@ static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host,
mult = msm_get_clock_mult_for_bus_mode(host);
desired_rate = clock * mult;
+
+ if (curr_ios.timing == MMC_TIMING_SD_HS && desired_rate == 50000000
+ && msm_host->uses_level_shifter)
+ desired_rate = LEVEL_SHIFTER_HIGH_SPEED_FREQ;
+
rc = dev_pm_opp_set_rate(mmc_dev(host->mmc), desired_rate);
if (rc) {
pr_err("%s: Failed to set clock at rate %u at timing %d\n",
@@ -2421,6 +2429,8 @@ static inline void sdhci_msm_get_of_property(struct platform_device *pdev,
of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config);
+ msm_host->uses_level_shifter = of_property_read_bool(node, "qcom,use-level-shifter");
+
if (of_device_is_compatible(node, "qcom,msm8916-sdhci"))
host->quirks2 |= SDHCI_QUIRK2_BROKEN_64_BIT_DMA;
}
--
2.34.1

226
projects/ROCKNIX/devices/SM8550/patches/linux/0200_arm64--dts--qcom--Add-AYN-QCS8550-Common.patch
View File

@@ -14,7 +14,7 @@ new file mode 100644
index 000000000000..0954c1854a05
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-ayn-common.dtsi
@@ -0,0 +1,1445 @@
@@ -0,0 +1,1661 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Teguh Sobirin.
@@ -115,7 +115,7 @@ index 000000000000..0954c1854a05
+ compatible = "pwm-fan";
+
+ fan-supply = <&vdd_fan_5v0>;
+ pwms = <&pm8550_pwm 3 100000>;
+ pwms = <&pm8550_pwm 3 40000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&fan_pwm_active>;
@@ -203,6 +203,223 @@ index 000000000000..0954c1854a05
+ };
+ };
+
+ thermal-zones {
+ cpuss0-thermal {
+ polling-delay = <200>;
+ trips {
+ cpuss0_fan0: trip-point2 { temperature = <50000>; hysteresis = <3000>; type = "active"; };
+ cpuss0_fan1: trip-point3 { temperature = <55000>; hysteresis = <3000>; type = "active"; };
+ cpuss0_fan2: trip-point4 { temperature = <60000>; hysteresis = <3000>; type = "active"; };
+ cpuss0_fan3: trip-point5 { temperature = <65000>; hysteresis = <3000>; type = "active"; };
+ cpuss0_fan4: trip-point6 { temperature = <70000>; hysteresis = <3000>; type = "active"; };
+ cpuss0_fan5: trip-point7 { temperature = <75000>; hysteresis = <3000>; type = "active"; };
+ cpuss0_fan6: trip-point8 { temperature = <80000>; hysteresis = <3000>; type = "active"; };
+ };
+
+ cooling-maps {
+ map0 { trip = <&cpuss0_fan0>; cooling-device = <&pwm_fan 0 1>; };
+ map1 { trip = <&cpuss0_fan1>; cooling-device = <&pwm_fan 1 2>; };
+ map2 { trip = <&cpuss0_fan2>; cooling-device = <&pwm_fan 2 3>; };
+ map3 { trip = <&cpuss0_fan3>; cooling-device = <&pwm_fan 3 4>; };
+ map4 { trip = <&cpuss0_fan4>; cooling-device = <&pwm_fan 4 5>; };
+ map5 { trip = <&cpuss0_fan5>; cooling-device = <&pwm_fan 5 6>; };
+ map6 { trip = <&cpuss0_fan6>; cooling-device = <&pwm_fan 6 7>; };
+ };
+ };
+ cpuss1-thermal {
+ polling-delay = <200>;
+ trips {
+ cpuss1_fan0: trip-point2 { temperature = <50000>; hysteresis = <3000>; type = "active"; };
+ cpuss1_fan1: trip-point3 { temperature = <55000>; hysteresis = <3000>; type = "active"; };
+ cpuss1_fan2: trip-point4 { temperature = <60000>; hysteresis = <3000>; type = "active"; };
+ cpuss1_fan3: trip-point5 { temperature = <65000>; hysteresis = <3000>; type = "active"; };
+ cpuss1_fan4: trip-point6 { temperature = <70000>; hysteresis = <3000>; type = "active"; };
+ cpuss1_fan5: trip-point7 { temperature = <75000>; hysteresis = <3000>; type = "active"; };
+ cpuss1_fan6: trip-point8 { temperature = <80000>; hysteresis = <3000>; type = "active"; };
+ };
+
+ cooling-maps {
+ map0 { trip = <&cpuss1_fan0>; cooling-device = <&pwm_fan 0 1>; };
+ map1 { trip = <&cpuss1_fan1>; cooling-device = <&pwm_fan 1 2>; };
+ map2 { trip = <&cpuss1_fan2>; cooling-device = <&pwm_fan 2 3>; };
+ map3 { trip = <&cpuss1_fan3>; cooling-device = <&pwm_fan 3 4>; };
+ map4 { trip = <&cpuss1_fan4>; cooling-device = <&pwm_fan 4 5>; };
+ map5 { trip = <&cpuss1_fan5>; cooling-device = <&pwm_fan 5 6>; };
+ map6 { trip = <&cpuss1_fan6>; cooling-device = <&pwm_fan 6 7>; };
+ };
+ };
+ cpuss2-thermal {
+ polling-delay = <200>;
+ trips {
+ cpuss2_fan0: trip-point2 { temperature = <50000>; hysteresis = <3000>; type = "active"; };
+ cpuss2_fan1: trip-point3 { temperature = <55000>; hysteresis = <3000>; type = "active"; };
+ cpuss2_fan2: trip-point4 { temperature = <60000>; hysteresis = <3000>; type = "active"; };
+ cpuss2_fan3: trip-point5 { temperature = <65000>; hysteresis = <3000>; type = "active"; };
+ cpuss2_fan4: trip-point6 { temperature = <70000>; hysteresis = <3000>; type = "active"; };
+ cpuss2_fan5: trip-point7 { temperature = <75000>; hysteresis = <3000>; type = "active"; };
+ cpuss2_fan6: trip-point8 { temperature = <80000>; hysteresis = <3000>; type = "active"; };
+ };
+
+ cooling-maps {
+ map0 { trip = <&cpuss2_fan0>; cooling-device = <&pwm_fan 0 1>; };
+ map1 { trip = <&cpuss2_fan1>; cooling-device = <&pwm_fan 1 2>; };
+ map2 { trip = <&cpuss2_fan2>; cooling-device = <&pwm_fan 2 3>; };
+ map3 { trip = <&cpuss2_fan3>; cooling-device = <&pwm_fan 3 4>; };
+ map4 { trip = <&cpuss2_fan4>; cooling-device = <&pwm_fan 4 5>; };
+ map5 { trip = <&cpuss2_fan5>; cooling-device = <&pwm_fan 5 6>; };
+ map6 { trip = <&cpuss2_fan6>; cooling-device = <&pwm_fan 6 7>; };
+ };
+ };
+ cpuss3-thermal {
+ polling-delay = <200>;
+ trips {
+ cpuss3_fan0: trip-point2 { temperature = <50000>; hysteresis = <3000>; type = "active"; };
+ cpuss3_fan1: trip-point3 { temperature = <55000>; hysteresis = <3000>; type = "active"; };
+ cpuss3_fan2: trip-point4 { temperature = <60000>; hysteresis = <3000>; type = "active"; };
+ cpuss3_fan3: trip-point5 { temperature = <65000>; hysteresis = <3000>; type = "active"; };
+ cpuss3_fan4: trip-point6 { temperature = <70000>; hysteresis = <3000>; type = "active"; };
+ cpuss3_fan5: trip-point7 { temperature = <75000>; hysteresis = <3000>; type = "active"; };
+ cpuss3_fan6: trip-point8 { temperature = <80000>; hysteresis = <3000>; type = "active"; };
+ };
+
+ cooling-maps {
+ map0 { trip = <&cpuss3_fan0>; cooling-device = <&pwm_fan 0 1>; };
+ map1 { trip = <&cpuss3_fan1>; cooling-device = <&pwm_fan 1 2>; };
+ map2 { trip = <&cpuss3_fan2>; cooling-device = <&pwm_fan 2 3>; };
+ map3 { trip = <&cpuss3_fan3>; cooling-device = <&pwm_fan 3 4>; };
+ map4 { trip = <&cpuss3_fan4>; cooling-device = <&pwm_fan 4 5>; };
+ map5 { trip = <&cpuss3_fan5>; cooling-device = <&pwm_fan 5 6>; };
+ map6 { trip = <&cpuss3_fan6>; cooling-device = <&pwm_fan 6 7>; };
+ };
+ };
+ cpu7-top-thermal {
+ polling-delay = <200>;
+ trips {
+ cpu7_top_fan0: trip-point2 { temperature = <70000>; hysteresis = <3000>; type = "active"; };
+ cpu7_top_fan1: trip-point3 { temperature = <75000>; hysteresis = <3000>; type = "active"; };
+ cpu7_top_fan2: trip-point4 { temperature = <80000>; hysteresis = <3000>; type = "active"; };
+ };
+
+ cooling-maps {
+ map0 { trip = <&cpu7_top_fan0>; cooling-device = <&pwm_fan 4 5>; };
+ map1 { trip = <&cpu7_top_fan1>; cooling-device = <&pwm_fan 5 6>; };
+ map2 { trip = <&cpu7_top_fan2>; cooling-device = <&pwm_fan 6 7>; };
+ };
+ };
+ gpuss-0-thermal {
+ polling-delay = <200>;
+ trips {
+ gpuss0_fan0: trip-point3 { temperature = <70000>; hysteresis = <3000>; type = "active"; };
+ gpuss0_fan1: trip-point4 { temperature = <75000>; hysteresis = <3000>; type = "active"; };
+ gpuss0_fan2: trip-point5 { temperature = <80000>; hysteresis = <3000>; type = "active"; };
+ };
+
+ cooling-maps {
+ map1 { trip = <&gpuss0_fan0>; cooling-device = <&pwm_fan 4 5>; };
+ map2 { trip = <&gpuss0_fan1>; cooling-device = <&pwm_fan 5 6>; };
+ map3 { trip = <&gpuss0_fan2>; cooling-device = <&pwm_fan 6 7>; };
+ };
+ };
+ gpuss-1-thermal {
+ polling-delay = <200>;
+ trips {
+ gpuss1_fan0: trip-point3 { temperature = <70000>; hysteresis = <3000>; type = "active"; };
+ gpuss1_fan1: trip-point4 { temperature = <75000>; hysteresis = <3000>; type = "active"; };
+ gpuss1_fan2: trip-point5 { temperature = <80000>; hysteresis = <3000>; type = "active"; };
+ };
+
+ cooling-maps {
+ map1 { trip = <&gpuss1_fan0>; cooling-device = <&pwm_fan 4 5>; };
+ map2 { trip = <&gpuss1_fan1>; cooling-device = <&pwm_fan 5 6>; };
+ map3 { trip = <&gpuss1_fan2>; cooling-device = <&pwm_fan 6 7>; };
+ };
+ };
+ gpuss-2-thermal {
+ polling-delay = <200>;
+ trips {
+ gpuss2_fan0: trip-point3 { temperature = <70000>; hysteresis = <3000>; type = "active"; };
+ gpuss2_fan1: trip-point4 { temperature = <75000>; hysteresis = <3000>; type = "active"; };
+ gpuss2_fan2: trip-point5 { temperature = <80000>; hysteresis = <3000>; type = "active"; };
+ };
+
+ cooling-maps {
+ map1 { trip = <&gpuss2_fan0>; cooling-device = <&pwm_fan 4 5>; };
+ map2 { trip = <&gpuss2_fan1>; cooling-device = <&pwm_fan 5 6>; };
+ map3 { trip = <&gpuss2_fan2>; cooling-device = <&pwm_fan 6 7>; };
+ };
+ };
+ gpuss-3-thermal {
+ polling-delay = <200>;
+ trips {
+ gpuss3_fan0: trip-point3 { temperature = <70000>; hysteresis = <3000>; type = "active"; };
+ gpuss3_fan1: trip-point4 { temperature = <75000>; hysteresis = <3000>; type = "active"; };
+ gpuss3_fan2: trip-point5 { temperature = <80000>; hysteresis = <3000>; type = "active"; };
+ };
+
+ cooling-maps {
+ map1 { trip = <&gpuss3_fan0>; cooling-device = <&pwm_fan 4 5>; };
+ map2 { trip = <&gpuss3_fan1>; cooling-device = <&pwm_fan 5 6>; };
+ map3 { trip = <&gpuss3_fan2>; cooling-device = <&pwm_fan 6 7>; };
+ };
+ };
+ gpuss-4-thermal {
+ polling-delay = <200>;
+ trips {
+ gpuss4_fan0: trip-point3 { temperature = <70000>; hysteresis = <3000>; type = "active"; };
+ gpuss4_fan1: trip-point4 { temperature = <75000>; hysteresis = <3000>; type = "active"; };
+ gpuss4_fan2: trip-point5 { temperature = <80000>; hysteresis = <3000>; type = "active"; };
+ };
+
+ cooling-maps {
+ map1 { trip = <&gpuss4_fan0>; cooling-device = <&pwm_fan 4 5>; };
+ map2 { trip = <&gpuss4_fan1>; cooling-device = <&pwm_fan 5 6>; };
+ map3 { trip = <&gpuss4_fan2>; cooling-device = <&pwm_fan 6 7>; };
+ };
+ };
+ gpuss-5-thermal {
+ polling-delay = <200>;
+ trips {
+ gpuss5_fan0: trip-point3 { temperature = <70000>; hysteresis = <3000>; type = "active"; };
+ gpuss5_fan1: trip-point4 { temperature = <75000>; hysteresis = <3000>; type = "active"; };
+ gpuss5_fan2: trip-point5 { temperature = <80000>; hysteresis = <3000>; type = "active"; };
+ };
+
+ cooling-maps {
+ map1 { trip = <&gpuss5_fan0>; cooling-device = <&pwm_fan 4 5>; };
+ map2 { trip = <&gpuss5_fan1>; cooling-device = <&pwm_fan 5 6>; };
+ map3 { trip = <&gpuss5_fan2>; cooling-device = <&pwm_fan 6 7>; };
+ };
+ };
+ gpuss-6-thermal {
+ polling-delay = <200>;
+ trips {
+ gpuss6_fan0: trip-point3 { temperature = <70000>; hysteresis = <3000>; type = "active"; };
+ gpuss6_fan1: trip-point4 { temperature = <75000>; hysteresis = <3000>; type = "active"; };
+ gpuss6_fan2: trip-point5 { temperature = <80000>; hysteresis = <3000>; type = "active"; };
+ };
+
+ cooling-maps {
+ map1 { trip = <&gpuss6_fan0>; cooling-device = <&pwm_fan 4 5>; };
+ map2 { trip = <&gpuss6_fan1>; cooling-device = <&pwm_fan 5 6>; };
+ map3 { trip = <&gpuss6_fan2>; cooling-device = <&pwm_fan 6 7>; };
+ };
+ };
+ gpuss-7-thermal {
+ polling-delay = <200>;
+ trips {
+ gpuss7_fan0: trip-point3 { temperature = <70000>; hysteresis = <3000>; type = "active"; };
+ gpuss7_fan1: trip-point4 { temperature = <75000>; hysteresis = <3000>; type = "active"; };
+ gpuss7_fan2: trip-point5 { temperature = <80000>; hysteresis = <3000>; type = "active"; };
+ };
+
+ cooling-maps {
+ map1 { trip = <&gpuss7_fan0>; cooling-device = <&pwm_fan 4 5>; };
+ map2 { trip = <&gpuss7_fan1>; cooling-device = <&pwm_fan 5 6>; };
+ map3 { trip = <&gpuss7_fan2>; cooling-device = <&pwm_fan 6 7>; };
+ };
+ };
+ };
+
+ sound {
+ compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard";
+ pinctrl-0 = <&lpi_i2s3_active>;
@@ -1162,7 +1379,6 @@ index 000000000000..0954c1854a05
+ no-sdio;
+ no-mmc;
+
+ qcom,use-level-shifter;
+ qcom,dll-config = <0x0007442c>;
+ /delete-property/ sdhci-caps-mask;
+
@@ -1417,14 +1633,14 @@ index 000000000000..0954c1854a05
+ vccq-max-microamp = <1200000>;
+ vdd-hba-supply = <&vreg_l3g_1p2>;
+
+ status = "okay";
+ status = "disabled";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l1d_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+ status = "disabled";
+};
+
+&usb_1 {

58
projects/ROCKNIX/devices/SM8550/patches/linux/0203_arm64--dts--qcom--Add-AYN-Odin2-Portal.patch
View File

@@ -27,7 +27,7 @@ new file mode 100644
index 000000000000..ac9b786e626e
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2portal.dts
@@ -0,0 +1,238 @@
@@ -0,0 +1,294 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Teguh Sobirin.
@@ -64,6 +64,62 @@ index 000000000000..ac9b786e626e
+ gpio = <&tlmm 142 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ multi-ledr1 {
+ compatible = "leds-group-multicolor";
+ color = <LED_COLOR_ID_RGB>;
+ function = "r1";
+ leds = <&ledr_r4>, <&ledr_g4>, <&ledr_b4>;
+ };
+
+ multi-ledl1 {
+ compatible = "leds-group-multicolor";
+ color = <LED_COLOR_ID_RGB>;
+ function = "l1";
+ leds = <&ledl_r4>, <&ledl_g4>, <&ledl_b4>;
+ };
+
+ multi-ledr2 {
+ compatible = "leds-group-multicolor";
+ color = <LED_COLOR_ID_RGB>;
+ function = "r2";
+ leds = <&ledr_r1>, <&ledr_g1>, <&ledr_b1>;
+ };
+
+ multi-ledl2 {
+ compatible = "leds-group-multicolor";
+ color = <LED_COLOR_ID_RGB>;
+ function = "l2";
+ leds = <&ledl_r1>, <&ledl_g1>, <&ledl_b1>;
+ };
+
+ multi-ledr3 {
+ compatible = "leds-group-multicolor";
+ color = <LED_COLOR_ID_RGB>;
+ function = "r3";
+ leds = <&ledr_r2>, <&ledr_g2>, <&ledr_b2>;
+ };
+
+ multi-ledl3 {
+ compatible = "leds-group-multicolor";
+ color = <LED_COLOR_ID_RGB>;
+ function = "l3";
+ leds = <&ledl_r2>, <&ledl_g2>, <&ledl_b2>;
+ };
+
+ multi-ledr4 {
+ compatible = "leds-group-multicolor";
+ color = <LED_COLOR_ID_RGB>;
+ function = "r4";
+ leds = <&ledr_r3>, <&ledr_g3>, <&ledr_b3>;
+ };
+
+ multi-ledl4 {
+ compatible = "leds-group-multicolor";
+ color = <LED_COLOR_ID_RGB>;
+ function = "l4";
+ leds = <&ledl_r3>, <&ledl_g3>, <&ledl_b3>;
+ };
+};
+
+&display_panel {

58
projects/ROCKNIX/devices/SM8550/patches/linux/0204_arm64--dts--qcom--Add-AYN-Thor.patch
View File

@@ -27,7 +27,7 @@ new file mode 100644
index 000000000000..f107519c0e5c
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-ayn-thor.dts
@@ -0,0 +1,374 @@
@@ -0,0 +1,430 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Teguh Sobirin.
@@ -129,6 +129,62 @@ index 000000000000..f107519c0e5c
+ gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ multi-ledr1 {
+ compatible = "leds-group-multicolor";
+ color = <LED_COLOR_ID_RGB>;
+ function = "r1";
+ leds = <&ledr_r4>, <&ledr_g4>, <&ledr_b4>;
+ };
+
+ multi-ledl1 {
+ compatible = "leds-group-multicolor";
+ color = <LED_COLOR_ID_RGB>;
+ function = "l1";
+ leds = <&ledl_r4>, <&ledl_g4>, <&ledl_b4>;
+ };
+
+ multi-ledr2 {
+ compatible = "leds-group-multicolor";
+ color = <LED_COLOR_ID_RGB>;
+ function = "r2";
+ leds = <&ledr_r1>, <&ledr_g1>, <&ledr_b1>;
+ };
+
+ multi-ledl2 {
+ compatible = "leds-group-multicolor";
+ color = <LED_COLOR_ID_RGB>;
+ function = "l2";
+ leds = <&ledl_r1>, <&ledl_g1>, <&ledl_b1>;
+ };
+
+ multi-ledr3 {
+ compatible = "leds-group-multicolor";
+ color = <LED_COLOR_ID_RGB>;
+ function = "r3";
+ leds = <&ledr_r2>, <&ledr_g2>, <&ledr_b2>;
+ };
+
+ multi-ledl3 {
+ compatible = "leds-group-multicolor";
+ color = <LED_COLOR_ID_RGB>;
+ function = "l3";
+ leds = <&ledl_r2>, <&ledl_g2>, <&ledl_b2>;
+ };
+
+ multi-ledr4 {
+ compatible = "leds-group-multicolor";
+ color = <LED_COLOR_ID_RGB>;
+ function = "r4";
+ leds = <&ledr_r3>, <&ledr_g3>, <&ledr_b3>;
+ };
+
+ multi-ledl4 {
+ compatible = "leds-group-multicolor";
+ color = <LED_COLOR_ID_RGB>;
+ function = "l4";
+ leds = <&ledl_r3>, <&ledl_g3>, <&ledl_b3>;
+ };
+};
+
+&display_panel {

10
projects/ROCKNIX/devices/SM8550/patches/linux/0210_arm64--dts--qcom--Add-AYANEO-Pocket-Common.patch
View File

@@ -3,7 +3,7 @@ new file mode 100644
index 000000000000..58d9ab342fe9
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocket-common.dtsi
@@ -0,0 +1,1482 @@
@@ -0,0 +1,1474 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Teguh Sobirin.
@@ -177,13 +177,6 @@ index 000000000000..58d9ab342fe9
+ reg = <0 0xfce00000 0 0x2900000>;
+ no-map;
+ };
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ size = <0x0 0x18000000>;
+ reusable;
+ linux,cma-default;
+ };
+ };
+
+ sound {
@@ -1066,7 +1059,6 @@ index 000000000000..58d9ab342fe9
+ no-sdio;
+ no-mmc;
+
+ qcom,use-level-shifter;
+ qcom,dll-config = <0x0007442c>;
+// /delete-property/ sdhci-caps-mask;
+