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RK3326: raise the TPL DDR frequency from 333MHz to 786MHz

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The performance gap users report against dArkOS ("more FPS, more
stable") is dominated by memory bandwidth. Our TPL blob initialises
every DDR type at 333MHz (verified via ddrbin_tool -g: lp2/ddr3/lp3/
ddr4/lp4 all 333) and mainline has no px30 dmc driver, so the memory
never leaves 333MHz. dArkOS runs the BSP dmc_ondemand governor, which
scales the same boards up to the 786MHz ceiling of the vendor R36S DTB
dmc table (528/666/786, verified by decompiling their shipped DTB), and
even its powersave mode pins 528MHz: their WORST case has 60% more
memory bandwidth than our best.

Rewrite the frequency fields inside the TPL with Rockchip's ddrbin_tool
(the long-standing ArkOS "DDR fix") so DDR comes up at 786MHz from
boot, for both the standard and the UART5 clone TPL variants. Override
with RK3326_DDR_FREQ=666 if a board proves unstable.

MUST be boot-tested on hardware before any release: a board whose DDR
cannot run 786MHz will hang in the TPL before U-Boot even starts.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
This commit is contained in:
Douglas Teles
2026-07-01 22:59:19 -03:00
parent 235f113c25
commit d80eb6c482
1 changed files with 19 additions and 2 deletions
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projects/ArchR/packages/tools/rkbin/package.mk
+19 -2
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@@ -22,8 +22,25 @@ PKG_URL="https://github.com/rockchip-linux/rkbin/archive/${PKG_VERSION}.tar.gz"
post_unpack() {
if [ "${DEVICE}" == "RK3326" ]; then
# RK3326: tune TPL for UART5 used on K36 clones
cp -v ${PKG_BUILD}/bin/rk33/rk3326_ddr_333MHz_*.bin ${PKG_BUILD}/rk3326_ddr_uart5.bin
# RK3326: the stock TPL blob initialises every DDR type at 333MHz and
# mainline has no px30 dmc driver, so the memory stays at 333MHz for
# the life of the system. That is far below what the BSP-based OSes on
# the same boards run: dArkOS scales the DDR with dmc_ondemand up to
# the 786MHz BSP ceiling and pins 528MHz even in its powersave mode.
# Rewrite the frequency fields inside the TPL with Rockchip's own
# ddrbin_tool (the long-standing ArkOS "DDR fix") so the memory comes
# up at speed from boot. Override with RK3326_DDR_FREQ=666 if a board
# proves unstable at 786.
RK3326_DDR_FREQ="${RK3326_DDR_FREQ:-786}"
DDR_BIN="$(ls ${PKG_BUILD}/bin/rk33/rk3326_ddr_333MHz_*.bin)"
${PKG_BUILD}/tools/ddrbin_tool.py rk3326 -g ${PKG_BUILD}/rk3326_ddr_freq.txt ${DDR_BIN}
sed -i -E "s|^(lp2_freq|ddr3_freq|lp3_freq|ddr4_freq|lp4_freq)=.*|\1=${RK3326_DDR_FREQ}|" ${PKG_BUILD}/rk3326_ddr_freq.txt
${PKG_BUILD}/tools/ddrbin_tool.py rk3326 ${PKG_BUILD}/rk3326_ddr_freq.txt ${DDR_BIN} >/dev/null
echo "rkbin: RK3326 TPL DDR frequency set to ${RK3326_DDR_FREQ}MHz"
# tune a second TPL copy for UART5 used on K36 clones (inherits the
# DDR frequency edit above)
cp -v ${DDR_BIN} ${PKG_BUILD}/rk3326_ddr_uart5.bin
${PKG_BUILD}/tools/ddrbin_tool.py rk3326 -g ${PKG_BUILD}/rk3326_ddr_uart5.txt ${PKG_BUILD}/rk3326_ddr_uart5.bin
sed -i 's|uart id=.*$|uart id=5|' ${PKG_BUILD}/rk3326_ddr_uart5.txt
${PKG_BUILD}/tools/ddrbin_tool.py rk3326 ${PKG_BUILD}/rk3326_ddr_uart5.txt ${PKG_BUILD}/rk3326_ddr_uart5.bin >/dev/null