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Allwinner: Add support for Tanix TX6

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This commit is contained in:
Jernej Skrabec
2019-06-27 17:20:39 +02:00
parent 8f49486c1a
commit cebeaa2927
9 changed files with 2800 additions and 2 deletions
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344
projects/Allwinner/devices/H6/patches/linux/11-pwm.patch Normal file
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@@ -0,0 +1,344 @@
From 0e014d5d469b49173f89897c898ee4d350f2b183 Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@siol.net>
Date: Fri, 26 Jul 2019 17:31:20 +0200
Subject: [PATCH 1/5] pwm: sun4i: Add a quirk for reset line
H6 PWM core needs deasserted reset line in order to work.
Add a quirk for it.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/pwm/pwm-sun4i.c | 27 +++++++++++++++++++++++++--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index de78c824bbfd..1b7be8fbde86 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -16,6 +16,7 @@
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
+#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/time.h>
@@ -72,12 +73,14 @@ static const u32 prescaler_table[] = {
struct sun4i_pwm_data {
bool has_prescaler_bypass;
+ bool has_reset;
unsigned int npwm;
};
struct sun4i_pwm_chip {
struct pwm_chip chip;
struct clk *clk;
+ struct reset_control *rst;
void __iomem *base;
spinlock_t ctrl_lock;
const struct sun4i_pwm_data *data;
@@ -371,6 +374,14 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
if (IS_ERR(pwm->clk))
return PTR_ERR(pwm->clk);
+ if (pwm->data->has_reset) {
+ pwm->rst = devm_reset_control_get(&pdev->dev, NULL);
+ if (IS_ERR(pwm->rst))
+ return PTR_ERR(pwm->rst);
+
+ reset_control_deassert(pwm->rst);
+ }
+
pwm->chip.dev = &pdev->dev;
pwm->chip.ops = &sun4i_pwm_ops;
pwm->chip.base = -1;
@@ -383,19 +394,31 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
ret = pwmchip_add(&pwm->chip);
if (ret < 0) {
dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
- return ret;
+ goto err_pwm_add;
}
platform_set_drvdata(pdev, pwm);
return 0;
+
+err_pwm_add:
+ reset_control_assert(pwm->rst);
+
+ return ret;
}
static int sun4i_pwm_remove(struct platform_device *pdev)
{
struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
+ int ret;
+
+ ret = pwmchip_remove(&pwm->chip);
+ if (ret)
+ return ret;
- return pwmchip_remove(&pwm->chip);
+ reset_control_assert(pwm->rst);
+
+ return 0;
}
static struct platform_driver sun4i_pwm_driver = {
--
2.22.1
From 56755aaa0610275f5348ac840c76b4e2b8572281 Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@siol.net>
Date: Fri, 26 Jul 2019 17:42:06 +0200
Subject: [PATCH 2/5] pwm: sun4i: Add a quirk for bus clock
H6 PWM core needs bus clock to be enabled in order to work.
Add a quirk for it.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/pwm/pwm-sun4i.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 1b7be8fbde86..7d3ac3f2dc3f 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -72,6 +72,7 @@ static const u32 prescaler_table[] = {
};
struct sun4i_pwm_data {
+ bool has_bus_clock;
bool has_prescaler_bypass;
bool has_reset;
unsigned int npwm;
@@ -79,6 +80,7 @@ struct sun4i_pwm_data {
struct sun4i_pwm_chip {
struct pwm_chip chip;
+ struct clk *bus_clk;
struct clk *clk;
struct reset_control *rst;
void __iomem *base;
@@ -382,6 +384,16 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
reset_control_deassert(pwm->rst);
}
+ if (pwm->data->has_bus_clock) {
+ pwm->bus_clk = devm_clk_get(&pdev->dev, "bus");
+ if (IS_ERR(pwm->bus_clk)) {
+ ret = PTR_ERR(pwm->bus_clk);
+ goto err_bus;
+ }
+
+ clk_prepare_enable(pwm->bus_clk);
+ }
+
pwm->chip.dev = &pdev->dev;
pwm->chip.ops = &sun4i_pwm_ops;
pwm->chip.base = -1;
@@ -402,6 +414,8 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
return 0;
err_pwm_add:
+ clk_disable_unprepare(pwm->bus_clk);
+err_bus:
reset_control_assert(pwm->rst);
return ret;
@@ -416,6 +430,7 @@ static int sun4i_pwm_remove(struct platform_device *pdev)
if (ret)
return ret;
+ clk_disable_unprepare(pwm->bus_clk);
reset_control_assert(pwm->rst);
return 0;
--
2.22.1
From 68c1b688e1e57ce22dfc6a72ad2b6f403953823a Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@siol.net>
Date: Fri, 26 Jul 2019 17:45:40 +0200
Subject: [PATCH 3/5] pwm: sun4i: Add support for H6 PWM
Now that sun4i PWM driver supports deasserting reset line and enabling
bus clock, support for H6 PWM can be added.
Note that while H6 PWM has two channels, only first one is wired to
output pin. Second channel is used as a clock source to companion AC200
chip which is bundled into same package.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/pwm/pwm-sun4i.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 7d3ac3f2dc3f..9e0eca79ff88 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -331,6 +331,13 @@ static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
.npwm = 1,
};
+static const struct sun4i_pwm_data sun50i_pwm_dual_bypass_clk_rst = {
+ .has_bus_clock = true,
+ .has_prescaler_bypass = true,
+ .has_reset = true,
+ .npwm = 2,
+};
+
static const struct of_device_id sun4i_pwm_dt_ids[] = {
{
.compatible = "allwinner,sun4i-a10-pwm",
@@ -347,6 +354,9 @@ static const struct of_device_id sun4i_pwm_dt_ids[] = {
}, {
.compatible = "allwinner,sun8i-h3-pwm",
.data = &sun4i_pwm_single_bypass,
+ }, {
+ .compatible = "allwinner,sun50i-h6-pwm",
+ .data = &sun50i_pwm_dual_bypass_clk_rst,
}, {
/* sentinel */
},
--
2.22.1
From b78fc7d807a6d4b715cad9b87c134a3cb6289f62 Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@siol.net>
Date: Fri, 26 Jul 2019 17:53:36 +0200
Subject: [PATCH 4/5] pwm: sun4i: Add support to output source clock directly
PWM core has an option to bypass whole logic and output unchanged source
clock as PWM output. This is achieved by enabling bypass bit.
Note that when bypass is enabled, no other setting has any meaning, not
even enable bit.
This mode of operation is needed to achieve high enough frequency to
serve as clock source for AC200 chip, which is integrated into same
package as H6 SoC.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/pwm/pwm-sun4i.c | 31 ++++++++++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 9e0eca79ff88..848cff26f385 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -120,6 +120,19 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
+ /*
+ * PWM chapter in H6 manual has a diagram which explains that if bypass
+ * bit is set, no other setting has any meaning. Even more, experiment
+ * proved that also enable bit is ignored in this case.
+ */
+ if (val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) {
+ state->period = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, clk_rate);
+ state->duty_cycle = state->period / 2;
+ state->polarity = PWM_POLARITY_NORMAL;
+ state->enabled = true;
+ return;
+ }
+
if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
sun4i_pwm->data->has_prescaler_bypass)
prescaler = 1;
@@ -211,7 +224,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
{
struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
struct pwm_state cstate;
- u32 ctrl;
+ u32 ctrl, clk_rate;
+ bool bypass;
int ret;
unsigned int delay_us;
unsigned long now;
@@ -226,6 +240,16 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
}
}
+ /*
+ * Although it would make much more sense to check for bypass in
+ * sun4i_pwm_calculate(), value of bypass bit also depends on "enabled".
+ * Period is allowed to be rounded up or down.
+ */
+ clk_rate = clk_get_rate(sun4i_pwm->clk);
+ bypass = (state->period == NSEC_PER_SEC / clk_rate ||
+ state->period == DIV_ROUND_UP(NSEC_PER_SEC, clk_rate)) &&
+ state->enabled;
+
spin_lock(&sun4i_pwm->ctrl_lock);
ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
@@ -273,6 +297,11 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
}
+ if (bypass)
+ ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
+ else
+ ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
+
sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
spin_unlock(&sun4i_pwm->ctrl_lock);
--
2.22.1
From e5fa4d2acf30ccac7f3817c299a2fa6f20c23c50 Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@siol.net>
Date: Fri, 26 Jul 2019 18:02:50 +0200
Subject: [PATCH 5/5] arm64: dts: allwinner: h6: Add PWM node
Allwinner H6 PWM is similar to that in A20 except that it has additional
bus clock and reset line.
Note that first PWM channel is connected to output pin and second
channel is used internally, as a clock source to AC200 co-packaged chip.
This means that any combination of these two channels can be used and
thus it doesn't make sense to add pinctrl nodes at this point.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index e8bed58e7246..c1abd805cfdc 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -229,6 +229,16 @@
status = "disabled";
};
+ pwm: pwm@300a000 {
+ compatible = "allwinner,sun50i-h6-pwm";
+ reg = <0x0300a000 0x400>;
+ clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
+ clock-names = "pwm", "bus";
+ resets = <&ccu RST_BUS_PWM>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
pio: pinctrl@300b000 {
compatible = "allwinner,sun50i-h6-pinctrl";
reg = <0x0300b000 0x400>;
--
2.22.1

103
projects/Allwinner/devices/H6/patches/linux/12-ac200-nodes.patch Normal file
View File

@@ -0,0 +1,103 @@
From fa11b2ef7b8359f70d010d3b76b7dfd90250dc5c Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@siol.net>
Date: Fri, 16 Aug 2019 16:40:20 +0200
Subject: [PATCH] arm64: dts: allwinner: h6: Add AC200 EPHY related nodes
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 51 ++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 8eec8685a50b..5eeb7da7a0ab 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -17,6 +17,16 @@
#address-cells = <1>;
#size-cells = <1>;
+ ac200_pwm_clk: ac200_clk {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1_pin>;
+ pwms = <&pwm 1 42 0>;
+ status = "disabled";
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -218,6 +228,12 @@
sid: efuse@3006000 {
compatible = "allwinner,sun50i-h6-sid";
reg = <0x03006000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ephy_calib: ephy_calib@2c {
+ reg = <0x2c 0x2>;
+ };
};
watchdog: watchdog@30090a0 {
@@ -268,6 +284,11 @@
drive-strength = <40>;
};
+ i2c3_pins: i2c3-pins {
+ pins = "PB17", "PB18";
+ function = "i2c3";
+ };
+
hdmi_pins: hdmi-pins {
pins = "PH8", "PH9", "PH10";
function = "hdmi";
@@ -290,6 +311,11 @@
bias-pull-up;
};
+ pwm1_pin: pwm1-pin {
+ pins = "PB19";
+ function = "pwm1";
+ };
+
mmc2_pins: mmc2-pins {
pins = "PC1", "PC4", "PC5", "PC6",
"PC7", "PC8", "PC9", "PC10",
@@ -408,6 +434,31 @@
status = "disabled";
};
+ i2c3: i2c@5002c00 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x05002c00 0x400>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C3>;
+ resets = <&ccu RST_BUS_I2C3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ac200: mfd@10 {
+ compatible = "x-powers,ac200";
+ reg = <0x10>;
+ clocks = <&ac200_pwm_clk>;
+
+ ac200_ephy: phy {
+ compatible = "x-powers,ac200-ephy";
+ nvmem-cells = <&ephy_calib>;
+ nvmem-cell-names = "ephy_calib";
+ };
+ };
+ };
+
emac: ethernet@5020000 {
compatible = "allwinner,sun50i-h6-emac",
"allwinner,sun50i-a64-emac";
--
2.22.1

185
projects/Allwinner/devices/H6/patches/linux/13-Tanix-TX6.patch Normal file
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@@ -0,0 +1,185 @@
From 13300ba386795eceeaf47fc199d5e8683dcd2ff8 Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@siol.net>
Date: Mon, 24 Jun 2019 12:17:58 +0200
Subject: [PATCH 1/2] Tanix TX6 DT
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
arch/arm64/boot/dts/allwinner/Makefile | 1 +
.../dts/allwinner/sun50i-h6-tanix-tx6.dts | 133 ++++++++++++++++++
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 7 +
3 files changed, 141 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index f6db0611cb85..395fe76f6819 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -25,3 +25,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
new file mode 100644
index 000000000000..c90af0b29f28
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (c) 2019 Jernej Skrabec <jernej.skrabec@siol.net>
+ */
+
+/dts-v1/;
+
+#include "sun50i-h6.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Tanix TX6";
+ compatible = "tanix,tanix-tx6", "allwinner,sun50i-h6";
+
+ aliases {
+ ethernet0 = &emac;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+ ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&ac200_pwm_clk {
+ status = "okay";
+};
+
+&de {
+ status = "okay";
+};
+
+&dwc3 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ext_rmii_pins>;
+ phy-mode = "rmii";
+ phy-handle = <&ext_rmii_phy>;
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&mdio {
+ ext_rmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&pwm {
+ status = "okay";
+};
+
+&r_ir {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ph_pins>;
+ status = "okay";
+};
+
+&usb2otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb2phy {
+ status = "okay";
+};
+
+&usb3phy {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 7628a7c83096..305e093c910f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -251,6 +251,13 @@
drive-strength = <40>;
};
+ ext_rmii_pins: rmii_pins {
+ pins = "PA0", "PA1", "PA2", "PA3", "PA4",
+ "PA5", "PA6", "PA7", "PA8", "PA9";
+ function = "emac";
+ drive-strength = <40>;
+ };
+
hdmi_pins: hdmi-pins {
pins = "PH8", "PH9", "PH10";
function = "hdmi";
--
2.22.0

1
projects/Allwinner/devices/H6/patches/u-boot/002-orange-pi-3-support.patch
View File

@@ -353,6 +353,7 @@ index 0000000000..9a9cd28142
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I_H6=y
+CONFIG_SUNXI_DRAM_H6_LPDDR3=y
+CONFIG_MMC0_CD_PIN="PF6"
+# CONFIG_PSCI_RESET is not set
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2

1402
projects/Allwinner/devices/H6/patches/u-boot/006-DDR3.patch Normal file
View File

File diff suppressed because it is too large Load Diff

51
projects/Allwinner/devices/H6/patches/u-boot/007-ethernet-hack.patch Normal file
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@@ -0,0 +1,51 @@
From 9e077d6ebaa5a76b0c91cbe6aabb66106e95caba Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@siol.net>
Date: Thu, 11 Jul 2019 23:28:58 +0200
Subject: [PATCH] ethernet hack
---
arch/arm/dts/sun50i-h6-eachlink-h6-mini.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/dts/sun50i-h6-eachlink-h6-mini.dts b/arch/arm/dts/sun50i-h6-eachlink-h6-mini.dts
index c217955a39..5c0099f1a7 100644
--- a/arch/arm/dts/sun50i-h6-eachlink-h6-mini.dts
+++ b/arch/arm/dts/sun50i-h6-eachlink-h6-mini.dts
@@ -16,6 +16,7 @@
compatible = "eachlink,h6-mini", "allwinner,sun50i-h6";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};
@@ -55,6 +56,12 @@
status = "okay";
};
+&emac {
+ phy-mode = "rmii";
+ phy-handle = <&ext_rmii_phy>;
+ status = "okay";
+};
+
&hdmi {
status = "okay";
};
@@ -74,6 +81,13 @@
status = "okay";
};
+&mdio {
+ ext_rmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
--
2.22.0

6
projects/Allwinner/linux/linux.aarch64.conf
View File

@@ -1796,6 +1796,7 @@ CONFIG_SWPHY=y
#
# MII PHY device drivers
#
CONFIG_AC200_PHY=y
# CONFIG_AMD_PHY is not set
# CONFIG_AQUANTIA_PHY is not set
# CONFIG_AX88796B_PHY is not set
@@ -2761,6 +2762,7 @@ CONFIG_MFD_CORE=y
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
# CONFIG_MFD_AC100 is not set
CONFIG_MFD_AC200=y
CONFIG_MFD_AXP20X=y
CONFIG_MFD_AXP20X_I2C=y
CONFIG_MFD_AXP20X_RSB=y
@@ -4571,7 +4573,7 @@ CONFIG_COMMON_CLK_SCPI=y
# CONFIG_COMMON_CLK_S2MPS11 is not set
# CONFIG_CLK_QORIQ is not set
# CONFIG_COMMON_CLK_XGENE is not set
# CONFIG_COMMON_CLK_PWM is not set
CONFIG_COMMON_CLK_PWM=y
# CONFIG_COMMON_CLK_VC5 is not set
# CONFIG_COMMON_CLK_FIXED_MMIO is not set
# CONFIG_CLK_SUNXI is not set
@@ -5123,7 +5125,7 @@ CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
# CONFIG_PWM_FSL_FTM is not set
# CONFIG_PWM_PCA9685 is not set
# CONFIG_PWM_SUN4I is not set
CONFIG_PWM_SUN4I=y
#
# IRQ chip support

2
projects/Allwinner/linux/linux.arm.conf
View File

@@ -1704,6 +1704,7 @@ CONFIG_SWPHY=y
#
# MII PHY device drivers
#
# CONFIG_AC200_PHY is not set
# CONFIG_AMD_PHY is not set
# CONFIG_AQUANTIA_PHY is not set
# CONFIG_AX88796B_PHY is not set
@@ -2587,6 +2588,7 @@ CONFIG_MFD_SUN4I_GPADC=y
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
# CONFIG_MFD_AC100 is not set
# CONFIG_MFD_AC200 is not set
CONFIG_MFD_AXP20X=y
CONFIG_MFD_AXP20X_I2C=y
CONFIG_MFD_AXP20X_RSB=y

708
projects/Allwinner/patches/linux/0014-AC200.patch Normal file
View File

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