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Merge pull request #2132 from loki666/sm8650-sdhc2

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linux/sm8650: fix sdhc2 overclock
This commit is contained in:
Philippe Simons
2025-12-17 22:50:50 +01:00
committed by GitHub
parent acfce6eb34 45d9ca648c
commit ab07d1ce84
3 changed files with 128 additions and 0 deletions
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24
projects/ROCKNIX/devices/SM8650/patches/linux/0001-dts-sm8650-add-sdhc2-reset.patch Normal file
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@@ -0,0 +1,24 @@
From 836543c1107d6a1906c2a03eb78adeefbe86552d Mon Sep 17 00:00:00 2001
From: Philippe Simons <simons.philippe@gmail.com>
Date: Wed, 17 Dec 2025 22:39:36 +0100
Subject: [PATCH] dts:sm8650 add sdhc2 reset
---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index ebf1971b1bfb..0285ab282b1e 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -4924,6 +4924,7 @@ sdhc_2: mmc@8804000 {
clock-names = "iface",
"core",
"xo";
+ resets = <&gcc GCC_SDCC2_BCR>;
interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
--
2.52.0

0
projects/ROCKNIX/devices/SM8650/patches/linux/0001-add-ayaneo-pocket-s2-dts.patch → projects/ROCKNIX/devices/SM8650/patches/linux/0100-add-ayaneo-pocket-s2-dts.patch
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104
projects/ROCKNIX/devices/SM8650/patches/linux/20251124_vladimir_zapolskiy_clk_qcom_gcc_sm8x50_use_floor_ops_for_sdcc_rcgs.patch Normal file
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@@ -0,0 +1,104 @@
From git@z Thu Jan 1 00:00:00 1970
Subject: [PATCH 1/2] clk: qcom: gcc-sm8550: Use floor ops for SDCC RCGs
From: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Date: Mon, 24 Nov 2025 23:20:11 +0200
Message-Id: <20251124212012.3660189-2-vladimir.zapolskiy@linaro.org>
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 7bit
In line with commit a27ac3806b0a ("clk: qcom: gcc-sm8450: Use floor ops
for SDCC RCGs") done to fix issues with overclocked SD cards on SM8450
powered boards set floor clock operations for SDCC RCGs on SM8550.
This change fixes initialization of some SD cards, where the problem
is manifested by the SDHC driver:
mmc0: Card appears overclocked; req 50000000 Hz, actual 100000000 Hz
mmc0: error -110 whilst initialising SD card
Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
drivers/clk/qcom/gcc-sm8550.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c
index 862a9bf73bcb..36a5b7de5b55 100644
--- a/drivers/clk/qcom/gcc-sm8550.c
+++ b/drivers/clk/qcom/gcc-sm8550.c
@@ -1025,7 +1025,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.parent_data = gcc_parent_data_9,
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
.flags = CLK_SET_RATE_PARENT,
- .ops = &clk_rcg2_shared_ops,
+ .ops = &clk_rcg2_shared_floor_ops,
},
};
@@ -1048,7 +1048,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
- .ops = &clk_rcg2_shared_ops,
+ .ops = &clk_rcg2_shared_floor_ops,
},
};
--
2.49.0
From git@z Thu Jan 1 00:00:00 1970
Subject: [PATCH 2/2] clk: qcom: gcc-sm8650: Use floor ops for SDCC RCGs
From: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Date: Mon, 24 Nov 2025 23:20:12 +0200
Message-Id: <20251124212012.3660189-3-vladimir.zapolskiy@linaro.org>
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 7bit
In line with commit a27ac3806b0a ("clk: qcom: gcc-sm8450: Use floor ops
for SDCC RCGs") done to fix issues with overclocked SD cards on SM8450
powered boards set floor clock operations for SDCC RCGs on SM8650.
This change fixes initialization of some SD cards, where the problem
is manifested by the SDHC driver:
mmc0: Card appears overclocked; req 50000000 Hz, actual 100000000 Hz
mmc0: error -110 whilst initialising SD card
Fixes: c58225b7e3d7 ("clk: qcom: add the SM8650 Global Clock Controller driver, part 1")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
drivers/clk/qcom/gcc-sm8650.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/gcc-sm8650.c b/drivers/clk/qcom/gcc-sm8650.c
index 24f98062b9dd..2dd6444ce036 100644
--- a/drivers/clk/qcom/gcc-sm8650.c
+++ b/drivers/clk/qcom/gcc-sm8650.c
@@ -1257,7 +1257,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.parent_data = gcc_parent_data_11,
.num_parents = ARRAY_SIZE(gcc_parent_data_11),
.flags = CLK_SET_RATE_PARENT,
- .ops = &clk_rcg2_shared_ops,
+ .ops = &clk_rcg2_shared_floor_ops,
},
};
@@ -1279,7 +1279,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
- .ops = &clk_rcg2_shared_ops,
+ .ops = &clk_rcg2_shared_floor_ops,
},
};
--
2.49.0