linux/sm8650: update patches

projects/ROCKNIX/devices/SM8650/patches/linux/0002-arm64_dts_qcom_sm8650_Enable_UHS-I_SDR50_and_SDR104.patch.disabled

@@ -0,0 +1,62 @@
+From c38a16e8f52873ad357ce93689d76360a33df7b2 Mon Sep 17 00:00:00 2001
+From: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
+Date: Wed, 26 Nov 2025 03:20:43 +0200
+Subject: [PATCH] arm64: dts: qcom: sm8650: Enable UHS-I SDR50 and SDR104 SD
+ card modes
+
+The restriction on UHS-I speed modes was added to all SM8650 platforms
+by copying it from SM8450 and SM8550 dtsi files, and it was an actually
+reproducible problem due to the overclocking of SD cards. Since the latter
+issue has been fixed in the SM8650 GCC driver, UHS-I speed modes are
+working fine on SM8650 boards, below is the test performed on SM8650-HDK:
+
+SDR50 speed mode:
+
+    mmc0: new UHS-I speed SDR50 SDHC card at address 0001
+    mmcblk0: mmc0:0001 00000 14.6 GiB
+     mmcblk0: p1
+
+    % dd if=/dev/mmcblk0p1 of=/dev/null bs=1M count=1024
+    1024+0 records in
+    1024+0 records out
+    1073741824 bytes (1.1 GB, 1.0 GiB) copied, 24.8086 s, 43.3 MB/s
+
+    SDR104 speed mode:
+
+    mmc0: new UHS-I speed SDR104 SDHC card at address 59b4
+    mmcblk0: mmc0:59b4 USDU1 28.3 GiB
+     mmcblk0: p1
+
+    % dd if=/dev/mmcblk0p1 of=/dev/null bs=1M count=1024
+    1024+0 records in
+    1024+0 records out
+    1073741824 bytes (1.1 GB, 1.0 GiB) copied, 12.9448 s, 82.9 MB/s
+
+Unset the UHS-I speed mode restrictions from the SM8550 platform dtsi
+file, there is no indication that the SDHC controller is broken.
+
+Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
+Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
+Link: https://patch.msgid.link/20251126012043.3764567-4-vladimir.zapolskiy@linaro.org
+Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
+---
+ arch/arm64/boot/dts/qcom/sm8650.dtsi | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
+index 3ddb5c3f097c..7b0f8f664af9 100644
+--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
++++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
+@@ -5032,9 +5032,6 @@
+ 
+ 			bus-width = <4>;
+ 
+-			/* Forbid SDR104/SDR50 - broken hw! */
+-			sdhci-caps-mask = <0x3 0>;
+-
+ 			qcom,dll-config = <0x0007642c>;
+ 			qcom,ddr-config = <0x80040868>;
+ 
+-- 
+GitLab

projects/ROCKNIX/devices/SM8650/patches/linux/0020-audioreach-Add-dedicated-WSA2-support.patch

@@ -25,14 +25,14 @@ index 2365424a9b42bf..fb34c61fb94b81 100644
  	intf_cfg->cfg.lpaif_type = module->hw_interface_type;
  	intf_cfg->cfg.intf_index = module->hw_interface_idx;
 -	intf_cfg->cfg.active_channels_mask = (1 << cfg->num_channels) - 1;
-+	dev_err(graph->dev, "IDX: 0x%08X, TYPE: 0x%08X", module->hw_interface_idx, module->hw_interface_type);
++	// dev_err(graph->dev, "IDX: 0x%08X, TYPE: 0x%08X", module->hw_interface_idx, module->hw_interface_type);
 +
 +	if((intf_cfg->cfg.lpaif_type == 7 && cfg->num_channels <= 2 && intf_cfg->cfg.intf_index == 1)
 +		|| ((intf_cfg->cfg.intf_index == 1) && (intf_cfg->cfg.lpaif_type == 2) && (cfg->num_channels <= 2) && (last_active_channel_mask>>2 & 0b11) != 0)) // Dedicated WSA2 RX0
 +	{
 +		intf_cfg->cfg.active_channels_mask = ((1 << cfg->num_channels) - 1) << 2; 
 +		last_active_channel_mask = intf_cfg->cfg.active_channels_mask;
-+		dev_err(graph->dev, "Setting mask to 0b1100");
++		// dev_err(graph->dev, "Setting mask to 0b1100");
 +		intf_cfg->cfg.lpaif_type = 2;	// ADSO do not support WSA2 DMA
 +		module->hw_interface_type = 2;	// so set lpaif type to WSA after set active channel mask
 +	} else

projects/ROCKNIX/devices/SM8650/patches/linux/0044_mmc--sdhci-msm--Toggle-the-FIFO-write-clock-after-.patch

@@ -1,99 +0,0 @@
-From 10c0d24c9ab36e166b717bc89a0c0d7ec668c978 Mon Sep 17 00:00:00 2001
-From: Ram Prakash Gupta <quic_rampraka@quicinc.com>
-Date: Tue, 22 Oct 2024 16:40:25 +0530
-Subject: [PATCH] mmc: sdhci-msm: Toggle the FIFO write clock after ungate
-
-For Qualcomm SoCs with sdcc minor version 6B and more, command path
-state machine is getting corrupted post clock ungate which is leading
-to software timeout.
-
-Toggle the write fifo clock to reset the async fifo to fix this issue.
-
-Signed-off-by: Ram Prakash Gupta <quic_rampraka@quicinc.com>
----
- drivers/mmc/host/sdhci-msm.c | 41 ++++++++++++++++++++++++++++++++++++
- 1 file changed, 41 insertions(+)
-
-diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
-index 9473039ccb13..b3643aec5444 100644
---- a/drivers/mmc/host/sdhci-msm.c
-+++ b/drivers/mmc/host/sdhci-msm.c
-@@ -158,6 +158,7 @@
- /* CQHCI vendor specific registers */
- #define CQHCI_VENDOR_CFG1	0xA00
- #define CQHCI_VENDOR_DIS_RST_ON_CQ_EN	(0x3 << 13)
-+#define RCLK_TOGGLE BIT(1)
- 
- struct sdhci_msm_offset {
- 	u32 core_hc_mode;
-@@ -303,6 +304,7 @@ struct sdhci_msm_host {
- 	u32 dll_config;
- 	u32 ddr_config;
- 	bool vqmmc_enabled;
-+	bool toggle_fifo_clk;
- };
- 
- static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host)
-@@ -1184,6 +1186,39 @@ static int sdhci_msm_restore_sdr_dll_config(struct sdhci_host *host)
- 	return ret;
- }
- 
-+/*
-+ * After MCLK ugating, toggle the FIFO write clock to get
-+ * the FIFO pointers and flags to valid state.
-+ */
-+static void sdhci_msm_toggle_fifo_write_clk(struct sdhci_host *host)
-+{
-+	u32 config;
-+	struct mmc_ios ios = host->mmc->ios;
-+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
-+	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
-+	const struct sdhci_msm_offset *msm_offset = msm_host->offset;
-+
-+	if ((msm_host->tuning_done || ios.enhanced_strobe) &&
-+		host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
-+		/*
-+		 * Select MCLK as DLL input clock.
-+		 */
-+		config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_3);
-+		config |= RCLK_TOGGLE;
-+		writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_3);
-+
-+		/* ensure above write as toggling same bit quickly */
-+		wmb();
-+		udelay(2);
-+
-+		/*
-+		 * Select RCLK as DLL input clock
-+		 */
-+		config &= ~RCLK_TOGGLE;
-+		writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_3);
-+	}
-+}
-+
- static void sdhci_msm_set_cdr(struct sdhci_host *host, bool enable)
- {
- 	const struct sdhci_msm_offset *msm_offset = sdhci_priv_msm_offset(host);
-@@ -2662,6 +2697,9 @@ static int sdhci_msm_probe(struct platform_device *pdev)
- 	if (core_major == 1 && core_minor >= 0x71)
- 		msm_host->uses_tassadar_dll = true;
- 
-+	if (core_major == 1 && core_minor >= 0x6B)
-+		msm_host->toggle_fifo_clk = true;
-+
- 	ret = sdhci_msm_register_vreg(msm_host);
- 	if (ret)
- 		goto clk_disable;
-@@ -2795,6 +2833,9 @@ static __maybe_unused int sdhci_msm_runtime_resume(struct device *dev)
- 				       msm_host->bulk_clks);
- 	if (ret)
- 		return ret;
-+
-+	if (msm_host->toggle_fifo_clk)
-+		sdhci_msm_toggle_fifo_write_clk(host);
- 	/*
- 	 * Whenever core-clock is gated dynamically, it's needed to
- 	 * restore the SDR DLL settings when the clock is ungated.
--- 
-2.34.1
-