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Merge branch 'master' of github.com:OpenELEC/OpenELEC.tv

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This commit is contained in:
Stephan Raue
2013-11-25 02:01:41 +01:00
parent 2756b8ee3c 28bbaa14c1
commit 2e3d49a50f
17 changed files with 1760 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

659
packages/multimedia/libva-driver-intel/patches.upstream/0001-render-add-support-for-brightness-contrast-hue-satur.patch Normal file
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File diff suppressed because it is too large Load Diff

276
packages/multimedia/libva-driver-intel/patches.upstream/0002-Increase-the-size-of-constant-buffer-for-PS-thread-t.patch Normal file
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@@ -0,0 +1,276 @@
From bf2bb5e0ccc8375800a9ed1bad956fd766641f1a Mon Sep 17 00:00:00 2001
From: Zhao Yakui <yakui.zhao@intel.com>
Date: Fri, 22 Nov 2013 13:39:34 +0800
Subject: [PATCH 2/5] Increase the size of constant buffer for PS thread to
pass more info
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
---
src/i965_render.c | 16 ++++-----
src/shaders/render/exa_wm.g4i | 52 ++++++++++++++-------------
src/shaders/render/exa_wm_src_affine.g4b | 12 +++----
src/shaders/render/exa_wm_src_affine.g4b.gen5 | 12 +++----
src/shaders/render/exa_wm_src_affine.g6a | 3 --
src/shaders/render/exa_wm_src_affine.g6b | 8 ++---
src/shaders/render/exa_wm_src_affine.g7a | 2 --
src/shaders/render/exa_wm_src_affine.g7b | 8 ++---
src/shaders/render/exa_wm_xy.g4b | 4 +--
src/shaders/render/exa_wm_xy.g4b.gen5 | 4 +--
10 files changed, 60 insertions(+), 61 deletions(-)
diff --git a/src/i965_render.c b/src/i965_render.c
index b4fd29b..0777ce0 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -55,7 +55,7 @@ static const uint32_t sf_kernel_static[][4] =
#include "shaders/render/exa_sf.g4b"
};
-#define PS_KERNEL_NUM_GRF 32
+#define PS_KERNEL_NUM_GRF 48
#define PS_MAX_THREADS 32
#define I965_GRF_BLOCKS(nreg) ((nreg + 15) / 16 - 1)
@@ -308,8 +308,8 @@ static struct i965_kernel render_kernels_gen7_haswell[] = {
#define URB_SF_ENTRIES 1
#define URB_SF_ENTRY_SIZE 2
-#define URB_CS_ENTRIES 1
-#define URB_CS_ENTRY_SIZE 1
+#define URB_CS_ENTRIES 4
+#define URB_CS_ENTRY_SIZE 4
static void
i965_render_vs_unit(VADriverContextP ctx)
@@ -445,8 +445,8 @@ i965_subpic_render_wm_unit(VADriverContextP ctx)
wm_state->thread2.scratch_space_base_pointer = 0;
wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
- wm_state->thread3.dispatch_grf_start_reg = 3; /* XXX */
- wm_state->thread3.const_urb_entry_read_length = 0;
+ wm_state->thread3.dispatch_grf_start_reg = 2; /* XXX */
+ wm_state->thread3.const_urb_entry_read_length = 4;
wm_state->thread3.const_urb_entry_read_offset = 0;
wm_state->thread3.urb_entry_read_length = 1; /* XXX */
wm_state->thread3.urb_entry_read_offset = 0; /* XXX */
@@ -510,7 +510,7 @@ i965_render_wm_unit(VADriverContextP ctx)
wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
wm_state->thread3.dispatch_grf_start_reg = 2; /* XXX */
- wm_state->thread3.const_urb_entry_read_length = 1;
+ wm_state->thread3.const_urb_entry_read_length = 4;
wm_state->thread3.const_urb_entry_read_offset = 0;
wm_state->thread3.urb_entry_read_length = 1; /* XXX */
wm_state->thread3.urb_entry_read_offset = 0; /* XXX */
@@ -2071,7 +2071,7 @@ gen6_emit_wm_state(VADriverContextP ctx, int kernel)
OUT_RELOC(batch,
render_state->curbe.bo,
I915_GEM_DOMAIN_INSTRUCTION, 0,
- 0);
+ (URB_CS_ENTRY_SIZE-1));
OUT_BATCH(batch, 0);
OUT_BATCH(batch, 0);
OUT_BATCH(batch, 0);
@@ -2837,7 +2837,7 @@ gen7_emit_wm_state(VADriverContextP ctx, int kernel)
BEGIN_BATCH(batch, 7);
OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_PS | (7 - 2));
- OUT_BATCH(batch, 1);
+ OUT_BATCH(batch, URB_CS_ENTRY_SIZE);
OUT_BATCH(batch, 0);
OUT_RELOC(batch,
render_state->curbe.bo,
diff --git a/src/shaders/render/exa_wm.g4i b/src/shaders/render/exa_wm.g4i
index dd47d51..e186d3a 100644
--- a/src/shaders/render/exa_wm.g4i
+++ b/src/shaders/render/exa_wm.g4i
@@ -1,5 +1,5 @@
/*
- * Copyright © 2006 Intel Corporation
+ * Copyright © 2006-2013 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -39,39 +39,43 @@ define(`screen_y0', `g1.4<0,1,0>F')
define(`interleaved_uv', `g2.0<0,1,0>UW')
/* Source transformation parameters */
-define(`src_du_dx', `g3.0<0,1,0>F')
-define(`src_du_dy', `g3.4<0,1,0>F')
-define(`src_uo', `g3.12<0,1,0>F')
-define(`src_dv_dx', `g3.16<0,1,0>F')
-define(`src_dv_dy', `g3.20<0,1,0>F')
-define(`src_vo', `g3.28<0,1,0>F')
-define(`src_dw_dx', `g4.0<0,1,0>F')
-define(`src_dw_dy', `g4.4<0,1,0>F')
-define(`src_wo', `g4.12<0,1,0>F')
-
-define(`mask_du_dx', `g5.0<0,1,0>F')
-define(`mask_du_dy', `g5.4<0,1,0>F')
-define(`mask_uo', `g5.12<0,1,0>F')
-define(`mask_dv_dx', `g5.16<0,1,0>F')
-define(`mask_dv_dy', `g5.20<0,1,0>F')
-define(`mask_vo', `g5.28<0,1,0>F')
-define(`mask_dw_dx', `g6.0<0,1,0>F')
-define(`mask_dw_dy', `g6.4<0,1,0>F')
-define(`mask_wo', `g6.12<0,1,0>F')
+define(`src_du_dx', `g6.0<0,1,0>F')
+define(`src_du_dy', `g6.4<0,1,0>F')
+define(`src_uo', `g6.12<0,1,0>F')
+define(`src_dv_dx', `g6.16<0,1,0>F')
+define(`src_dv_dy', `g6.20<0,1,0>F')
+define(`src_vo', `g6.28<0,1,0>F')
+define(`src_dw_dx', `g7.0<0,1,0>F')
+define(`src_dw_dy', `g7.4<0,1,0>F')
+define(`src_wo', `g7.12<0,1,0>F')
+
+define(`mask_du_dx', `g8.0<0,1,0>F')
+define(`mask_du_dy', `g8.4<0,1,0>F')
+define(`mask_uo', `g8.12<0,1,0>F')
+define(`mask_dv_dx', `g8.16<0,1,0>F')
+define(`mask_dv_dy', `g8.20<0,1,0>F')
+define(`mask_vo', `g8.28<0,1,0>F')
+define(`mask_dw_dx', `g9.0<0,1,0>F')
+define(`mask_dw_dy', `g9.4<0,1,0>F')
+define(`mask_wo', `g9.12<0,1,0>F')
+
+/* Attribute for snb+ */
+define(`a0_a_x',`g10.0<0,1,0>F')
+define(`a0_a_y',`g10.16<0,1,0>F')
/*
* Local variables. Pairs must be aligned on even reg boundry
*/
/* this holds the X dest coordinates */
-define(`dst_x', `g8')
+define(`dst_x', `g42')
define(`dst_x_0', `dst_x')
-define(`dst_x_1', `g9')
+define(`dst_x_1', `g43')
/* this holds the Y dest coordinates */
-define(`dst_y', `g10')
+define(`dst_y', `g44')
define(`dst_y_0', `dst_y')
-define(`dst_y_1', `g11')
+define(`dst_y_1', `g45')
/* When computing x * dn/dx, use this */
define(`temp_x', `g30')
diff --git a/src/shaders/render/exa_wm_src_affine.g4b b/src/shaders/render/exa_wm_src_affine.g4b
index d30da87..7507b72 100644
--- a/src/shaders/render/exa_wm_src_affine.g4b
+++ b/src/shaders/render/exa_wm_src_affine.g4b
@@ -1,8 +1,8 @@
- { 0x00802041, 0x23c077bd, 0x008d0100, 0x00000060 },
- { 0x00802041, 0x238077bd, 0x008d0140, 0x00000064 },
+ { 0x00802041, 0x23c077bd, 0x008d0540, 0x000000c0 },
+ { 0x00802041, 0x238077bd, 0x008d0580, 0x000000c4 },
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
- { 0x00802040, 0x204077be, 0x008d03c0, 0x0000006c },
- { 0x00802041, 0x23c077bd, 0x008d0100, 0x00000070 },
- { 0x00802041, 0x238077bd, 0x008d0140, 0x00000074 },
+ { 0x00802040, 0x204077be, 0x008d03c0, 0x000000cc },
+ { 0x00802041, 0x23c077bd, 0x008d0540, 0x000000d0 },
+ { 0x00802041, 0x238077bd, 0x008d0580, 0x000000d4 },
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
- { 0x00802040, 0x208077be, 0x008d03c0, 0x0000007c },
+ { 0x00802040, 0x208077be, 0x008d03c0, 0x000000dc },
diff --git a/src/shaders/render/exa_wm_src_affine.g4b.gen5 b/src/shaders/render/exa_wm_src_affine.g4b.gen5
index d30da87..7507b72 100644
--- a/src/shaders/render/exa_wm_src_affine.g4b.gen5
+++ b/src/shaders/render/exa_wm_src_affine.g4b.gen5
@@ -1,8 +1,8 @@
- { 0x00802041, 0x23c077bd, 0x008d0100, 0x00000060 },
- { 0x00802041, 0x238077bd, 0x008d0140, 0x00000064 },
+ { 0x00802041, 0x23c077bd, 0x008d0540, 0x000000c0 },
+ { 0x00802041, 0x238077bd, 0x008d0580, 0x000000c4 },
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
- { 0x00802040, 0x204077be, 0x008d03c0, 0x0000006c },
- { 0x00802041, 0x23c077bd, 0x008d0100, 0x00000070 },
- { 0x00802041, 0x238077bd, 0x008d0140, 0x00000074 },
+ { 0x00802040, 0x204077be, 0x008d03c0, 0x000000cc },
+ { 0x00802041, 0x23c077bd, 0x008d0540, 0x000000d0 },
+ { 0x00802041, 0x238077bd, 0x008d0580, 0x000000d4 },
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
- { 0x00802040, 0x208077be, 0x008d03c0, 0x0000007c },
+ { 0x00802040, 0x208077be, 0x008d03c0, 0x000000dc },
diff --git a/src/shaders/render/exa_wm_src_affine.g6a b/src/shaders/render/exa_wm_src_affine.g6a
index 568aef3..04358cb 100644
--- a/src/shaders/render/exa_wm_src_affine.g6a
+++ b/src/shaders/render/exa_wm_src_affine.g6a
@@ -35,9 +35,6 @@ define(`vh', `m5')
define(`bl', `g2.0<8,8,1>F')
define(`bh', `g4.0<8,8,1>F')
-define(`a0_a_x',`g7.0<0,1,0>F')
-define(`a0_a_y',`g7.16<0,1,0>F')
-
/* U */
pln (8) ul<1>F a0_a_x bl { align1 }; /* pixel 0-7 */
pln (8) uh<1>F a0_a_x bh { align1 }; /* pixel 8-15 */
diff --git a/src/shaders/render/exa_wm_src_affine.g6b b/src/shaders/render/exa_wm_src_affine.g6b
index 5d0ffcc..22c1d22 100644
--- a/src/shaders/render/exa_wm_src_affine.g6b
+++ b/src/shaders/render/exa_wm_src_affine.g6b
@@ -1,4 +1,4 @@
- { 0x0060005a, 0x204077be, 0x000000e0, 0x008d0040 },
- { 0x0060005a, 0x206077be, 0x000000e0, 0x008d0080 },
- { 0x0060005a, 0x208077be, 0x000000f0, 0x008d0040 },
- { 0x0060005a, 0x20a077be, 0x000000f0, 0x008d0080 },
+ { 0x0060005a, 0x204077be, 0x00000140, 0x008d0040 },
+ { 0x0060005a, 0x206077be, 0x00000140, 0x008d0080 },
+ { 0x0060005a, 0x208077be, 0x00000150, 0x008d0040 },
+ { 0x0060005a, 0x20a077be, 0x00000150, 0x008d0080 },
diff --git a/src/shaders/render/exa_wm_src_affine.g7a b/src/shaders/render/exa_wm_src_affine.g7a
index a786bc0..88e5ed5 100644
--- a/src/shaders/render/exa_wm_src_affine.g7a
+++ b/src/shaders/render/exa_wm_src_affine.g7a
@@ -35,8 +35,6 @@ define(`vh', `g69')
define(`bl', `g2.0<8,8,1>F')
define(`bh', `g4.0<8,8,1>F')
-define(`a0_a_x',`g7.0<0,1,0>F')
-define(`a0_a_y',`g7.16<0,1,0>F')
/* U */
pln (8) ul<1>F a0_a_x bl { align1 }; /* pixel 0-7 */
diff --git a/src/shaders/render/exa_wm_src_affine.g7b b/src/shaders/render/exa_wm_src_affine.g7b
index 5dbbf1b..a15b7b6 100644
--- a/src/shaders/render/exa_wm_src_affine.g7b
+++ b/src/shaders/render/exa_wm_src_affine.g7b
@@ -1,4 +1,4 @@
- { 0x0060005a, 0x284077bd, 0x000000e0, 0x008d0040 },
- { 0x0060005a, 0x286077bd, 0x000000e0, 0x008d0080 },
- { 0x0060005a, 0x288077bd, 0x000000f0, 0x008d0040 },
- { 0x0060005a, 0x28a077bd, 0x000000f0, 0x008d0080 },
+ { 0x0060005a, 0x284077bd, 0x00000140, 0x008d0040 },
+ { 0x0060005a, 0x286077bd, 0x00000140, 0x008d0080 },
+ { 0x0060005a, 0x288077bd, 0x00000150, 0x008d0040 },
+ { 0x0060005a, 0x28a077bd, 0x00000150, 0x008d0080 },
diff --git a/src/shaders/render/exa_wm_xy.g4b b/src/shaders/render/exa_wm_xy.g4b
index 327fc29..2b3b235 100644
--- a/src/shaders/render/exa_wm_xy.g4b
+++ b/src/shaders/render/exa_wm_xy.g4b
@@ -1,4 +1,4 @@
{ 0x00800040, 0x23c06d29, 0x00480028, 0x10101010 },
{ 0x00800040, 0x23806d29, 0x0048002a, 0x11001100 },
- { 0x00802040, 0x2100753d, 0x008d03c0, 0x00004020 },
- { 0x00802040, 0x2140753d, 0x008d0380, 0x00004024 },
+ { 0x00802040, 0x2540753d, 0x008d03c0, 0x00004020 },
+ { 0x00802040, 0x2580753d, 0x008d0380, 0x00004024 },
diff --git a/src/shaders/render/exa_wm_xy.g4b.gen5 b/src/shaders/render/exa_wm_xy.g4b.gen5
index 327fc29..2b3b235 100644
--- a/src/shaders/render/exa_wm_xy.g4b.gen5
+++ b/src/shaders/render/exa_wm_xy.g4b.gen5
@@ -1,4 +1,4 @@
{ 0x00800040, 0x23c06d29, 0x00480028, 0x10101010 },
{ 0x00800040, 0x23806d29, 0x0048002a, 0x11001100 },
- { 0x00802040, 0x2100753d, 0x008d03c0, 0x00004020 },
- { 0x00802040, 0x2140753d, 0x008d0380, 0x00004024 },
+ { 0x00802040, 0x2540753d, 0x008d03c0, 0x00004020 },
+ { 0x00802040, 0x2580753d, 0x008d0380, 0x00004024 },
--
1.8.3.2

629
packages/multimedia/libva-driver-intel/patches.upstream/0003-Constant-buffer-passes-YUV2RGB-CSC-matrix-instead-of.patch Normal file
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130
packages/multimedia/libva-driver-intel/patches.upstream/0004-Support-the-BT709-color-standard-for-conversion-from.patch Normal file
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@@ -0,0 +1,130 @@
From 9c5a739430029aece3b9e29bd3e3ae612e46c6f0 Mon Sep 17 00:00:00 2001
From: Zhao Yakui <yakui.zhao@intel.com>
Date: Fri, 22 Nov 2013 13:39:34 +0800
Subject: [PATCH 4/5] Support the BT709 color standard for conversion from YUV
to RGB
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
---
src/i965_output_dri.c | 7 +++++++
src/i965_render.c | 22 +++++++++++++++++-----
src/i965_render.h | 2 ++
3 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/src/i965_output_dri.c b/src/i965_output_dri.c
index de7be92..1467367 100644
--- a/src/i965_output_dri.c
+++ b/src/i965_output_dri.c
@@ -127,6 +127,7 @@ i965_put_surface_dri(
bool new_region = false;
uint32_t name;
int i, ret;
+ unsigned int color_flag = 0;
/* Currently don't support DRI1 */
if (!VA_CHECK_DRM_AUTH_TYPE(ctx, VA_DRM_AUTH_DRI2))
@@ -179,6 +180,12 @@ i965_put_surface_dri(
assert(ret == 0);
}
+ color_flag = flags & VA_SRC_COLOR_MASK;
+ if (color_flag == 0)
+ color_flag = VA_SRC_BT601;
+
+ pp_flag = color_flag;
+
if ((flags & VA_FILTER_SCALING_MASK) == VA_FILTER_SCALING_NL_ANAMORPHIC)
pp_flag |= I965_PP_FLAG_AVS;
diff --git a/src/i965_render.c b/src/i965_render.c
index 5b1a1a5..5be8a96 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -317,6 +317,12 @@ static float yuv_to_rgb_bt601[3][4] = {
{1.164, 2.017, 0, -0.50196,},
};
+static float yuv_to_rgb_bt709[3][4] = {
+{1.164, 0, 1.793, -0.06275,},
+{1.164, -0.213, -0.533, -0.50196,},
+{1.164, 2.112, 0, -0.50196,},
+};
+
static void
i965_render_vs_unit(VADriverContextP ctx)
{
@@ -1066,7 +1072,8 @@ i965_render_upload_vertex(
static void
i965_render_upload_constants(VADriverContextP ctx,
- struct object_surface *obj_surface)
+ struct object_surface *obj_surface,
+ unsigned int flags)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
struct i965_render_state *render_state = &i965->render_state;
@@ -1077,6 +1084,7 @@ i965_render_upload_constants(VADriverContextP ctx,
float hue = (float)i965->hue_attrib->value / 180 * PI;
float saturation = (float)i965->saturation_attrib->value / DEFAULT_SATURATION;
float *yuv_to_rgb;
+ unsigned int color_flag;
dri_bo_map(render_state->curbe.bo, 1);
assert(render_state->curbe.bo->virtual);
@@ -1107,8 +1115,12 @@ i965_render_upload_constants(VADriverContextP ctx,
*color_balance_base++ = cos(hue) * contrast * saturation;
*color_balance_base++ = sin(hue) * contrast * saturation;
+ color_flag = flags & VA_SRC_COLOR_MASK;
yuv_to_rgb = (float *)constant_buffer + 8;
- memcpy(yuv_to_rgb, yuv_to_rgb_bt601, sizeof(yuv_to_rgb_bt601));
+ if (color_flag == VA_SRC_BT709)
+ memcpy(yuv_to_rgb, yuv_to_rgb_bt709, sizeof(yuv_to_rgb_bt709));
+ else
+ memcpy(yuv_to_rgb, yuv_to_rgb_bt601, sizeof(yuv_to_rgb_bt601));
dri_bo_unmap(render_state->curbe.bo);
}
@@ -1155,7 +1167,7 @@ i965_surface_render_state_setup(
i965_render_cc_viewport(ctx);
i965_render_cc_unit(ctx);
i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect);
- i965_render_upload_constants(ctx, obj_surface);
+ i965_render_upload_constants(ctx, obj_surface, flags);
}
static void
@@ -1842,7 +1854,7 @@ gen6_render_setup_states(
gen6_render_color_calc_state(ctx);
gen6_render_blend_state(ctx);
gen6_render_depth_stencil_state(ctx);
- i965_render_upload_constants(ctx, obj_surface);
+ i965_render_upload_constants(ctx, obj_surface, flags);
i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect);
}
@@ -2436,7 +2448,7 @@ gen7_render_setup_states(
gen7_render_color_calc_state(ctx);
gen7_render_blend_state(ctx);
gen7_render_depth_stencil_state(ctx);
- i965_render_upload_constants(ctx, obj_surface);
+ i965_render_upload_constants(ctx, obj_surface, flags);
i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect);
}
diff --git a/src/i965_render.h b/src/i965_render.h
index f09b535..1960ace 100644
--- a/src/i965_render.h
+++ b/src/i965_render.h
@@ -33,6 +33,8 @@
#define NUM_RENDER_KERNEL 3
+#define VA_SRC_COLOR_MASK 0x000000f0
+
#include "i965_post_processing.h"
struct i965_kernel;
--
1.8.3.2

40
packages/multimedia/libva-driver-intel/patches.upstream/0005-Support-the-smpte240m-color-standard-for-conversion-.patch Normal file
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@@ -0,0 +1,40 @@
From a653c376d7650bf967a753cd4bda68bfeab5f4eb Mon Sep 17 00:00:00 2001
From: Zhao Yakui <yakui.zhao@intel.com>
Date: Fri, 22 Nov 2013 13:39:34 +0800
Subject: [PATCH 5/5] Support the smpte240m color standard for conversion from
YUV to RGB
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
---
src/i965_render.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/src/i965_render.c b/src/i965_render.c
index 5be8a96..92270cb 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -323,6 +323,12 @@ static float yuv_to_rgb_bt709[3][4] = {
{1.164, 2.112, 0, -0.50196,},
};
+static float yuv_to_rgb_smpte_240[3][4] = {
+{1.164, 0, 1.794, -0.06275,},
+{1.164, -0.258, -0.5425, -0.50196,},
+{1.164, 2.078, 0, -0.50196,},
+};
+
static void
i965_render_vs_unit(VADriverContextP ctx)
{
@@ -1119,6 +1125,8 @@ i965_render_upload_constants(VADriverContextP ctx,
yuv_to_rgb = (float *)constant_buffer + 8;
if (color_flag == VA_SRC_BT709)
memcpy(yuv_to_rgb, yuv_to_rgb_bt709, sizeof(yuv_to_rgb_bt709));
+ else if (color_flag == VA_SRC_SMPTE_240)
+ memcpy(yuv_to_rgb, yuv_to_rgb_smpte_240, sizeof(yuv_to_rgb_smpte_240));
else
memcpy(yuv_to_rgb, yuv_to_rgb_bt601, sizeof(yuv_to_rgb_bt601));
--
1.8.3.2

0
packages/multimedia/libva-driver-intel/patches.upstream/libva-driver-intel-fix-surface_empty.patch → packages/multimedia/libva-driver-intel/patches.upstream/0006-libva-driver-intel-fix-surface_empty.patch
View File

16
packages/sysutils/systemd/package.mk
View File

@@ -152,6 +152,22 @@ post_makeinstall_target() {
# remove debug-shell.service, we install our own
rm -rf $INSTALL/lib/systemd/system/debug-shell.service
# remove systemd-update-utmp. pointless
rm -rf $INSTALL/lib/systemd/systemd-update-utmp
rm -rf $INSTALL/lib/systemd/system/systemd-update-utmp-runlevel.service
rm -rf $INSTALL/lib/systemd/system/systemd-update-utmp.service
rm -rf $INSTALL/lib/systemd/system/sysinit.target.wants/systemd-update-utmp.service
# remove systemd-ask-password. pointless
rm -rf $INSTALL/lib/systemd/system/systemd-ask-password-wall.service
rm -rf $INSTALL/lib/systemd/system/systemd-ask-password-wall.path
rm -rf $INSTALL/lib/systemd/system/systemd-ask-password-console.path
rm -rf $INSTALL/lib/systemd/system/systemd-ask-password-console.service
rm -rf $INSTALL/bin/systemd-ask-password
rm -rf $INSTALL/bin/systemd-tty-ask-password-agent
rm -rf $INSTALL/lib/systemd/system/sysinit.target.wants/systemd-ask-password-console.path
rm -rf $INSTALL/lib/systemd/system/multi-user.target.wants/systemd-ask-password-wall.path
# remove some generators we never use
rm -rf $INSTALL/lib/systemd/system-generators/systemd-fstab-generator

2
packages/sysutils/timezone-data/system.d/tz-data-monitor.path
View File

@@ -3,7 +3,7 @@ Description=Timezone data monitor
After=local-fs.target
[Path]
PathModified=/storage/.xbmc/userdata/guisettings.xml
PathChanged=/storage/.xbmc/userdata/guisettings.xml
[Install]
WantedBy=multi-user.target

1
packages/sysutils/timezone-data/system.d/tz-data-monitor.service
View File

@@ -4,6 +4,7 @@ Description=Timezone data monitor
[Service]
Type=oneshot
ExecStart=/bin/systemctl restart tz-data.service
StartLimitInterval=0
[Install]
WantedBy=multi-user.target

1
packages/sysutils/timezone-data/system.d/tz-data.service
View File

@@ -8,6 +8,7 @@ ConditionPathExists=/storage/.xbmc/userdata/guisettings.xml
Type=oneshot
ExecStart=/usr/lib/openelec/tzdata-setup
RemainAfterExit=yes
StartLimitInterval=0
[Install]
WantedBy=xbmc.service

4
projects/ARCTIC_MC/linux/linux.x86_64.conf
View File

@@ -3333,9 +3333,7 @@ CONFIG_RTS5139=m
# CONFIG_VT6655 is not set
CONFIG_VT6656=m
# CONFIG_DX_SEP is not set
CONFIG_ZSMALLOC=y
CONFIG_ZRAM=y
# CONFIG_ZRAM_DEBUG is not set
# CONFIG_ZSMALLOC is not set
# CONFIG_FB_SM7XX is not set
# CONFIG_CRYSTALHD is not set
# CONFIG_FB_XGI is not set

4
projects/ATV/linux/linux.i386.conf
View File

@@ -2852,9 +2852,7 @@ CONFIG_RTS5139=m
# CONFIG_VT6655 is not set
# CONFIG_VT6656 is not set
# CONFIG_DX_SEP is not set
CONFIG_ZSMALLOC=y
CONFIG_ZRAM=y
# CONFIG_ZRAM_DEBUG is not set
# CONFIG_ZSMALLOC is not set
# CONFIG_FB_SM7XX is not set
# CONFIG_CRYSTALHD is not set
# CONFIG_FB_XGI is not set

4
projects/Generic/linux/linux.i386.conf
View File

@@ -3363,9 +3363,7 @@ CONFIG_RTS5139=m
# CONFIG_VT6655 is not set
CONFIG_VT6656=m
# CONFIG_DX_SEP is not set
CONFIG_ZSMALLOC=y
CONFIG_ZRAM=y
# CONFIG_ZRAM_DEBUG is not set
# CONFIG_ZSMALLOC is not set
# CONFIG_FB_SM7XX is not set
# CONFIG_CRYSTALHD is not set
# CONFIG_FB_XGI is not set

4
projects/Generic/linux/linux.x86_64.conf
View File

@@ -3332,9 +3332,7 @@ CONFIG_RTS5139=m
# CONFIG_VT6655 is not set
CONFIG_VT6656=m
# CONFIG_DX_SEP is not set
CONFIG_ZSMALLOC=y
CONFIG_ZRAM=y
# CONFIG_ZRAM_DEBUG is not set
# CONFIG_ZSMALLOC is not set
# CONFIG_FB_SM7XX is not set
# CONFIG_CRYSTALHD is not set
# CONFIG_FB_XGI is not set

4
projects/RPi/linux/linux.arm.conf
View File

@@ -2378,9 +2378,7 @@ CONFIG_RTS5139=m
# CONFIG_TRANZPORT is not set
# CONFIG_USB_SERIAL_QUATECH2 is not set
CONFIG_VT6656=m
CONFIG_ZSMALLOC=y
CONFIG_ZRAM=y
# CONFIG_ZRAM_DEBUG is not set
# CONFIG_ZSMALLOC is not set
# CONFIG_USB_ENESTORAGE is not set
# CONFIG_BCM_WIMAX is not set
# CONFIG_FT1000 is not set

4
projects/Virtual/linux/linux.i386.conf
View File

@@ -3363,9 +3363,7 @@ CONFIG_RTS5139=m
# CONFIG_VT6655 is not set
CONFIG_VT6656=m
# CONFIG_DX_SEP is not set
CONFIG_ZSMALLOC=y
CONFIG_ZRAM=y
# CONFIG_ZRAM_DEBUG is not set
# CONFIG_ZSMALLOC is not set
# CONFIG_FB_SM7XX is not set
# CONFIG_CRYSTALHD is not set
# CONFIG_FB_XGI is not set

4
projects/Virtual/linux/linux.x86_64.conf
View File

@@ -3332,9 +3332,7 @@ CONFIG_RTS5139=m
# CONFIG_VT6655 is not set
CONFIG_VT6656=m
# CONFIG_DX_SEP is not set
CONFIG_ZSMALLOC=y
CONFIG_ZRAM=y
# CONFIG_ZRAM_DEBUG is not set
# CONFIG_ZSMALLOC is not set
# CONFIG_FB_SM7XX is not set
# CONFIG_CRYSTALHD is not set
# CONFIG_FB_XGI is not set