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Merge pull request #2104 from loki666/sm8650

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linux/sm8650: patches
This commit is contained in:
Philippe Simons
2025-12-05 22:04:15 +01:00
committed by GitHub
parent 189cfe485f f0e1521e90
commit 13fa2b29a3
3 changed files with 347 additions and 5 deletions
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6
projects/ROCKNIX/devices/SM8650/patches/linux/0001-add-ayaneo-pocket-s2-dts.patch
View File

@@ -3,7 +3,7 @@ new file mode 100644
index 000000000000..681ded735fe4
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-ps2.dts
@@ -0,0 +1,1734 @@
@@ -0,0 +1,1730 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023, Linaro Limited
@@ -722,8 +722,6 @@ index 000000000000..681ded735fe4
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vreg_l17b_2p5: ldo17 {
@@ -812,8 +810,6 @@ index 000000000000..681ded735fe4
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+

89
projects/ROCKNIX/devices/SM8650/patches/linux/v4_20251202_charan_kalla_iommu_arm_smmu_add_actlr_settings_for_mdss_on_qualcomm_platforms.patch Normal file
View File

@@ -0,0 +1,89 @@
From git@z Thu Jan 1 00:00:00 1970
Subject: [PATCH v4] iommu/arm-smmu: add actlr settings for mdss on Qualcomm
platforms
From: Charan Teja Kalla <charan.kalla@oss.qualcomm.com>
Date: Tue, 02 Dec 2025 18:24:47 +0530
Message-Id: <20251202125447.2102658-1-charan.kalla@oss.qualcomm.com>
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 7bit
Add ACTLR settings for missing MDSS devices on Qualcomm platforms.
These are QoS settings and are specific to per SoC thus different
settings, eg: some have shallow prefetch while others have no
prefetch.
Aswell, this prefetch feature is not implemented for all the
platforms, capturing to those are implemented to the best of my
knowledge.
Signed-off-by: Charan Teja Kalla <charan.kalla@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
Changes from V3:
1) Add actlr setting for missing sc8180x & sm6115.
2) Improved commit message.
https://lore.kernel.org/all/20251124171030.323989-1-charan.kalla@oss.qualcomm.com/
Changes from V2:
1) Add actlr settings for all the mdss devices on Qualcomm platforms.
2) Improved the commit message that explain why different ACTLR
settings
https://lore.kernel.org/lkml/20251118171822.3539062-1-charan.kalla@oss.qualcomm.com/#t
Changes from V1:
1) Added actlr setting only for MDSS and dropped for fastrpc. --
konrad
2) ACTLR table is updated per alphanumeric order -- konrad
https://lore.kernel.org/all/20251105075307.1658329-1-charan.kalla@oss.qualcomm.com/
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 26 ++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index c21a401c71eb..149da53091de 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -41,12 +41,38 @@ static const struct of_device_id qcom_smmu_actlr_client_of_match[] = {
.data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) },
{ .compatible = "qcom,fastrpc",
.data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) },
+ { .compatible = "qcom,qcm2290-mdss",
+ .data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) },
{ .compatible = "qcom,sc7280-mdss",
.data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) },
{ .compatible = "qcom,sc7280-venus",
.data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) },
+ { .compatible = "qcom,sc8180x-mdss",
+ .data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) },
+ { .compatible = "qcom,sc8280xp-mdss",
+ .data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) },
+ { .compatible = "qcom,sm6115-mdss",
+ .data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) },
+ { .compatible = "qcom,sm6125-mdss",
+ .data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) },
+ { .compatible = "qcom,sm6350-mdss",
+ .data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) },
+ { .compatible = "qcom,sm8150-mdss",
+ .data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) },
+ { .compatible = "qcom,sm8250-mdss",
+ .data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) },
+ { .compatible = "qcom,sm8350-mdss",
+ .data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) },
+ { .compatible = "qcom,sm8450-mdss",
+ .data = (const void *) (PREFETCH_DEFAULT | CMTLB) },
{ .compatible = "qcom,sm8550-mdss",
.data = (const void *) (PREFETCH_DEFAULT | CMTLB) },
+ { .compatible = "qcom,sm8650-mdss",
+ .data = (const void *) (PREFETCH_DEFAULT | CMTLB) },
+ { .compatible = "qcom,sm8750-mdss",
+ .data = (const void *) (PREFETCH_DEFAULT | CMTLB) },
+ { .compatible = "qcom,x1e80100-mdss",
+ .data = (const void *) (PREFETCH_DEFAULT | CMTLB) },
{ }
};
--
2.34.1

257
projects/ROCKNIX/devices/SM8650/patches/linux/v5_20251120_quic_utiwari_crypto_qce_add_runtime_pm_and_interconnect_bandwidth_scaling_support.patch Normal file
View File

@@ -0,0 +1,257 @@
From git@z Thu Jan 1 00:00:00 1970
Subject: [PATCH v5] crypto: qce - Add runtime PM and interconnect bandwidth
scaling support
From: Udit Tiwari <quic_utiwari@quicinc.com>
Date: Thu, 20 Nov 2025 11:54:43 +0530
Message-Id: <20251120062443.2016084-1-quic_utiwari@quicinc.com>
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 7bit
The Qualcomm Crypto Engine (QCE) driver currently lacks support for
runtime power management (PM) and interconnect bandwidth control.
As a result, the hardware remains fully powered and clocks stay
enabled even when the device is idle. Additionally, static
interconnect bandwidth votes are held indefinitely, preventing the
system from reclaiming unused bandwidth.
Address this by enabling runtime PM and dynamic interconnect
bandwidth scaling to allow the system to suspend the device when idle
and scale interconnect usage based on actual demand. Improve overall
system efficiency by reducing power usage and optimizing interconnect
resource allocation.
Make the following changes as part of this integration:
- Add support for pm_runtime APIs to manage device power state
transitions.
- Implement runtime_suspend() and runtime_resume() callbacks to gate
clocks and vote for interconnect bandwidth only when needed.
- Replace devm_clk_get_optional_enabled() with devm_pm_clk_create() +
pm_clk_add() and let the PM core manage device clocks during runtime
PM and system sleep.
- Register dev_pm_ops with the platform driver to hook into the PM
framework.
Tested:
- Verify that ICC votes drop to zero after probe and upon request
completion.
- Confirm that runtime PM usage count increments during active
requests and decrements afterward.
- Observe that the device correctly enters the suspended state when
idle.
Signed-off-by: Udit Tiwari <quic_utiwari@quicinc.com>
---
Changes in v5:
- Drop Reported-by and Closes tags for kernel test robot W=1 warnings, as
the issue was fixed within the same patch series.
- Fix a minor comment indentation/style issue.
Changes in v4:
- Annotate runtime PM callbacks with __maybe_unused to silence W=1 warnings.
- Add Reported-by and Closes tags for kernel test robot warning.
Changes in v3:
- Switch from manual clock management to PM clock helpers
(devm_pm_clk_create() + pm_clk_add()); no direct clk_* enable/disable
in runtime callbacks.
- Replace pm_runtime_get_sync() with pm_runtime_resume_and_get(); remove
pm_runtime_put_noidle() on error.
- Define PM ops using helper macros and reuse runtime callbacks for system
sleep via pm_runtime_force_suspend()/pm_runtime_force_resume().
- Link to v2: https://lore.kernel.org/lkml/20250826110917.3383061-1-quic_utiwari@quicinc.com/
Changes in v2:
- Extend suspend/resume support to include runtime PM and ICC scaling.
- Register dev_pm_ops and implement runtime_suspend/resume callbacks.
- Link to v1: https://lore.kernel.org/lkml/20250606105808.2119280-1-quic_utiwari@quicinc.com/
---
drivers/crypto/qce/core.c | 103 +++++++++++++++++++++++++++++++-------
1 file changed, 86 insertions(+), 17 deletions(-)
diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index b966f3365b7d..2f07cc479998 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -12,6 +12,9 @@
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/pm_runtime.h>
+#include <linux/pm_clock.h>
#include <linux/types.h>
#include <crypto/algapi.h>
#include <crypto/internal/hash.h>
@@ -90,13 +93,17 @@ static int qce_handle_queue(struct qce_device *qce,
struct crypto_async_request *async_req, *backlog;
int ret = 0, err;
+ ret = pm_runtime_resume_and_get(qce->dev);
+ if (ret < 0)
+ return ret;
+
scoped_guard(mutex, &qce->lock) {
if (req)
ret = crypto_enqueue_request(&qce->queue, req);
/* busy, do not dequeue request */
if (qce->req)
- return ret;
+ goto qce_suspend;
backlog = crypto_get_backlog(&qce->queue);
async_req = crypto_dequeue_request(&qce->queue);
@@ -105,7 +112,7 @@ static int qce_handle_queue(struct qce_device *qce,
}
if (!async_req)
- return ret;
+ goto qce_suspend;
if (backlog) {
scoped_guard(mutex, &qce->lock)
@@ -118,6 +125,8 @@ static int qce_handle_queue(struct qce_device *qce,
schedule_work(&qce->done_work);
}
+qce_suspend:
+ pm_runtime_put_autosuspend(qce->dev);
return ret;
}
@@ -207,37 +216,47 @@ static int qce_crypto_probe(struct platform_device *pdev)
if (ret < 0)
return ret;
- qce->core = devm_clk_get_optional_enabled(qce->dev, "core");
- if (IS_ERR(qce->core))
- return PTR_ERR(qce->core);
+ /* PM clock helpers: register device clocks */
+ ret = devm_pm_clk_create(dev);
+ if (ret)
+ return ret;
- qce->iface = devm_clk_get_optional_enabled(qce->dev, "iface");
- if (IS_ERR(qce->iface))
- return PTR_ERR(qce->iface);
+ ret = pm_clk_add(dev, "core");
+ if (ret)
+ return ret;
- qce->bus = devm_clk_get_optional_enabled(qce->dev, "bus");
- if (IS_ERR(qce->bus))
- return PTR_ERR(qce->bus);
+ ret = pm_clk_add(dev, "iface");
+ if (ret)
+ return ret;
- qce->mem_path = devm_of_icc_get(qce->dev, "memory");
+ ret = pm_clk_add(dev, "bus");
+ if (ret)
+ return ret;
+
+ qce->mem_path = devm_of_icc_get(dev, "memory");
if (IS_ERR(qce->mem_path))
return PTR_ERR(qce->mem_path);
- ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH);
+ /* Enable runtime PM after clocks and ICC are acquired */
+ ret = devm_pm_runtime_enable(dev);
if (ret)
return ret;
- ret = devm_qce_dma_request(qce->dev, &qce->dma);
+ ret = pm_runtime_resume_and_get(dev);
if (ret)
return ret;
+ ret = devm_qce_dma_request(qce->dev, &qce->dma);
+ if (ret)
+ goto err_pm;
+
ret = qce_check_version(qce);
if (ret)
- return ret;
+ goto err_pm;
ret = devm_mutex_init(qce->dev, &qce->lock);
if (ret)
- return ret;
+ goto err_pm;
INIT_WORK(&qce->done_work, qce_req_done_work);
crypto_init_queue(&qce->queue, QCE_QUEUE_LENGTH);
@@ -245,9 +264,58 @@ static int qce_crypto_probe(struct platform_device *pdev)
qce->async_req_enqueue = qce_async_request_enqueue;
qce->async_req_done = qce_async_request_done;
- return devm_qce_register_algs(qce);
+ ret = devm_qce_register_algs(qce);
+ if (ret)
+ goto err_pm;
+
+ /* Configure autosuspend after successful init */
+ pm_runtime_set_autosuspend_delay(dev, 100);
+ pm_runtime_use_autosuspend(dev);
+ pm_runtime_mark_last_busy(dev);
+ pm_runtime_put_autosuspend(dev);
+
+ return 0;
+
+err_pm:
+ pm_runtime_put(dev);
+
+ return ret;
+}
+
+static int __maybe_unused qce_runtime_suspend(struct device *dev)
+{
+ struct qce_device *qce = dev_get_drvdata(dev);
+
+ icc_disable(qce->mem_path);
+
+ return 0;
+}
+
+static int __maybe_unused qce_runtime_resume(struct device *dev)
+{
+ struct qce_device *qce = dev_get_drvdata(dev);
+ int ret = 0;
+
+ ret = icc_enable(qce->mem_path);
+ if (ret)
+ return ret;
+
+ ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH);
+ if (ret)
+ goto err_icc;
+
+ return 0;
+
+err_icc:
+ icc_disable(qce->mem_path);
+ return ret;
}
+static const struct dev_pm_ops qce_crypto_pm_ops = {
+ SET_RUNTIME_PM_OPS(qce_runtime_suspend, qce_runtime_resume, NULL)
+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
+};
+
static const struct of_device_id qce_crypto_of_match[] = {
{ .compatible = "qcom,crypto-v5.1", },
{ .compatible = "qcom,crypto-v5.4", },
@@ -261,6 +329,7 @@ static struct platform_driver qce_crypto_driver = {
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = qce_crypto_of_match,
+ .pm = &qce_crypto_pm_ops,
},
};
module_platform_driver(qce_crypto_driver);
--
2.34.1