Xing Zheng 3e1531dbc3 clk: rockchip: fix the incorrect pclk_edp div width for RK3399
The range of the  pclk_edp_div_con is [13:8] and 6 bits, not 5.

Reported-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Tested-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-18 11:23:36 +01:00
2016-12-25 17:21:22 +01:00
2016-12-26 20:29:25 -08:00
2016-12-26 17:30:24 -08:00
2016-12-25 17:21:22 +01:00
2016-05-23 17:04:14 -07:00
2017-01-01 14:31:53 -08:00

Linux kernel
============

This file was moved to Documentation/admin-guide/README.rst

Please notice that there are several guides for kernel developers and users.
These guides can be rendered in a number of formats, like HTML and PDF.

In order to build the documentation, use ``make htmldocs`` or
``make pdfdocs``.

There are various text files in the Documentation/ subdirectory,
several of them using the Restructured Text markup notation.
See Documentation/00-INDEX for a list of what is contained in each file.

Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.
S
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