ff1930c6bd
MIPS,clk: migrate JZ4740 to common clock framework
...
Migrate the JZ4740 & the qi_lb60 board to use common clock framework
via the new Ingenic SoC CGU driver. Note that the JZ4740-specific
debugfs code is removed since common clock framework provides its own
debug capabilities.
Signed-off-by: Paul Burton <paul.burton@imgtec.com >
Co-authored-by: Paul Cercueil <paul@crapouillou.net >
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk >
Cc: Kumar Gala <galak@codeaurora.org >
Cc: Lars-Peter Clausen <lars@metafoo.de >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Mike Turquette <mturquette@linaro.org >
Cc: Pawel Moll <pawel.moll@arm.com >
Cc: Rob Herring <robh+dt@kernel.org >
Cc: Stephen Boyd <sboyd@codeaurora.org >
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Fabian Frederick <fabf@skynet.be >
Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com >
Cc: Linus Walleij <linus.walleij@linaro.org >
Cc: Stephen Warren <swarren@wwwdotorg.org >
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com >
Patchwork: https://patchwork.linux-mips.org/patch/10151/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:53:15 +02:00
b066303fb3
clk: ingenic: add driver for Ingenic SoC CGU clocks
...
This driver supports the CGU clocks for Ingenic SoCs. It is generic
enough to be usable across at least the JZ4740 to the JZ4780, and will
be made use of on such devices in subsequent commits. This patch by
itself only adds the SoC-agnostic infrastructure that forms the bulk of
the CGU driver for the aforementioned further commits to make use of.
Signed-off-by: Paul Burton <paul.burton@imgtec.com >
Co-authored-by: Paul Cercueil <paul@crapouillou.net >
Cc: Lars-Peter Clausen <lars@metafoo.de >
Cc: Mike Turquette <mturquette@linaro.org >
Cc: Stephen Boyd <sboyd@codeaurora.org >
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10150/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:53:15 +02:00
fe4ef45b5b
DEVICETREE: Add Ingenic CGU binding documentation
...
Document the devicetree binding for Ingenic SoC CGUs, and add headers
defining the clock specifiers for clocks provided by the JZ4740 & JZ4780
CGU blocks.
Signed-off-by: Paul Burton <paul.burton@imgtec.com >
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk >
Cc: Kumar Gala <galak@codeaurora.org >
Cc: Lars-Peter Clausen <lars@metafoo.de >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Mike Turquette <mturquette@linaro.org >
Cc: Pawel Moll <pawel.moll@arm.com >
Cc: Rob Herring <robh+dt@kernel.org >
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10152/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:53:13 +02:00
e06b86a33a
MIPS: JZ4740: replace use of jz4740_clock_bdata
...
Replace uses of the jz4740_clock_bdata struct with calls to clk_get_rate
for the appropriate clock. This is in preparation for migrating the
clocks towards common clock framework & devicetree.
Signed-off-by: Paul Burton <paul.burton@imgtec.com >
Cc: Lars-Peter Clausen <lars@metafoo.de >
Cc: linux-mips@linux-mips.org
Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com >
Cc: linux-kernel@vger.kernel.org
Cc: Apelete Seketeli <apelete@seketeli.net >
Patchwork: https://patchwork.linux-mips.org/patch/10149/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:53:12 +02:00
1f4b840983
MIPS: JZ4740: Call jz4740_clock_init earlier
...
Call jz4740_clock_init before any uses of jz4740_clock_bdata occur. This
is in preparation for replacing uses of that struct with calls to
clk_get_rate, which will allow the clocks to be migrated towards common
clock framework & devicetree.
Signed-off-by: Paul Burton <paul.burton@imgtec.com >
Cc: Lars-Peter Clausen <lars@metafoo.de >
Cc: linux-mips@linux-mips.org
Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com >
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10148/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:53:11 +02:00
44e08e7099
MIPS/IRQCHIP: Move Ingenic SoC intc driver to drivers/irqchip
...
Move the driver for Ingenic SoC interrupt controllers into
drivers/irqchip where it belongs.
Signed-off-by: Paul Burton <paul.burton@imgtec.com >
Cc: Lars-Peter Clausen <lars@metafoo.de >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: Jason Cooper <jason@lakedaemon.net >
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com >
Patchwork: https://patchwork.linux-mips.org/patch/10147/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:53:10 +02:00
24ccfa06b7
MIPS: JZ4740: support newer SoC interrupt controllers
...
Allow the interrupt controllers of the JZ4770, JZ4775 & JZ4780 SoCs to
be probed via devicetree, supporting the 64 interrupts they provide.
Signed-off-by: Paul Burton <paul.burton@imgtec.com >
Cc: Lars-Peter Clausen <lars@metafoo.de >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: Jason Cooper <jason@lakedaemon.net >
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com >
Patchwork: https://patchwork.linux-mips.org/patch/10155/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:53:07 +02:00
2da018849f
MIPS: JZ4740: Avoid JZ4740-specific naming
...
Rename the functions including jz4740 in their names to be more generic
in preparation for supporting further SoCs, and for moving this
interrupt controller code to drivers/irqchip.
Signed-off-by: Paul Burton <paul.burton@imgtec.com >
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com >
Cc: Lars-Peter Clausen <lars@metafoo.de >
Patchwork: https://patchwork.linux-mips.org/patch/10146/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:53:06 +02:00
3aa94590e7
MIPS: JZ4740: read intc base address from DT
...
Read the base address of the SoC interrupt controller from the device
tree rather than relying upon the JZ4740_INTC_BASE_ADDR macro, in order
to remove the dependency on the asm/mach-jz4740/base.h header.
Signed-off-by: Paul Burton <paul.burton@imgtec.com >
Cc: Lars-Peter Clausen <lars@metafoo.de >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: Jason Cooper <jason@lakedaemon.net >
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com >
Patchwork: https://patchwork.linux-mips.org/patch/10145/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:53:05 +02:00
ad68f8d3c2
MIPS: JZ4740: define IRQ numbers based on number of intc IRQs
...
For interrupts numbered after those of the interrupt controller, define
their numbers based upon the number of interrupts provided by the SoC
interrupt controller. This is in preparation for supporting newer
Ingenic SoCs which provide more interrupts.
Signed-off-by: Paul Burton <paul.burton@imgtec.com >
Cc: Lars-Peter Clausen <lars@metafoo.de >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: Jason Cooper <jason@lakedaemon.net >
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10143/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:53:04 +02:00
943d69c6c2
MIPS: JZ4740: support >32 interrupts
...
On newer Ingenic SoCs the interrupt controller supports more than 32
interrupts, which it does by duplicating the registers at intervals
of 0x20 bytes within its address space. Add support for an arbitrary
number of interrupts using multiple generic chips, and provide the
number of chips to register from the interrupt controller probe
function.
Signed-off-by: Paul Burton <paul.burton@imgtec.com >
Cc: Lars-Peter Clausen <lars@metafoo.de >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: Jason Cooper <jason@lakedaemon.net >
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com >
Patchwork: https://patchwork.linux-mips.org/patch/10141/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:53:03 +02:00
fe778ece8e
MIPS: JZ4740: Remove jz_intc_base global
...
Avoid the need for the global variable jz_intc_base by introducing a
struct ingenic_intc_data and passing it around as the IRQ handler data.
Signed-off-by: Paul Burton <paul.burton@imgtec.com >
Cc: Lars-Peter Clausen <lars@metafoo.de >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: Jason Cooper <jason@lakedaemon.net >
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com >
Patchwork: https://patchwork.linux-mips.org/patch/10144/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:53:02 +02:00
2aabd281d6
MIPS: JZ4740: drop intc debugfs code
...
The debugfs code becomes a nuisance when attempting to avoid globals,
since the interrupt controller probe function run too early for it to be
safe to create the debugfs files. Drop it.
Signed-off-by: Paul Burton <paul.burton@imgtec.com >
Cc: Lars-Peter Clausen <lars@metafoo.de >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: Jason Cooper <jason@lakedaemon.net >
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com >
Patchwork: https://patchwork.linux-mips.org/patch/10139/
Acked-by: Lars-Peter Clausen <lars@metafoo.de >
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:53:02 +02:00
638c885185
MIPS: JZ4740: register an irq_domain for the interrupt controller
...
When probing the interrupt controller, register an IRQ domain such
that the interrupts can be translated by devicetree code & thus used
from devicetree.
Signed-off-by: Paul Burton <paul.burton@imgtec.com >
Cc: Lars-Peter Clausen <lars@metafoo.de >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: Jason Cooper <jason@lakedaemon.net >
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com >
Patchwork: https://patchwork.linux-mips.org/patch/10140/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:53:00 +02:00
69ce4b2288
MIPS: JZ4740: parse SoC interrupt controller parent IRQ from DT
...
Rather than hardcoding the IRQ number used to cascade interrupts from
the SoC interrupt controller to the CPU interrupt controller, read that
IRQ number from the DT describing the system.
Signed-off-by: Paul Burton <paul.burton@imgtec.com >
Cc: Lars-Peter Clausen <lars@metafoo.de >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: Jason Cooper <jason@lakedaemon.net >
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com >
Patchwork: https://patchwork.linux-mips.org/patch/10137/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:52:59 +02:00
adbdce77cc
MIPS: JZ4740: probe interrupt controller via DT
...
Declare the JZ4740 interrupt controller for probe via DT using the
standard irqchip_init function, and make use of that function to probe
the controller by adding the appropriate node to the JZ4740 dtsi.
Signed-off-by: Paul Burton <paul.burton@imgtec.com >
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk >
Cc: Jason Cooper <jason@lakedaemon.net >
Cc: Kumar Gala <galak@codeaurora.org >
Cc: Lars-Peter Clausen <lars@metafoo.de >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Pawel Moll <pawel.moll@arm.com >
Cc: Rob Herring <robh+dt@kernel.org >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com >
Patchwork: https://patchwork.linux-mips.org/patch/10135/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:52:58 +02:00
5f408ebfd2
devicetree: document Ingenic SoC interrupt controller binding
...
Add binding documentation for Ingenic SoC interrupt controllers.
Signed-off-by: Paul Burton <paul.burton@imgtec.com >
Acked-by: Rob Herring <robh@kernel.org >
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk >
Cc: Jason Cooper <jason@lakedaemon.net >
Cc: Kumar Gala <galak@codeaurora.org >
Cc: Lars-Peter Clausen <lars@metafoo.de >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Pawel Moll <pawel.moll@arm.com >
Cc: Thomas Gleixner <tglx@linutronix.de >
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10134/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:52:56 +02:00
0e81db8f5b
MIPS: JZ4740: Move arch_init_irq out of arch/mips/jz4740/irq.c
...
In preparation for moving the JZ4740 interrupt controller driver to
drivers/irqchip, move arch_init_irq into setup.c such that everything
remaining in irq.c is related to said JZ4740 interrupt controller.
Signed-off-by: Paul Burton <paul.burton@imgtec.com >
Cc: Lars-Peter Clausen <lars@metafoo.de >
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com >
Patchwork: https://patchwork.linux-mips.org/patch/10136/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:52:56 +02:00
2974a35657
MIPS: JZ4740: use generic plat_irq_dispatch
...
Make use of the generic plat_irq_dispatch function introduced by commit
85f7cdacbbpaul.burton@imgtec.com >
Cc: Lars-Peter Clausen <lars@metafoo.de >
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com >
Patchwork: https://patchwork.linux-mips.org/patch/10138/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:52:55 +02:00
8e8261eb6a
MIPS: JZ4740: probe CPU interrupt controller via DT
...
Use the generic irqchip_init function to probe irqchip drivers using DT,
and add the appropriate node to the JZ4740 devicetree in place of the
call to mips_cpu_irq_init.
Signed-off-by: Paul Burton <paul.burton@imgtec.com >
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk >
Cc: Kumar Gala <galak@codeaurora.org >
Cc: Lars-Peter Clausen <lars@metafoo.de >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Pawel Moll <pawel.moll@arm.com >
Cc: Rob Herring <robh+dt@kernel.org >
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com >
Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com >
Patchwork: https://patchwork.linux-mips.org/patch/10166/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:52:54 +02:00
892b8cf06d
IRQCHIP: irq_cpu: declare irqchip table entry
...
Allow the MIPS CPU interrupt controller to be probed from DT using the
generic __irqchip_of_table for platforms which use irqchip_init. This
will avoid such platforms needing to duplicate the compatible string &
init function pointer.
[ralf@linux-mips.org: Resolved conflict due the preceeding commit that
moves irq-cpu.c.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: linux-kernel@vger.kernel.org
Cc: Felix Fietkau <nbd@openwrt.org>
Patchwork: https://patchwork.linux-mips.org/patch/10131/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:52:52 +02:00
67e38cf293
MIPS/IRQCHIP: Move irq_chip from arch/mips to drivers/irqchip.
...
While at it, rename it because in drivers/irqchip no longer every CPU is
a MIPS.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:52:50 +02:00
ffb1843d05
MIPS: JZ4740: require & include DT
...
Require a DT for JZ4740 based systems, and add a stub one for the
qi_lb60 (Ben NanoNote) board. Devices will be migrated to being probed
via this DT over time.
Signed-off-by: Paul Burton <paul.burton@imgtec.com >
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk >
Cc: Kumar Gala <galak@codeaurora.org >
Cc: Lars-Peter Clausen <lars@metafoo.de >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Pawel Moll <pawel.moll@arm.com >
Cc: Rob Herring <robh+dt@kernel.org >
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Andrew Bresticker <abrestic@chromium.org >
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10132/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:52:49 +02:00
252617a4ab
MIPS: ingenic: Add newer vendor IDs
...
Ingenic have actually varied the vendor/company ID of the XBurst cores
across their range of SoCs, whilst keeping the product ID & revision
constant... Add definitions for vendor IDs known to be used in some of
Ingenic's newer SoCs, and handle them in the same way as the existing
Ingenic vendor ID from the JZ4740.
Signed-off-by: Paul Burton <paul.burton@imgtec.com >
Co-authored-by: Paul Cercueil <paul@crapouillou.net >
Cc: Lars-Peter Clausen <lars@metafoo.de >
Cc: linux-mips@linux-mips.org
Cc: Steven J. Hill <Steven.Hill@imgtec.com >
Cc: Joshua Kinard <kumba@gentoo.org >
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com >
Cc: Maciej W. Rozycki <macro@linux-mips.org >
Cc: linux-kernel@vger.kernel.org
Cc: Huacai Chen <chenhc@lemote.com >
Cc: Markos Chandras <markos.chandras@imgtec.com >
Patchwork: https://patchwork.linux-mips.org/patch/10128/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:52:48 +02:00
de361e8bb9
MIPS: JZ4740: introduce CONFIG_MACH_INGENIC
...
In preparation for supporting Ingenic SoCs other than the JZ4740,
introduce MACH_INGENIC to Kconfig & move MACH_JZ4740 to a separate
entry selected by the board when appropriate. This allows MACH_INGENIC
to be used to enable things generic across Ingenic SoCs.
Signed-off-by: Paul Burton <paul.burton@imgtec.com >
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Andrew Bresticker <abrestic@chromium.org >
Patchwork: https://patchwork.linux-mips.org/patch/10130/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2015-06-21 21:52:47 +02:00
Paul Burton
Ralf Baechle