In the microMIPS encoding some memory access instructions have their
immediate offset reduced to 12 bits only. That does not match the GCC
`R' constraint we use in some places to satisfy the requirement,
resulting in build failures like this:
{standard input}: Assembler messages:
{standard input}:720: Error: macro used $at after ".set noat"
{standard input}:720: Warning: macro instruction expanded into multiple instructions
Fix the problem by defining a macro, `GCC_OFF12_ASM', that expands to
the right constraint depending on whether microMIPS or standard MIPS
code is produced. Also apply the fix to where `m' is used as in the
worst case this change does nothing, e.g. where the pointer was already
in a register such as a function argument and no further offset was
requested, and in the best case it avoids an extraneous sequence of up
to two instructions to load the high 20 bits of the address in the LL/SC
loop. This reduces the risk of lock contention that is the higher the
more instructions there are in the critical section between LL and SC.
Strictly speaking we could just bulk-replace `R' with `ZC' as the latter
constraint adjusts automatically depending on the ISA selected.
However it was only introduced with GCC 4.9 and we keep supporing older
compilers for the standard MIPS configuration, hence the slightly more
complicated approach I chose.
The choice of a zero-argument function-like rather than an object-like
macro was made so that it does not look like a function call taking the
C expression used for the constraint as an argument. This is so as not
to confuse the reader or formatting checkers like `checkpatch.pl' and
follows previous practice.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8482/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Only allow 32-bit microMIPS builds, we're not ready yet for 64-bit
microMIPS support.
QEMU does have support for the 64-bit microMIPS ISA and with minor
tweaks it is possible to have a 64-bit processor emulated there that
runs microMIPS code, so despite the lack of actual 64-bit microMIPS
hardware there is a way to run 64-bit microMIPS Linux, but it can all be
considered early development and we are not there yet. Userland tools
are lacking too, e.g. GCC produces bad code:
{standard input}: Assembler messages:
{standard input}:380: Warning: wrong size instruction in a 16-bit branch delay slot
And our build fails early on, so disable the configuration, for the sake
of automatic random config checkers if nothing else. Whoever needs to
experiment with 64-bit microMIPS support can revert this change easily.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8481/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Fix:
arch/mips/kernel/signal.c: In function 'handle_signal':
arch/mips/kernel/signal.c:533:21: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
unsigned int tmp = (unsigned int)current->mm->context.vdso;
^
arch/mips/kernel/signal.c:536:9: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]
vdso = (void *)tmp;
^
cc1: all warnings being treated as errors
when building a 64-bit kernel.
This is not really a supported configuration, but the cast is wrong
either way, Linux makes the assumption that sizeof(void *) equals
sizeof(unsigned long) and therefore the latter type is expected to be
used where integer operations have to be applied to pointers for some
reason.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8480/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The microMIPS microassembler is only suitable for configurations where
the kernel itself is built to microMIPS machine code and not where only
user microMIPS software is supported. The former is controlled with the
CPU_MICROMIPS configuration setting, whereas SYS_SUPPORTS_MICROMIPS is
used for the latter.
Not only that, but with a given microMIPS vs standard MIPS kernel
configuration only one microassembler is needed, that matches the ISA
selected -- CP0.Config3.ISAOnExc is mandatory on microMIPS processors,
so there is never a need to mix microMIPS and standard MIPS code.
Consequently build only the microassembler that matches the ISA selected
for the kernel.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8479/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Add missing microMIPS support to Malta. Currently the kernel only
enables support for the instruction set for the SEAD-3 board despite the
fact processor features have nothing to do with the board a processor is
installed in.
In this case there is no way to run microMIPS software in a fully
supported way under Linux on QEMU. QEMU supports the emulation of a
Malta board, but does not emulate SEAD-3. Linux supports running
microMIPS code on a SEAD-3 board, but hardcodes such support to off on
an emulated Malta board even if the processor selected has the microMIPS
instruction set implemented.
Adding support for the SEAD-3 to QEMU is a major project. Flipping a
bit in the kernel that shouldn't have been cleared in the first place is
a trivial effort. Thus the answer is plain...
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8478/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Building a 64bit kernel for the SGI O2 (IP32) and the SGI Indy (IP22) uses
the 'vmlinux.32' target, which converts the output 64-bit 'vmlinux' image
into a 32-bit wrapped image. This is needed for certain revisions of the
IP22 and IP32 ARCS PROMs to boot correctly, but this target is missing
from the 'archhelp' info that is emitted by 'make help'.
Signed-off-by: Joshua Kinard <kumba@gentoo.org>
Cc: Linux MIPS List <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/7991/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
We should not need to read fuses during normal operation, also the current
code has issues with that (not safe for concurrent access). Since there
are no in-kernel users for these, just delete them. Drivers should
not need such OCTEON_HAS_FEATURE mechanism in any case, instead the
information should be passed via device tree.
Signed-off-by: Aaro Koskinen <aaro.koskinen@nsn.com>
Cc: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7665/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Allow unsupported CPU types to use backtrace with timer-based profiling.
Some CPUs (notably OCTEON) lack architecture-specific oprofile driver. In
such case oprofile can fallback to timer-based mode, and arch code can
still provide the backtrace functionality. So just set up the backtrace
hook always.
Signed-off-by: Aaro Koskinen <aaro.koskinen@nsn.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8108/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Maciej W. Rozycki
Aaro Koskinen
Ralf Baechle
Joshua Kinard
Markos Chandras
Aaro Koskinen
Andrew Bresticker