Commit Graph

664078 Commits

Author SHA1 Message Date
Adam Borowski 99a97a8ba9 drm/nouveau/gpio: enable interrupts on cards with 32 gpio lines
The code attempts to enable them, but hits an undefined behaviour by
shifting by the entire register's width:

    int lines = 32;
    u32 mask = (1 << lines) - 1;    // 00000000 on x86
    u32 mask = (1 << lines) - 1;    // ffffffff on arm (32)
    u32 mask = (1 << lines) - 1;    // 00000000 on arm64
    u32 mask = (1ULL << lines) - 1; // ffffffff everywhere

Signed-off-by: Adam Borowski <kilobyte@angband.pl>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:53:50 +10:00
Ben Skeggs b2c4ef7079 drm/nouveau/gr/gp107: initial support
Forked from GP106 implementation.

Differences:
- 1 PPC/GPC
- Slightly different grctx magics

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:04 +10:00
Alexandre Courbot fa1dbc4972 drm/nouveau/core: recognise GP10B chipset
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:04 +10:00
Alexandre Courbot c3f7de6a4c drm/nouveau/platform: support for probing GP10B
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:04 +10:00
Alexandre Courbot e6e1817a55 drm/nouveau/platform: make VDD regulator optional
GP10B's power is managed by generic PM domains, so it does not require a
VDD regulator. Add this option into the chip function structure.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:04 +10:00
Alexandre Courbot 51751f7db0 drm/nouveau/gr: support for GP10B
GR is similar to GP100, with a few unavailable registers.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:04 +10:00
Alexandre Courbot 0af0327cd9 drm/nouveau/ibus: add GP10B support
GP10B requires a specific initialization sequence due to the absence of
devinit.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:04 +10:00
Alexandre Courbot b9a995def6 drm/nouveau/mc: add GP10B support
GP10B's MC is compatible with GP100's, but engines need to be explicitly
put out of ELPG during init.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:04 +10:00
Alexandre Courbot fdde00ed11 drm/nouveau/fb: add GP10B support
GP10B's FB is largely compatible with the GP100 implementation.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:04 +10:00
Alexandre Courbot af3a4f7efb drm/nouveau/fifo: add GP10B support
GP10B's FIFO is similar to GP100's, but only allows 512 channels.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:04 +10:00
Alexandre Courbot a558be625c drm/nouveau/msgqueue: support for GP10B PMU firmware
The GP10B firmware is very close to GM20B's. The only difference is that
it supports booting multiple falcons. In order to avoid having too much
functions and structures shared, implement its support in the same
source file as GM20B firmware.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:04 +10:00
Alexandre Courbot 59d5592d3b drm/nouveau/secboot: add GP10B support
GP10B's secboot is largely similar to GM20B's. Only differences are MC
base address and the fact that GPCCS is also securely managed.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:04 +10:00
Alexandre Courbot c79505c1f9 drm/nouveau/secboot/gm20b: specify MC base address as argument
Allow the MC base address to be specified as an argument for the WPR
region reading function. GP10B uses a different address layout as GM20B,
so this is necessary. Also export the function to be used by GP10B.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:04 +10:00
Alexandre Courbot 008796d9a3 drm/nouveau/secboot: start LS firmware in post-run hook
The LS firmware post-run hook is the right place to start said LS
firmware. Moving it here also allows to remove special handling in the
ACR code.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:04 +10:00
Alexandre Courbot d424d278b2 drm/nouveau/secboot: let LS post_run hooks return error
A LS post-run hook can meet an error meaning the failure of secure boot.
Make sure this can be reported.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:04 +10:00
Alexandre Courbot 2963a06a4d drm/nouveau/secboot: pass instance to LS firmware loaders
Having access to the secboot instance loading a LS firmware can be
useful to LS firmware handlers. At least more useful than just having an
out-of-context subdev pointer.

GP10B's firmware will also need to know the WPR address, which can be
obtained from the secboot instance.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:04 +10:00
Alexandre Courbot 598a8148e7 drm/nouveau/secboot: allow to boot multiple falcons
Change the secboot and msgqueue interfaces to take a mask of falcons to
reset instead of a single falcon. The GP10B firmware interface requires
FECS and GPCCS to be booted in a single firmware command.

For firmwares that only support single falcon boot, it is trivial to
loop over the mask and boot each falcons individually.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:03 +10:00
Thierry Reding e5ffa727e5 drm/nouveau/imem/gk20a: Turn instmem lock into mutex
The gk20a implementation of instance memory uses vmap()/vunmap() to map
memory regions into the kernel's virtual address space. These functions
may sleep, so protecting them by a spin lock is not safe. This triggers
a warning if the DEBUG_ATOMIC_SLEEP Kconfig option is enabled. Fix this
by using a mutex instead.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:03 +10:00
Ben Skeggs 2ebd42bc28 drm/nouveau: initial support (display-only) for GP107
Forked from GP106 implementation.

Split out from commit enabling secboot/gr support so that it can be
added to earlier kernels.

Cc: stable@vger.kernel.org	[4.10+]
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:38:38 +10:00
Ben Skeggs df60d1f23b drm/nouveau/kms/nv50: fix double dma_fence_put() when destroying plane state
When the atomic support was added to nouveau, the DRM core did not do this.

However, later in the same merge window, a commit (drm/fence: add in-fences
support) was merged that added it, leading to use-after-frees of the fence
object.

Cc: stable@vger.kernel.org	[4.10+]
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:38:34 +10:00
Ben Skeggs aeecfcd744 drm/nouveau/kms/nv50: fix setting of HeadSetRasterVertBlankDmi method
Cc: stable@vger.kernel.org	[4.10+]
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:38:31 +10:00
Ilia Mirkin ac799acaa4 drm/nouveau/mmu/nv4a: use nv04 mmu rather than the nv44 one
The NV4A (aka NV44A) is an oddity in the family. It only comes in AGP
and PCI varieties, rather than a core PCIE chip with a bridge for
AGP/PCI as necessary. As a result, it appears that the MMU is also
non-functional. For AGP cards, the vast majority of the NV4A lineup,
this worked out since we force AGP cards to use the nv04 mmu. However
for PCI variants, this did not work.

Switching to the NV04 MMU makes it work like a charm. Thanks to mwk for
the suggestion. This should be a no-op for NV4A AGP boards, as they were
using it already.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70388
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: stable@vger.kernel.org
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:38:25 +10:00
Ilia Mirkin ad01a91a82 drm/nouveau/mpeg: mthd returns true on success now
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Fixes: 590801c1a3 ("drm/nouveau/mpeg: remove dependence on namedb/engctx lookup")
Cc: stable@vger.kernel.org # v4.3+
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:38:22 +10:00
Dave Airlie fabe2be10f Merge branch 'drm/next/du' of git://linuxtv.org/pinchartl/media into drm-next
RCAR GEN3 DU HDMI support.

* 'drm/next/du' of git://linuxtv.org/pinchartl/media: (22 commits)
  drm: rcar-du: Add HDMI outputs to R8A7795 device description
  drm: rcar-du: Add DPLL support
  drm: rcar-du: Skip disabled outputs
  drm: rcar-du: Add Gen3 HDMI encoder support
  dt-bindings: display: renesas: Add R-Car Gen3 HDMI TX DT bindings
  drm: rcar-du: Hardcode encoders types to DRM_MODE_ENCODER_NONE
  drm: rcar-du: Replace manual bridge implementation with DRM bridge
  drm: rcar-du: Add support for LVDS mode selection
  drm: rcar-du: Use the DRM panel API
  drm: rcar-du: Document the vsps property in the DT bindings
  drm: rcar-du: Remove wait field from rcar_du_device structure
  drm: rcar-du: Make sure the VSP is initialized on platforms that need it
  drm: rcar-du: Use DRM core's atomic commit helper
  drm: rcar-du: Clear handled event pointer in CRTC state
  drm: rcar-du: Handle event when disabling CRTCs
  drm: rcar-du: Don't open code of_device_get_match_data()
  drm: rcar-du: Switch to encoder .atomic_mode_set() helper function
  drm: panels: Add LVDS panel driver
  drm: Add data transmission order bus flag
  devicetree/bindings: display: Add bindings for two Mitsubishi panels
  ...
2017-04-05 07:17:12 +10:00
Koji Matsuoka 0dda563e57 drm: rcar-du: Add HDMI outputs to R8A7795 device description
Update the device description with the two available HDMI outputs.

Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2017-04-04 17:04:21 +03:00