Commit Graph

217192 Commits

Author SHA1 Message Date
Nicolas Ferre 24cecc1be6 AT91: rtc: enable built-in RTC in Kconfig for at91sam9g45 family
Enable built-in RTC IP in Kconfig and modify comments and help messages.
RTT as RTC is still available but should not be selected in common case.

Reported-by: Yegor Yefremov <yegor_sub1@visionsystems.de>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2010-10-26 11:32:49 +02:00
Nicolas Ferre 75305d768d at91/atmel-mci: inclusion of sd/mmc driver in at91sam9g45 chip and board
This adds the support of atmel-mci sd/mmc driver in at91sam9g45 devices and
board files. This also configures the DMA controller slave interface for
at_hdmac dmaengine driver.

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2010-10-26 11:32:49 +02:00
Nicolas Ferre a2a571b74a AT91: pm: make sure that r0 is 0 when dealing with cache operations
When using CP15 cache operations (c7), we make sure that Rd (r0)
is actually 0 as ARM 926 TRM is saying.

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2010-10-26 11:32:48 +02:00
Nicolas Ferre 8aeeda822f AT91: pm: use plain cpu_do_idle() for "wait for interrupt"
For power management at91_pm_enter() routine, use the cpu_do_idle() for a
rock solid "wait for interrupt" implementation.
For AT91SAM9 ARM 926 based chips, we can exceed the cache line length as
we can access RAM even while in self-refresh mode.
We keep plain access to CP15 for at91rm9200 as this feature is not
available: instructions have to be in a single cache line.

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2010-10-26 11:32:48 +02:00
Nicolas Ferre bb413db591 AT91: reset: extend alternate reset procedure to several chips
Several at91sam9 chips need the alternate reset procedure to be sure to halt
SDRAM smoothly before resetting the chip.
This is an extension of previous patch "Fix AT91SAM9G20 reset" to all chips
affected.

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2010-10-26 11:32:48 +02:00
Nicolas Ferre 1345562b44 AT91: reset routine cleanup, remove not needed icache flush
Generalize assembler reset routine to allow use on several at91sam9 chips.
This patch replace double definitions of SDRAM controller registers and RSTC
registers with use of classical header files.

For this rework, we remove the not needed icache flush as it is already
done in the calling function: arm_machine_restart().

Rename at91sam9g20_reset.S to generalize to several chips.

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2010-10-26 11:32:48 +02:00
Nicolas Ferre ef4d63e6f5 AT91: trivial: align comment of at91sam9g20_reset with one more tab
Preparing next patch with longer names

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2010-10-26 11:32:47 +02:00
Peter Horton 184c82e853 AT91: Fix AT91SAM9G20 reset as per the errata in the data sheet
If the SDRAM is not cleanly shutdown before reset it can be left driving
the bus, which then stops the bootloader booting from NAND.

Signed-off-by: Peter Horton <phorton@bitbox.co.uk>
[nicolas.ferre@atmel.com: change file header line order]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2010-10-26 11:32:47 +02:00
Peter Gsellmann abf0c1bc94 AT91: add board support for Pcontrol_G20
Board is a carrier board for Stamp9G20, with additional peripherals
for a building automation system

Signed-off-by: Peter Gsellmann <pgsellmann@portner-elektronik.at>
[nicolas.ferre@atmel.com: remove machine_desc.io_pg_offst and .phys_io]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2010-10-26 11:32:47 +02:00
Linus Torvalds b18cae4224 Merge branch 'for-next' of git://android.git.kernel.org/kernel/tegra
* 'for-next' of git://android.git.kernel.org/kernel/tegra:
  spi: tegra: fix error setting on timeout
  spi: add spi_tegra driver
  tegra: harmony: enable PCI Express
  tegra: add PCI Express support
  tegra: add PCI Express clocks
  [ARM] tegra: Add APB DMA support
  [ARM] tegra: Add cpufreq support
  [ARM] tegra: common: Update common clock init table
  [ARM] tegra: clock: Add dvfs support, bug fixes, and cleanups
  [ARM] tegra: Add support for reading fuses
  [ARM] tegra: gpio: Add suspend and wake support
  [ARM] tegra: pinmux: add safe values, move tegra2, add suspend
  [ARM] tegra: add suspend and mirror irqs to legacy controller
  [ARM] tegra: Add legacy irq support
  [ARM] tegra: update iomap
2010-10-25 18:42:06 -07:00
Linus Torvalds 4833c16dea Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin:
  Blackfin: fix inverted anomaly 05000481 logic
  Blackfin: drop unused irq_panic()/DEBUG_ICACHE_CHECK
  Blackfin: ppi/spi/twi headers: add missing __BFP undef
  Blackfin: update defconfigs
  Blackfin: bfin_twi.h: start a common TWI header
  netdev: bfin_mac: push settings to platform resources
2010-10-25 18:41:32 -07:00
Erik Gilling f41649e040 spi: tegra: fix error setting on timeout
avoids derefencing an uninitialized pointer

Change-Id: Icf528441ae481e9f6f5ddc0be32c7c217fa49701
Signed-off-by: Erik Gilling <konkers@android.com>
2010-10-25 16:57:46 -07:00
Linus Torvalds e0e170bd7d Merge branch 'next' of git://git.monstr.eu/linux-2.6-microblaze
* 'next' of git://git.monstr.eu/linux-2.6-microblaze: (42 commits)
  microblaze: Fix build with make 3.82
  fbdev/xilinxfb: Microblaze driver support
  microblaze: Support C optimized lib functions for little-endian
  microblaze: Separate library optimized functions
  microblaze: Support timer on AXI lite
  microblaze: Add support for little-endian Microblaze
  microblaze: KGDB little endian support
  microblaze: Add PVR for endians plus detection
  net: emaclite: Add support for little-endian platforms
  microblaze: trivial: Add comment for AXI pvr
  microblaze: pci-common cleanup
  microblaze: Support early console on uart16550
  microblaze: Do not compile early console support for uartlite if is disabled
  microblaze: Setup early console dynamically
  microblaze: Rename all uartlite early printk functions
  microblaze: remove early printk uarlite console dependency from header
  microblaze: Remove additional compatible properties
  microblaze: Remove hardcoded asm instraction for PVR loading
  microblaze: Use static const char * const where possible
  microblaze: Define VMALLOC_START/END
  ...
2010-10-25 16:53:11 -07:00
Linus Torvalds b20f9e5bdd Merge branch 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/staging
* 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/staging: (24 commits)
  hwmon: lis3: Release resources in case of failure
  hwmon: lis3: Short explanations of platform data fields
  hwmon: lis3: Enhance lis3 selftest with IRQ line test
  hwmon: lis3: use block read to access data registers
  hwmon: lis3: Adjust fuzziness for 8 bit device
  hwmon: lis3: New parameters to platform data
  hwmon: lis3: restore axis enabled bits
  hwmon: lis3: Power on corrections
  hwmon: lis3: Update coordinates at polled device open
  hwmon: lis3: Cleanup interrupt handling
  hwmon: lis3: regulator control
  hwmon: lis3: pm_runtime support
  Kirkwood: add fan support for Network Space Max v2
  hwmon: add generic GPIO fan driver
  hwmon: (coretemp) fix reading of microcode revision (v2)
  hwmon: ({core, pkg, via-cpu}temp) remove unnecessary CONFIG_HOTPLUG_CPU ifdefs
  hwmon: (pkgtemp) align driver initialization style with coretemp
  hwmon: LTC4261 Hardware monitoring driver
  hwmon: (lis3) add axes module parameter for custom axis-mapping
  hwmon: (hp_accel) Add HP Mini 510x family support
  ...
2010-10-25 16:25:31 -07:00
David Howells 5260562754 MN10300: Fix the PERCPU() alignment to allow for workqueues
In the MN10300 arch, we occasionally see an assertion being tripped in
alloc_cwqs() at the following line:

        /* just in case, make sure it's actually aligned */
  --->  BUG_ON(!IS_ALIGNED(wq->cpu_wq.v, align));
        return wq->cpu_wq.v ? 0 : -ENOMEM;

The values are:

        wa->cpu_wq.v => 0x902776e0
        align => 0x100

and align is calculated by the following:

        const size_t align = max_t(size_t, 1 << WORK_STRUCT_FLAG_BITS,
                                   __alignof__(unsigned long long));

This is because the pointer in question (wq->cpu_wq.v) loses some of its
lower bits to control flags, and so the object it points to must be
sufficiently aligned to avoid the need to use those bits for pointing to
things.

Currently, 4 control bits and 4 colour bits are used in normal
circumstances, plus a debugging bit if debugging is set.  This requires
the cpu_workqueue_struct struct to be at least 256 bytes aligned (or 512
bytes aligned with debugging).

PERCPU() alignment on MN13000, however, is only 32 bytes as set in
vmlinux.lds.S.  So we set this to PAGE_SIZE (4096) to match most other
arches and stick a comment in alloc_cwqs() for anyone else who triggers
the assertion.

Reported-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: David Howells <dhowells@redhat.com>
Acked-by: Mark Salter <msalter@redhat.com>
Cc: Tejun Heo <tj@kernel.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-10-25 16:24:06 -07:00
Samu Onkalo b11e7b3f3b hwmon: lis3: Release resources in case of failure
If lis3lv02d_init_device fails, HW resources were not released
properly. In case of failure call release_resources if available.

Signed-off-by: Samu Onkalo <samu.p.onkalo@nokia.com>
Acked-by: Eric Piel <eric.piel@tremplin-utc.net>
Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com>
2010-10-25 14:44:59 -07:00
Mike Frysinger ad3e01a331 Blackfin: fix inverted anomaly 05000481 logic
No one uses these MMRs so we didn't notice when the anomaly handling
logic was inverted.

Reported-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-10-25 17:24:00 -04:00
Mike Frysinger 09ebdedf48 Blackfin: drop unused irq_panic()/DEBUG_ICACHE_CHECK
This code was useful during early port development when our icache code
wasn't solid, but that ship has sailed long ago, and no code calls this
function anymore (irq_panic).  So punt it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-10-25 17:24:00 -04:00
Samu Onkalo 83af1bd81f hwmon: lis3: Short explanations of platform data fields
Short documentation at kernel doc format.

Signed-off-by: Samu Onkalo <samu.p.onkalo@nokia.com>
Acked-by: Jonathan Cameron <jic23@cam.ac.uk>
Acked-by: Eric Piel <eric.piel@tremplin-utc.net>
Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com>
2010-10-25 14:11:39 -07:00
Samu Onkalo 029756d0b8 hwmon: lis3: Enhance lis3 selftest with IRQ line test
Configure chip to data ready mode in selftest and count received
interrupts to see that interrupt line(s) are working.

Signed-off-by: Samu Onkalo <samu.p.onkalo@nokia.com>
Acked-by: Eric Piel <eric.piel@tremplin-utc.net>
Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com>
2010-10-25 14:11:39 -07:00
Samu Onkalo f10a5407b5 hwmon: lis3: use block read to access data registers
Add optional blockread function to interface driver. If available
the chip driver uses it for data register access. For 12 bit device
it reads 6 bytes to get 3*16bit data. For 8 bit device it reads out
5 bytes since every second byte is dummy.
This optimizes bus usage and reduces number of operations and
interrupts needed for one data update.

Signed-off-by: Samu Onkalo <samu.p.onkalo@nokia.com>
Acked-by: Jonathan Cameron <jic23@cam.ac.uk>
Acked-by: Eric Piel <eric.piel@tremplin-utc.net>
Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com>
2010-10-25 14:11:39 -07:00
Samu Onkalo 477bc918c2 hwmon: lis3: Adjust fuzziness for 8 bit device
Default fuziness is set smaller for 8 device.
In 12 bit device LSB is quite close to 1 mg
(mg = 1 / 1000 of earth gravity).
In 8bit device LSB is about 18 mg.
Set fuziness to 1 for 8 bit device.

Signed-off-by: Samu Onkalo <samu.p.onkalo@nokia.com>
Acked-by: Eric Piel <eric.piel@tremplin-utc.net>
Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com>
2010-10-25 14:11:39 -07:00
Samu Onkalo cc23aa1ce2 hwmon: lis3: New parameters to platform data
Added default output data rate setting to platform data.
If default rate is 0, reset default value is used.
Added control for duration via platform data.
Added possibility to configure interrupts to trig on
both rising and falling edge. The lis3 WU unit can be
configured quite many ways and with some configurations it
is quite handy to get coordinate refresh when some
event trigs and when it reason goes away.

Signed-off-by: Samu Onkalo <samu.p.onkalo@nokia.com>
Acked-by: Jonathan Cameron <jic23@cam.ac.uk>
Acked-by: Eric Piel <eric.piel@tremplin-utc.net>
Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com>
2010-10-25 14:11:38 -07:00
Samu Onkalo ed37d7f619 hwmon: lis3: restore axis enabled bits
All axis enable bits are set to 0 at module remove.
Restore reset default value at init.

Signed-off-by: Samu Onkalo <samu.p.onkalo@nokia.com>
Acked-by: Eric Piel <eric.piel@tremplin-utc.net>
Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com>
2010-10-25 14:11:38 -07:00
Samu Onkalo 2a7fade7e0 hwmon: lis3: Power on corrections
Sometimes lis3 chip seems to fail to setup factory tuning at boot up.
This probably happens if there is some odd power ramp down ramp up sequence
for example in device restart. Set boot bit in control2 register to
trig boot sequence manually and wait until it is finished.

Signed-off-by: Samu Onkalo <samu.p.onkalo@nokia.com>
Acked-by: Jonathan Cameron <jic23@cam.ac.uk>
Acked-by: Eric Piel <eric.piel@tremplin-utc.net>
Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com>
2010-10-25 14:11:38 -07:00