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Merge branch 'tegra/clk' into next/dt2
This is a dependency for the tegra/dt branch. Conflicts: drivers/clocksource/tegra20_timer.c Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
@@ -0,0 +1,56 @@
|
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Frequently asked questions about the sunxi clock system
|
||||
=======================================================
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||||
|
||||
This document contains useful bits of information that people tend to ask
|
||||
about the sunxi clock system, as well as accompanying ASCII art when adequate.
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||||
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||||
Q: Why is the main 24MHz oscillator gatable? Wouldn't that break the
|
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system?
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||||
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||||
A: The 24MHz oscillator allows gating to save power. Indeed, if gated
|
||||
carelessly the system would stop functioning, but with the right
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steps, one can gate it and keep the system running. Consider this
|
||||
simplified suspend example:
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||||
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||||
While the system is operational, you would see something like
|
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24MHz 32kHz
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|
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PLL1
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\
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\_ CPU Mux
|
||||
|
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||||
[CPU]
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|
||||
When you are about to suspend, you switch the CPU Mux to the 32kHz
|
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oscillator:
|
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|
||||
24Mhz 32kHz
|
||||
| |
|
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PLL1 |
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/
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CPU Mux _/
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|
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[CPU]
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Finally you can gate the main oscillator
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32kHz
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|
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||||
|
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||||
/
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CPU Mux _/
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|
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[CPU]
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||||
Q: Were can I learn more about the sunxi clocks?
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||||
A: The linux-sunxi wiki contains a page documenting the clock registers,
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you can find it at
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http://linux-sunxi.org/A10/CCM
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||||
The authoritative source for information at this time is the ccmu driver
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released by Allwinner, you can find it at
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https://github.com/linux-sunxi/linux-sunxi/tree/sunxi-3.0/arch/arm/mach-sun4i/clock/ccmu
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@@ -174,9 +174,9 @@ int clk_foo_enable(struct clk_hw *hw)
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};
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|
||||
Below is a matrix detailing which clk_ops are mandatory based upon the
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hardware capbilities of that clock. A cell marked as "y" means
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hardware capabilities of that clock. A cell marked as "y" means
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mandatory, a cell marked as "n" implies that either including that
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callback is invalid or otherwise uneccesary. Empty cells are either
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callback is invalid or otherwise unnecessary. Empty cells are either
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optional or must be evaluated on a case-by-case basis.
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clock hardware characteristics
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@@ -1,19 +1,84 @@
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NVIDIA Tegra Power Management Controller (PMC)
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Properties:
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The PMC block interacts with an external Power Management Unit. The PMC
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mostly controls the entry and exit of the system from different sleep
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modes. It provides power-gating controllers for SoC and CPU power-islands.
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Required properties:
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- name : Should be pmc
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- compatible : Should contain "nvidia,tegra<chip>-pmc".
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- reg : Offset and length of the register set for the device
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- clocks : Must contain an entry for each entry in clock-names.
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- clock-names : Must include the following entries:
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"pclk" (The Tegra clock of that name),
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"clk32k_in" (The 32KHz clock input to Tegra).
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Optional properties:
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- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
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The PMU is an external Power Management Unit, whose interrupt output
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signal is fed into the PMC. This signal is optionally inverted, and then
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fed into the ARM GIC. The PMC is not involved in the detection or
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handling of this interrupt signal, merely its inversion.
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- nvidia,suspend-mode : The suspend mode that the platform should use.
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Valid values are 0, 1 and 2:
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0 (LP0): CPU + Core voltage off and DRAM in self-refresh
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1 (LP1): CPU voltage off and DRAM in self-refresh
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2 (LP2): CPU voltage off
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- nvidia,core-power-req-active-high : Boolean, core power request active-high
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- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high
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- nvidia,combined-power-req : Boolean, combined power request for CPU & Core
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- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
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is enabled.
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Required properties when nvidia,suspend-mode is specified:
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- nvidia,cpu-pwr-good-time : CPU power good time in uS.
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- nvidia,cpu-pwr-off-time : CPU power off time in uS.
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- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time>
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Core power good time in uS.
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- nvidia,core-pwr-off-time : Core power off time in uS.
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Required properties when nvidia,suspend-mode=<0>:
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- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector
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The LP0 vector contains the warm boot code that is executed by AVP when
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resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7
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processor and always being the first boot processor when chip is power on
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or resume from deep sleep mode. When the system is resumed from the deep
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sleep mode, the warm boot code will restore some PLLs, clocks and then
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bring up CPU0 for resuming the system.
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Example:
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/ SoC dts including file
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pmc@7000f400 {
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compatible = "nvidia,tegra20-pmc";
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reg = <0x7000e400 0x400>;
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clocks = <&tegra_car 110>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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nvidia,invert-interrupt;
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nvidia,suspend-mode = <1>;
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nvidia,cpu-pwr-good-time = <2000>;
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nvidia,cpu-pwr-off-time = <100>;
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nvidia,core-pwr-good-time = <3845 3845>;
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nvidia,core-pwr-off-time = <458>;
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nvidia,core-power-req-active-high;
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nvidia,sys-clock-req-active-high;
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nvidia,lp0-vec = <0xbdffd000 0x2000>;
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};
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/ Tegra board dts file
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{
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...
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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clk32k_in: clock {
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compatible = "fixed-clock";
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reg=<0>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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...
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};
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@@ -0,0 +1,22 @@
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Binding for the axi-clkgen clock generator
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be "adi,axi-clkgen".
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- #clock-cells : from common clock binding; Should always be set to 0.
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- reg : Address and length of the axi-clkgen register set.
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- clocks : Phandle and clock specifier for the parent clock.
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Optional properties:
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- clock-output-names : From common clock binding.
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Example:
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clock@0xff000000 {
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compatible = "adi,axi-clkgen";
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#clock-cells = <0>;
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reg = <0xff000000 0x1000>;
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clocks = <&osc 1>;
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};
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@@ -0,0 +1,303 @@
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NVIDIA Tegra114 Clock And Reset Controller
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This binding uses the common clock binding:
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
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for muxing and gating Tegra's clocks, and setting their rates.
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Required properties :
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- compatible : Should be "nvidia,tegra114-car"
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- reg : Should contain CAR registers location and length
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- clocks : Should contain phandle and clock specifiers for two clocks:
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the 32 KHz "32k_in", and the board-specific oscillator "osc".
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- #clock-cells : Should be 1.
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In clock consumers, this cell represents the clock ID exposed by the CAR.
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The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
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registers. These IDs often match those in the CAR's RST_DEVICES registers,
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but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
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this case, those clocks are assigned IDs above 160 in order to highlight
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this issue. Implementations that interpret these clock IDs as bit values
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within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
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explicitly handle these special cases.
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The balance of the clocks controlled by the CAR are assigned IDs of 160 and
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above.
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0 unassigned
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1 unassigned
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2 unassigned
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3 unassigned
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4 rtc
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5 timer
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6 uarta
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7 unassigned (register bit affects uartb and vfir)
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8 unassigned
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9 sdmmc2
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10 unassigned (register bit affects spdif_in and spdif_out)
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11 i2s1
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12 i2c1
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13 ndflash
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14 sdmmc1
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15 sdmmc4
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16 unassigned
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17 pwm
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18 i2s2
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19 epp
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20 unassigned (register bit affects vi and vi_sensor)
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21 2d
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22 usbd
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23 isp
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24 3d
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25 unassigned
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26 disp2
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27 disp1
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28 host1x
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29 vcp
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30 i2s0
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31 unassigned
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32 unassigned
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33 unassigned
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34 apbdma
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35 unassigned
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36 kbc
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37 unassigned
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38 unassigned
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39 unassigned (register bit affects fuse and fuse_burn)
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40 kfuse
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41 sbc1
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42 nor
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43 unassigned
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44 sbc2
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45 unassigned
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||||
46 sbc3
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47 i2c5
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48 dsia
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49 unassigned
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||||
50 mipi
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51 hdmi
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52 csi
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53 unassigned
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||||
54 i2c2
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||||
55 uartc
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56 mipi-cal
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57 emc
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58 usb2
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59 usb3
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60 msenc
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61 vde
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62 bsea
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63 bsev
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64 unassigned
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||||
65 uartd
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66 unassigned
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||||
67 i2c3
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68 sbc4
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69 sdmmc3
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70 unassigned
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||||
71 owr
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||||
72 afi
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||||
73 csite
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||||
74 unassigned
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||||
75 unassigned
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||||
76 la
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77 trace
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78 soc_therm
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79 dtv
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||||
80 ndspeed
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||||
81 i2cslow
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||||
82 dsib
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83 tsec
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||||
84 unassigned
|
||||
85 unassigned
|
||||
86 unassigned
|
||||
87 unassigned
|
||||
88 unassigned
|
||||
89 xusb_host
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||||
90 unassigned
|
||||
91 msenc
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||||
92 csus
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||||
93 unassigned
|
||||
94 unassigned
|
||||
95 unassigned (bit affects xusb_dev and xusb_dev_src)
|
||||
|
||||
96 unassigned
|
||||
97 unassigned
|
||||
98 unassigned
|
||||
99 mselect
|
||||
100 tsensor
|
||||
101 i2s3
|
||||
102 i2s4
|
||||
103 i2c4
|
||||
104 sbc5
|
||||
105 sbc6
|
||||
106 d_audio
|
||||
107 apbif
|
||||
108 dam0
|
||||
109 dam1
|
||||
110 dam2
|
||||
111 hda2codec_2x
|
||||
112 unassigned
|
||||
113 audio0_2x
|
||||
114 audio1_2x
|
||||
115 audio2_2x
|
||||
116 audio3_2x
|
||||
117 audio4_2x
|
||||
118 spdif_2x
|
||||
119 actmon
|
||||
120 extern1
|
||||
121 extern2
|
||||
122 extern3
|
||||
123 unassigned
|
||||
124 unassigned
|
||||
125 hda
|
||||
126 unassigned
|
||||
127 se
|
||||
|
||||
128 hda2hdmi
|
||||
129 unassigned
|
||||
130 unassigned
|
||||
131 unassigned
|
||||
132 unassigned
|
||||
133 unassigned
|
||||
134 unassigned
|
||||
135 unassigned
|
||||
136 unassigned
|
||||
137 unassigned
|
||||
138 unassigned
|
||||
139 unassigned
|
||||
140 unassigned
|
||||
141 unassigned
|
||||
142 unassigned
|
||||
143 unassigned (bit affects xusb_falcon_src, xusb_fs_src,
|
||||
xusb_host_src and xusb_ss_src)
|
||||
144 cilab
|
||||
145 cilcd
|
||||
146 cile
|
||||
147 dsialp
|
||||
148 dsiblp
|
||||
149 unassigned
|
||||
150 dds
|
||||
151 unassigned
|
||||
152 dp2
|
||||
153 amx
|
||||
154 adx
|
||||
155 unassigned (bit affects dfll_ref and dfll_soc)
|
||||
156 xusb_ss
|
||||
|
||||
192 uartb
|
||||
193 vfir
|
||||
194 spdif_in
|
||||
195 spdif_out
|
||||
196 vi
|
||||
197 vi_sensor
|
||||
198 fuse
|
||||
199 fuse_burn
|
||||
200 clk_32k
|
||||
201 clk_m
|
||||
202 clk_m_div2
|
||||
203 clk_m_div4
|
||||
204 pll_ref
|
||||
205 pll_c
|
||||
206 pll_c_out1
|
||||
207 pll_c2
|
||||
208 pll_c3
|
||||
209 pll_m
|
||||
210 pll_m_out1
|
||||
211 pll_p
|
||||
212 pll_p_out1
|
||||
213 pll_p_out2
|
||||
214 pll_p_out3
|
||||
215 pll_p_out4
|
||||
216 pll_a
|
||||
217 pll_a_out0
|
||||
218 pll_d
|
||||
219 pll_d_out0
|
||||
220 pll_d2
|
||||
221 pll_d2_out0
|
||||
222 pll_u
|
||||
223 pll_u_480M
|
||||
224 pll_u_60M
|
||||
225 pll_u_48M
|
||||
226 pll_u_12M
|
||||
227 pll_x
|
||||
228 pll_x_out0
|
||||
229 pll_re_vco
|
||||
230 pll_re_out
|
||||
231 pll_e_out0
|
||||
232 spdif_in_sync
|
||||
233 i2s0_sync
|
||||
234 i2s1_sync
|
||||
235 i2s2_sync
|
||||
236 i2s3_sync
|
||||
237 i2s4_sync
|
||||
238 vimclk_sync
|
||||
239 audio0
|
||||
240 audio1
|
||||
241 audio2
|
||||
242 audio3
|
||||
243 audio4
|
||||
244 spdif
|
||||
245 clk_out_1
|
||||
246 clk_out_2
|
||||
247 clk_out_3
|
||||
248 blink
|
||||
252 xusb_host_src
|
||||
253 xusb_falcon_src
|
||||
254 xusb_fs_src
|
||||
255 xusb_ss_src
|
||||
256 xusb_dev_src
|
||||
257 xusb_dev
|
||||
258 xusb_hs_src
|
||||
259 sclk
|
||||
260 hclk
|
||||
261 pclk
|
||||
262 cclk_g
|
||||
263 cclk_lp
|
||||
264 dfll_ref
|
||||
265 dfll_soc
|
||||
|
||||
Example SoC include file:
|
||||
|
||||
/ {
|
||||
tegra_car: clock {
|
||||
compatible = "nvidia,tegra114-car";
|
||||
reg = <0x60006000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
usb@c5004000 {
|
||||
clocks = <&tegra_car 58>; /* usb2 */
|
||||
};
|
||||
};
|
||||
|
||||
Example board file:
|
||||
|
||||
/ {
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
osc: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
clk_32k: clock@1 {
|
||||
compatible = "fixed-clock";
|
||||
reg = <1>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
&tegra_car {
|
||||
clocks = <&clk_32k> <&osc>;
|
||||
};
|
||||
};
|
||||
@@ -120,8 +120,8 @@ Required properties :
|
||||
90 clk_d
|
||||
91 unassigned
|
||||
92 sus
|
||||
93 cdev1
|
||||
94 cdev2
|
||||
93 cdev2
|
||||
94 cdev1
|
||||
95 unassigned
|
||||
|
||||
96 uart2
|
||||
|
||||
@@ -0,0 +1,44 @@
|
||||
Device Tree Clock bindings for arch-sunxi
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"allwinner,sun4i-osc-clk" - for a gatable oscillator
|
||||
"allwinner,sun4i-pll1-clk" - for the main PLL clock
|
||||
"allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
|
||||
"allwinner,sun4i-axi-clk" - for the AXI clock
|
||||
"allwinner,sun4i-ahb-clk" - for the AHB clock
|
||||
"allwinner,sun4i-apb0-clk" - for the APB0 clock
|
||||
"allwinner,sun4i-apb1-clk" - for the APB1 clock
|
||||
"allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
|
||||
|
||||
Required properties for all clocks:
|
||||
- reg : shall be the control register address for the clock.
|
||||
- clocks : shall be the input parent clock(s) phandle for the clock
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
|
||||
For example:
|
||||
|
||||
osc24M: osc24M@01c20050 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-osc-clk";
|
||||
reg = <0x01c20050 0x4>;
|
||||
clocks = <&osc24M_fixed>;
|
||||
};
|
||||
|
||||
pll1: pll1@01c20000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-pll1-clk";
|
||||
reg = <0x01c20000 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
};
|
||||
|
||||
cpu: cpu@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-cpu-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&osc32k>, <&osc24M>, <&pll1>;
|
||||
};
|
||||
@@ -675,6 +675,7 @@ config ARCH_TEGRA
|
||||
select HAVE_CLK
|
||||
select HAVE_SMP
|
||||
select MIGHT_HAVE_CACHE_L2X0
|
||||
select SOC_BUS
|
||||
select SPARSE_IRQ
|
||||
select USE_OF
|
||||
help
|
||||
|
||||
@@ -12,10 +12,22 @@
|
||||
|
||||
serial@70006300 {
|
||||
status = "okay";
|
||||
clock-frequency = <408000000>;
|
||||
};
|
||||
|
||||
pmc {
|
||||
nvidia,invert-interrupt;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -12,10 +12,22 @@
|
||||
|
||||
serial@70006300 {
|
||||
status = "okay";
|
||||
clock-frequency = <408000000>;
|
||||
};
|
||||
|
||||
pmc {
|
||||
nvidia,invert-interrupt;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -24,10 +24,11 @@
|
||||
0 42 0x04
|
||||
0 121 0x04
|
||||
0 122 0x04>;
|
||||
clocks = <&tegra_car 5>;
|
||||
};
|
||||
|
||||
tegra_car: clock {
|
||||
compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
|
||||
compatible = "nvidia,tegra114-car";
|
||||
reg = <0x60006000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@@ -66,6 +67,7 @@
|
||||
reg-shift = <2>;
|
||||
interrupts = <0 36 0x04>;
|
||||
status = "disabled";
|
||||
clocks = <&tegra_car 6>;
|
||||
};
|
||||
|
||||
serial@70006040 {
|
||||
@@ -74,6 +76,7 @@
|
||||
reg-shift = <2>;
|
||||
interrupts = <0 37 0x04>;
|
||||
status = "disabled";
|
||||
clocks = <&tegra_car 192>;
|
||||
};
|
||||
|
||||
serial@70006200 {
|
||||
@@ -82,6 +85,7 @@
|
||||
reg-shift = <2>;
|
||||
interrupts = <0 46 0x04>;
|
||||
status = "disabled";
|
||||
clocks = <&tegra_car 55>;
|
||||
};
|
||||
|
||||
serial@70006300 {
|
||||
@@ -90,17 +94,21 @@
|
||||
reg-shift = <2>;
|
||||
interrupts = <0 90 0x04>;
|
||||
status = "disabled";
|
||||
clocks = <&tegra_car 65>;
|
||||
};
|
||||
|
||||
rtc {
|
||||
compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
|
||||
reg = <0x7000e000 0x100>;
|
||||
interrupts = <0 2 0x04>;
|
||||
clocks = <&tegra_car 4>;
|
||||
};
|
||||
|
||||
pmc {
|
||||
compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc";
|
||||
compatible = "nvidia,tegra114-pmc";
|
||||
reg = <0x7000e400 0x400>;
|
||||
clocks = <&tegra_car 261>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
};
|
||||
|
||||
iommu {
|
||||
|
||||
@@ -444,7 +444,20 @@
|
||||
};
|
||||
|
||||
sdhci@c8000600 {
|
||||
cd-gpios = <&gpio 23 0>; /* gpio PC7 */
|
||||
cd-gpios = <&gpio 23 1>; /* gpio PC7 */
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
|
||||
@@ -437,7 +437,7 @@
|
||||
|
||||
sdhci@c8000200 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 155 0>; /* gpio PT3 */
|
||||
bus-width = <4>;
|
||||
@@ -445,12 +445,25 @@
|
||||
|
||||
sdhci@c8000600 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 58 0>; /* gpio PH2 */
|
||||
cd-gpios = <&gpio 58 1>; /* gpio PH2 */
|
||||
wp-gpios = <&gpio 59 0>; /* gpio PH3 */
|
||||
power-gpios = <&gpio 70 0>; /* gpio PI6 */
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
kbc {
|
||||
status = "okay";
|
||||
nvidia,debounce-delay-ms = <2>;
|
||||
|
||||
@@ -436,7 +436,7 @@
|
||||
|
||||
sdhci@c8000000 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 173 0>; /* gpio PV5 */
|
||||
cd-gpios = <&gpio 173 1>; /* gpio PV5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 169 0>; /* gpio PV1 */
|
||||
bus-width = <4>;
|
||||
@@ -447,6 +447,19 @@
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
|
||||
@@ -584,7 +584,7 @@
|
||||
|
||||
sdhci@c8000400 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 70 0>; /* gpio PI6 */
|
||||
bus-width = <4>;
|
||||
@@ -595,6 +595,19 @@
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
|
||||
@@ -465,12 +465,25 @@
|
||||
};
|
||||
|
||||
sdhci@c8000600 {
|
||||
cd-gpios = <&gpio 58 0>; /* gpio PH2 */
|
||||
cd-gpios = <&gpio 58 1>; /* gpio PH2 */
|
||||
wp-gpios = <&gpio 59 0>; /* gpio PH3 */
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
|
||||
|
||||
@@ -325,11 +325,24 @@
|
||||
|
||||
sdhci@c8000600 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 121 0>; /* gpio PP1 */
|
||||
cd-gpios = <&gpio 121 1>; /* gpio PP1 */
|
||||
wp-gpios = <&gpio 122 0>; /* gpio PP2 */
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
poweroff {
|
||||
compatible = "gpio-poweroff";
|
||||
gpios = <&gpio 191 1>; /* gpio PX7, active low */
|
||||
|
||||
@@ -520,7 +520,7 @@
|
||||
|
||||
sdhci@c8000400 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 70 0>; /* gpio PI6 */
|
||||
bus-width = <4>;
|
||||
@@ -531,6 +531,19 @@
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
||||
@@ -510,6 +510,7 @@
|
||||
|
||||
sdhci@c8000400 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 173 0>; /* gpio PV5 */
|
||||
bus-width = <8>;
|
||||
};
|
||||
@@ -519,6 +520,19 @@
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
kbc {
|
||||
status = "okay";
|
||||
nvidia,debounce-delay-ms = <20>;
|
||||
|
||||
@@ -145,6 +145,7 @@
|
||||
0 1 0x04
|
||||
0 41 0x04
|
||||
0 42 0x04>;
|
||||
clocks = <&tegra_car 5>;
|
||||
};
|
||||
|
||||
tegra_car: clock {
|
||||
@@ -304,6 +305,7 @@
|
||||
compatible = "nvidia,tegra20-rtc";
|
||||
reg = <0x7000e000 0x100>;
|
||||
interrupts = <0 2 0x04>;
|
||||
clocks = <&tegra_car 4>;
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
@@ -416,6 +418,8 @@
|
||||
pmc {
|
||||
compatible = "nvidia,tegra20-pmc";
|
||||
reg = <0x7000e400 0x400>;
|
||||
clocks = <&tegra_car 110>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
};
|
||||
|
||||
memory-controller@7000f000 {
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user