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ASoC: omap-mcpdm: Replace legacy driver
Reasons for the replacement: The current driver for McPDM was developed to support the legacy mode only. In preparation for the ABE support the current driver stack need the be replaced. The new driver is much simpler, easier to extend, and it also fixes some of the issues with the old stack. Main changes: - single file for omap-mcpdm (mcpdm.c/h removed) - Define names for registers, bits cleaned up, prefixed - Full-duplex audio operation (arecord | aplay) has been fixed - Less code McPDM need to be turned off after all streams has been stopped. This might cause pop noise on the output, if the codec's DAC is still powered at this time. Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com> Signed-off-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Sebastien Guiriec <s-guiriec@ti.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Misael Lopez Cruz
committed by
Peter Ujfalusi
Peter Ujfalusi
parent
3a98cd6b2b
commit
f5f9d7bf6e
@@ -1,7 +1,7 @@
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# OMAP Platform Support
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snd-soc-omap-objs := omap-pcm.o
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snd-soc-omap-mcbsp-objs := omap-mcbsp.o
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snd-soc-omap-mcpdm-objs := omap-mcpdm.o mcpdm.o
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snd-soc-omap-mcpdm-objs := omap-mcpdm.o
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snd-soc-omap-hdmi-objs := omap-hdmi.o
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obj-$(CONFIG_SND_OMAP_SOC) += snd-soc-omap.o
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@@ -1,474 +0,0 @@
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/*
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* mcpdm.c -- McPDM interface driver
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*
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* Author: Jorge Eduardo Candelaria <x0107209@ti.com>
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* Copyright (C) 2009 - Texas Instruments, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/wait.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/err.h>
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#include <linux/pm_runtime.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include "mcpdm.h"
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static struct omap_mcpdm *mcpdm;
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static inline void omap_mcpdm_write(u16 reg, u32 val)
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{
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__raw_writel(val, mcpdm->io_base + reg);
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}
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static inline int omap_mcpdm_read(u16 reg)
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{
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return __raw_readl(mcpdm->io_base + reg);
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}
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static void omap_mcpdm_reg_dump(void)
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{
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dev_dbg(mcpdm->dev, "***********************\n");
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dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
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omap_mcpdm_read(MCPDM_IRQSTATUS_RAW));
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dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
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omap_mcpdm_read(MCPDM_IRQSTATUS));
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dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
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omap_mcpdm_read(MCPDM_IRQENABLE_SET));
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dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
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omap_mcpdm_read(MCPDM_IRQENABLE_CLR));
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dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
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omap_mcpdm_read(MCPDM_IRQWAKE_EN));
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dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
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omap_mcpdm_read(MCPDM_DMAENABLE_SET));
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dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
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omap_mcpdm_read(MCPDM_DMAENABLE_CLR));
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dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
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omap_mcpdm_read(MCPDM_DMAWAKEEN));
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dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
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omap_mcpdm_read(MCPDM_CTRL));
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dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
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omap_mcpdm_read(MCPDM_DN_DATA));
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dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
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omap_mcpdm_read(MCPDM_UP_DATA));
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dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
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omap_mcpdm_read(MCPDM_FIFO_CTRL_DN));
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dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
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omap_mcpdm_read(MCPDM_FIFO_CTRL_UP));
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dev_dbg(mcpdm->dev, "DN_OFFSET: 0x%04x\n",
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omap_mcpdm_read(MCPDM_DN_OFFSET));
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dev_dbg(mcpdm->dev, "***********************\n");
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}
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/*
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* Takes the McPDM module in and out of reset state.
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* Uplink and downlink can be reset individually.
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*/
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static void omap_mcpdm_reset_capture(int reset)
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{
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int ctrl = omap_mcpdm_read(MCPDM_CTRL);
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if (reset)
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ctrl |= SW_UP_RST;
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else
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ctrl &= ~SW_UP_RST;
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omap_mcpdm_write(MCPDM_CTRL, ctrl);
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}
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static void omap_mcpdm_reset_playback(int reset)
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{
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int ctrl = omap_mcpdm_read(MCPDM_CTRL);
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if (reset)
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ctrl |= SW_DN_RST;
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else
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ctrl &= ~SW_DN_RST;
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omap_mcpdm_write(MCPDM_CTRL, ctrl);
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}
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/*
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* Enables the transfer through the PDM interface to/from the Phoenix
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* codec by enabling the corresponding UP or DN channels.
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*/
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void omap_mcpdm_start(int stream)
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{
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int ctrl = omap_mcpdm_read(MCPDM_CTRL);
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if (stream)
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ctrl |= mcpdm->up_channels;
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else
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ctrl |= mcpdm->dn_channels;
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omap_mcpdm_write(MCPDM_CTRL, ctrl);
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}
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/*
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* Disables the transfer through the PDM interface to/from the Phoenix
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* codec by disabling the corresponding UP or DN channels.
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*/
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void omap_mcpdm_stop(int stream)
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{
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int ctrl = omap_mcpdm_read(MCPDM_CTRL);
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if (stream)
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ctrl &= ~mcpdm->up_channels;
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else
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ctrl &= ~mcpdm->dn_channels;
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omap_mcpdm_write(MCPDM_CTRL, ctrl);
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}
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/*
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* Configures McPDM uplink for audio recording.
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* This function should be called before omap_mcpdm_start.
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*/
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int omap_mcpdm_capture_open(struct omap_mcpdm_link *uplink)
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{
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int irq_mask = 0;
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int ctrl;
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if (!uplink)
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return -EINVAL;
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mcpdm->uplink = uplink;
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/* Enable irq request generation */
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irq_mask |= uplink->irq_mask & MCPDM_UPLINK_IRQ_MASK;
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omap_mcpdm_write(MCPDM_IRQENABLE_SET, irq_mask);
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/* Configure uplink threshold */
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if (uplink->threshold > UP_THRES_MAX)
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uplink->threshold = UP_THRES_MAX;
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omap_mcpdm_write(MCPDM_FIFO_CTRL_UP, uplink->threshold);
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/* Configure DMA controller */
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omap_mcpdm_write(MCPDM_DMAENABLE_SET, DMA_UP_ENABLE);
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/* Set pdm out format */
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ctrl = omap_mcpdm_read(MCPDM_CTRL);
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ctrl &= ~PDMOUTFORMAT;
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ctrl |= uplink->format & PDMOUTFORMAT;
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/* Uplink channels */
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mcpdm->up_channels = uplink->channels & (PDM_UP_MASK | PDM_STATUS_MASK);
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omap_mcpdm_write(MCPDM_CTRL, ctrl);
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return 0;
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}
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/*
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* Configures McPDM downlink for audio playback.
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* This function should be called before omap_mcpdm_start.
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*/
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int omap_mcpdm_playback_open(struct omap_mcpdm_link *downlink)
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{
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int irq_mask = 0;
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int ctrl;
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if (!downlink)
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return -EINVAL;
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mcpdm->downlink = downlink;
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/* Enable irq request generation */
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irq_mask |= downlink->irq_mask & MCPDM_DOWNLINK_IRQ_MASK;
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omap_mcpdm_write(MCPDM_IRQENABLE_SET, irq_mask);
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/* Configure uplink threshold */
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if (downlink->threshold > DN_THRES_MAX)
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downlink->threshold = DN_THRES_MAX;
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omap_mcpdm_write(MCPDM_FIFO_CTRL_DN, downlink->threshold);
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/* Enable DMA request generation */
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omap_mcpdm_write(MCPDM_DMAENABLE_SET, DMA_DN_ENABLE);
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/* Set pdm out format */
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ctrl = omap_mcpdm_read(MCPDM_CTRL);
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ctrl &= ~PDMOUTFORMAT;
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ctrl |= downlink->format & PDMOUTFORMAT;
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/* Downlink channels */
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mcpdm->dn_channels = downlink->channels & (PDM_DN_MASK | PDM_CMD_MASK);
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omap_mcpdm_write(MCPDM_CTRL, ctrl);
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return 0;
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}
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/*
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* Cleans McPDM uplink configuration.
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* This function should be called when the stream is closed.
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*/
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int omap_mcpdm_capture_close(struct omap_mcpdm_link *uplink)
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{
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int irq_mask = 0;
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if (!uplink)
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return -EINVAL;
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/* Disable irq request generation */
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irq_mask |= uplink->irq_mask & MCPDM_UPLINK_IRQ_MASK;
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omap_mcpdm_write(MCPDM_IRQENABLE_CLR, irq_mask);
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/* Disable DMA request generation */
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omap_mcpdm_write(MCPDM_DMAENABLE_CLR, DMA_UP_ENABLE);
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/* Clear Downlink channels */
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mcpdm->up_channels = 0;
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mcpdm->uplink = NULL;
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return 0;
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}
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/*
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* Cleans McPDM downlink configuration.
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* This function should be called when the stream is closed.
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*/
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int omap_mcpdm_playback_close(struct omap_mcpdm_link *downlink)
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{
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int irq_mask = 0;
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if (!downlink)
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return -EINVAL;
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/* Disable irq request generation */
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irq_mask |= downlink->irq_mask & MCPDM_DOWNLINK_IRQ_MASK;
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omap_mcpdm_write(MCPDM_IRQENABLE_CLR, irq_mask);
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/* Disable DMA request generation */
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omap_mcpdm_write(MCPDM_DMAENABLE_CLR, DMA_DN_ENABLE);
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/* clear Downlink channels */
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mcpdm->dn_channels = 0;
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mcpdm->downlink = NULL;
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return 0;
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}
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static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
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{
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struct omap_mcpdm *mcpdm_irq = dev_id;
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int irq_status;
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irq_status = omap_mcpdm_read(MCPDM_IRQSTATUS);
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/* Acknowledge irq event */
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omap_mcpdm_write(MCPDM_IRQSTATUS, irq_status);
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if (irq & MCPDM_DN_IRQ_FULL) {
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dev_err(mcpdm_irq->dev, "DN FIFO error %x\n", irq_status);
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omap_mcpdm_reset_playback(1);
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omap_mcpdm_playback_open(mcpdm_irq->downlink);
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omap_mcpdm_reset_playback(0);
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}
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if (irq & MCPDM_DN_IRQ_EMPTY) {
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dev_err(mcpdm_irq->dev, "DN FIFO error %x\n", irq_status);
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omap_mcpdm_reset_playback(1);
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omap_mcpdm_playback_open(mcpdm_irq->downlink);
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omap_mcpdm_reset_playback(0);
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}
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if (irq & MCPDM_DN_IRQ) {
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dev_dbg(mcpdm_irq->dev, "DN write request\n");
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}
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if (irq & MCPDM_UP_IRQ_FULL) {
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dev_err(mcpdm_irq->dev, "UP FIFO error %x\n", irq_status);
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omap_mcpdm_reset_capture(1);
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omap_mcpdm_capture_open(mcpdm_irq->uplink);
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omap_mcpdm_reset_capture(0);
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}
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if (irq & MCPDM_UP_IRQ_EMPTY) {
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dev_err(mcpdm_irq->dev, "UP FIFO error %x\n", irq_status);
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omap_mcpdm_reset_capture(1);
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omap_mcpdm_capture_open(mcpdm_irq->uplink);
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omap_mcpdm_reset_capture(0);
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}
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if (irq & MCPDM_UP_IRQ) {
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dev_dbg(mcpdm_irq->dev, "UP write request\n");
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}
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return IRQ_HANDLED;
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}
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int omap_mcpdm_request(void)
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{
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int ret;
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pm_runtime_get_sync(mcpdm->dev);
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spin_lock(&mcpdm->lock);
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if (!mcpdm->free) {
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dev_err(mcpdm->dev, "McPDM interface is in use\n");
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spin_unlock(&mcpdm->lock);
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ret = -EBUSY;
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goto err;
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}
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mcpdm->free = 0;
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spin_unlock(&mcpdm->lock);
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/* Disable lines while request is ongoing */
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omap_mcpdm_write(MCPDM_CTRL, 0x00);
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ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
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0, "McPDM", (void *)mcpdm);
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if (ret) {
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dev_err(mcpdm->dev, "Request for McPDM IRQ failed\n");
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goto err;
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}
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return 0;
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err:
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mcpdm->free = 1;
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pm_runtime_put_sync(mcpdm->dev);
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return ret;
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}
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void omap_mcpdm_free(void)
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{
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spin_lock(&mcpdm->lock);
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if (mcpdm->free) {
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dev_err(mcpdm->dev, "McPDM interface is already free\n");
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spin_unlock(&mcpdm->lock);
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return;
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}
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mcpdm->free = 1;
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spin_unlock(&mcpdm->lock);
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pm_runtime_put_sync(mcpdm->dev);
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free_irq(mcpdm->irq, (void *)mcpdm);
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}
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/* Enable/disable DC offset cancelation for the analog
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* headset path (PDM channels 1 and 2).
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*/
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int omap_mcpdm_set_offset(int offset1, int offset2)
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{
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int offset;
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if ((offset1 > DN_OFST_MAX) || (offset2 > DN_OFST_MAX))
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return -EINVAL;
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offset = (offset1 << DN_OFST_RX1) | (offset2 << DN_OFST_RX2);
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/* offset cancellation for channel 1 */
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if (offset1)
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offset |= DN_OFST_RX1_EN;
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else
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offset &= ~DN_OFST_RX1_EN;
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/* offset cancellation for channel 2 */
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if (offset2)
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offset |= DN_OFST_RX2_EN;
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else
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offset &= ~DN_OFST_RX2_EN;
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omap_mcpdm_write(MCPDM_DN_OFFSET, offset);
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return 0;
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}
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int __devinit omap_mcpdm_probe(struct platform_device *pdev)
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{
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struct resource *res;
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int ret = 0;
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mcpdm = kzalloc(sizeof(struct omap_mcpdm), GFP_KERNEL);
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if (!mcpdm) {
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ret = -ENOMEM;
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goto exit;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (res == NULL) {
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dev_err(&pdev->dev, "no resource\n");
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goto err_resource;
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}
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spin_lock_init(&mcpdm->lock);
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mcpdm->free = 1;
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if (!request_mem_region(res->start, resource_size(res), "McPDM")) {
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ret = -EBUSY;
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goto err_resource;
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}
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mcpdm->io_base = ioremap(res->start, resource_size(res));
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if (!mcpdm->io_base) {
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ret = -ENOMEM;
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goto err_remap;
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}
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mcpdm->irq = platform_get_irq(pdev, 0);
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mcpdm->dev = &pdev->dev;
|
||||
platform_set_drvdata(pdev, mcpdm);
|
||||
|
||||
pm_runtime_enable(mcpdm->dev);
|
||||
|
||||
return 0;
|
||||
|
||||
err_remap:
|
||||
release_mem_region(res->start, resource_size(res));
|
||||
err_resource:
|
||||
kfree(mcpdm);
|
||||
exit:
|
||||
return ret;
|
||||
}
|
||||
|
||||
int __devexit omap_mcpdm_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct omap_mcpdm *mcpdm_ptr = platform_get_drvdata(pdev);
|
||||
struct resource *res;
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
|
||||
pm_runtime_disable(mcpdm_ptr->dev);
|
||||
|
||||
iounmap(mcpdm_ptr->io_base);
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
release_mem_region(res->start, resource_size(res));
|
||||
|
||||
mcpdm_ptr->free = 0;
|
||||
mcpdm_ptr->dev = NULL;
|
||||
|
||||
kfree(mcpdm_ptr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1,152 +0,0 @@
|
||||
/*
|
||||
* mcpdm.h -- Defines for McPDM driver
|
||||
*
|
||||
* Author: Jorge Eduardo Candelaria <x0107209@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
|
||||
* 02110-1301 USA
|
||||
*
|
||||
*/
|
||||
|
||||
/* McPDM registers */
|
||||
|
||||
#define MCPDM_REVISION 0x00
|
||||
#define MCPDM_SYSCONFIG 0x10
|
||||
#define MCPDM_IRQSTATUS_RAW 0x24
|
||||
#define MCPDM_IRQSTATUS 0x28
|
||||
#define MCPDM_IRQENABLE_SET 0x2C
|
||||
#define MCPDM_IRQENABLE_CLR 0x30
|
||||
#define MCPDM_IRQWAKE_EN 0x34
|
||||
#define MCPDM_DMAENABLE_SET 0x38
|
||||
#define MCPDM_DMAENABLE_CLR 0x3C
|
||||
#define MCPDM_DMAWAKEEN 0x40
|
||||
#define MCPDM_CTRL 0x44
|
||||
#define MCPDM_DN_DATA 0x48
|
||||
#define MCPDM_UP_DATA 0x4C
|
||||
#define MCPDM_FIFO_CTRL_DN 0x50
|
||||
#define MCPDM_FIFO_CTRL_UP 0x54
|
||||
#define MCPDM_DN_OFFSET 0x58
|
||||
|
||||
/*
|
||||
* MCPDM_IRQ bit fields
|
||||
* IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR
|
||||
*/
|
||||
|
||||
#define MCPDM_DN_IRQ (1 << 0)
|
||||
#define MCPDM_DN_IRQ_EMPTY (1 << 1)
|
||||
#define MCPDM_DN_IRQ_ALMST_EMPTY (1 << 2)
|
||||
#define MCPDM_DN_IRQ_FULL (1 << 3)
|
||||
|
||||
#define MCPDM_UP_IRQ (1 << 8)
|
||||
#define MCPDM_UP_IRQ_EMPTY (1 << 9)
|
||||
#define MCPDM_UP_IRQ_ALMST_FULL (1 << 10)
|
||||
#define MCPDM_UP_IRQ_FULL (1 << 11)
|
||||
|
||||
#define MCPDM_DOWNLINK_IRQ_MASK 0x00F
|
||||
#define MCPDM_UPLINK_IRQ_MASK 0xF00
|
||||
|
||||
/*
|
||||
* MCPDM_DMAENABLE bit fields
|
||||
*/
|
||||
|
||||
#define DMA_DN_ENABLE 0x1
|
||||
#define DMA_UP_ENABLE 0x2
|
||||
|
||||
/*
|
||||
* MCPDM_CTRL bit fields
|
||||
*/
|
||||
|
||||
#define PDM_UP1_EN 0x0001
|
||||
#define PDM_UP2_EN 0x0002
|
||||
#define PDM_UP3_EN 0x0004
|
||||
#define PDM_DN1_EN 0x0008
|
||||
#define PDM_DN2_EN 0x0010
|
||||
#define PDM_DN3_EN 0x0020
|
||||
#define PDM_DN4_EN 0x0040
|
||||
#define PDM_DN5_EN 0x0080
|
||||
#define PDMOUTFORMAT 0x0100
|
||||
#define CMD_INT 0x0200
|
||||
#define STATUS_INT 0x0400
|
||||
#define SW_UP_RST 0x0800
|
||||
#define SW_DN_RST 0x1000
|
||||
#define PDM_UP_MASK 0x007
|
||||
#define PDM_DN_MASK 0x0F8
|
||||
#define PDM_CMD_MASK 0x200
|
||||
#define PDM_STATUS_MASK 0x400
|
||||
|
||||
|
||||
#define PDMOUTFORMAT_LJUST (0 << 8)
|
||||
#define PDMOUTFORMAT_RJUST (1 << 8)
|
||||
|
||||
/*
|
||||
* MCPDM_FIFO_CTRL bit fields
|
||||
*/
|
||||
|
||||
#define UP_THRES_MAX 0xF
|
||||
#define DN_THRES_MAX 0xF
|
||||
|
||||
/*
|
||||
* MCPDM_DN_OFFSET bit fields
|
||||
*/
|
||||
|
||||
#define DN_OFST_RX1_EN 0x0001
|
||||
#define DN_OFST_RX2_EN 0x0100
|
||||
|
||||
#define DN_OFST_RX1 1
|
||||
#define DN_OFST_RX2 9
|
||||
#define DN_OFST_MAX 0x1F
|
||||
|
||||
#define MCPDM_UPLINK 1
|
||||
#define MCPDM_DOWNLINK 2
|
||||
|
||||
struct omap_mcpdm_link {
|
||||
int irq_mask;
|
||||
int threshold;
|
||||
int format;
|
||||
int channels;
|
||||
};
|
||||
|
||||
struct omap_mcpdm_platform_data {
|
||||
unsigned long phys_base;
|
||||
u16 irq;
|
||||
};
|
||||
|
||||
struct omap_mcpdm {
|
||||
struct device *dev;
|
||||
unsigned long phys_base;
|
||||
void __iomem *io_base;
|
||||
u8 free;
|
||||
int irq;
|
||||
|
||||
spinlock_t lock;
|
||||
struct omap_mcpdm_platform_data *pdata;
|
||||
struct omap_mcpdm_link *downlink;
|
||||
struct omap_mcpdm_link *uplink;
|
||||
struct completion irq_completion;
|
||||
|
||||
int dn_channels;
|
||||
int up_channels;
|
||||
};
|
||||
|
||||
extern void omap_mcpdm_start(int stream);
|
||||
extern void omap_mcpdm_stop(int stream);
|
||||
extern int omap_mcpdm_capture_open(struct omap_mcpdm_link *uplink);
|
||||
extern int omap_mcpdm_playback_open(struct omap_mcpdm_link *downlink);
|
||||
extern int omap_mcpdm_capture_close(struct omap_mcpdm_link *uplink);
|
||||
extern int omap_mcpdm_playback_close(struct omap_mcpdm_link *downlink);
|
||||
extern int omap_mcpdm_request(void);
|
||||
extern void omap_mcpdm_free(void);
|
||||
extern int omap_mcpdm_set_offset(int offset1, int offset2);
|
||||
int __devinit omap_mcpdm_probe(struct platform_device *pdev);
|
||||
int __devexit omap_mcpdm_remove(struct platform_device *pdev);
|
||||
+337
-106
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,95 @@
|
||||
/*
|
||||
* omap-mcpdm.h
|
||||
*
|
||||
* Copyright (C) 2009 - 2011 Texas Instruments
|
||||
*
|
||||
* Contact: Misael Lopez Cruz <misael.lopez@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
|
||||
* 02110-1301 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __OMAP_MCPDM_H__
|
||||
#define __OMAP_MCPDM_H__
|
||||
|
||||
#define MCPDM_REG_REVISION 0x00
|
||||
#define MCPDM_REG_SYSCONFIG 0x10
|
||||
#define MCPDM_REG_IRQSTATUS_RAW 0x24
|
||||
#define MCPDM_REG_IRQSTATUS 0x28
|
||||
#define MCPDM_REG_IRQENABLE_SET 0x2C
|
||||
#define MCPDM_REG_IRQENABLE_CLR 0x30
|
||||
#define MCPDM_REG_IRQWAKE_EN 0x34
|
||||
#define MCPDM_REG_DMAENABLE_SET 0x38
|
||||
#define MCPDM_REG_DMAENABLE_CLR 0x3C
|
||||
#define MCPDM_REG_DMAWAKEEN 0x40
|
||||
#define MCPDM_REG_CTRL 0x44
|
||||
#define MCPDM_REG_DN_DATA 0x48
|
||||
#define MCPDM_REG_UP_DATA 0x4C
|
||||
#define MCPDM_REG_FIFO_CTRL_DN 0x50
|
||||
#define MCPDM_REG_FIFO_CTRL_UP 0x54
|
||||
#define MCPDM_REG_DN_OFFSET 0x58
|
||||
|
||||
/*
|
||||
* MCPDM_IRQ bit fields
|
||||
* IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR
|
||||
*/
|
||||
|
||||
#define MCPDM_DN_IRQ (1 << 0)
|
||||
#define MCPDM_DN_IRQ_EMPTY (1 << 1)
|
||||
#define MCPDM_DN_IRQ_ALMST_EMPTY (1 << 2)
|
||||
#define MCPDM_DN_IRQ_FULL (1 << 3)
|
||||
|
||||
#define MCPDM_UP_IRQ (1 << 8)
|
||||
#define MCPDM_UP_IRQ_EMPTY (1 << 9)
|
||||
#define MCPDM_UP_IRQ_ALMST_FULL (1 << 10)
|
||||
#define MCPDM_UP_IRQ_FULL (1 << 11)
|
||||
|
||||
#define MCPDM_DOWNLINK_IRQ_MASK 0x00F
|
||||
#define MCPDM_UPLINK_IRQ_MASK 0xF00
|
||||
|
||||
/*
|
||||
* MCPDM_DMAENABLE bit fields
|
||||
*/
|
||||
|
||||
#define MCPDM_DMA_DN_ENABLE (1 << 0)
|
||||
#define MCPDM_DMA_UP_ENABLE (1 << 1)
|
||||
|
||||
/*
|
||||
* MCPDM_CTRL bit fields
|
||||
*/
|
||||
|
||||
#define MCPDM_PDM_UPLINK_EN(x) (1 << (x - 1)) /* ch1 is at bit 0 */
|
||||
#define MCPDM_PDM_DOWNLINK_EN(x) (1 << (x + 2)) /* ch1 is at bit 3 */
|
||||
#define MCPDM_PDMOUTFORMAT (1 << 8)
|
||||
#define MCPDM_CMD_INT (1 << 9)
|
||||
#define MCPDM_STATUS_INT (1 << 10)
|
||||
#define MCPDM_SW_UP_RST (1 << 11)
|
||||
#define MCPDM_SW_DN_RST (1 << 12)
|
||||
#define MCPDM_WD_EN (1 << 14)
|
||||
#define MCPDM_PDM_UP_MASK 0x7
|
||||
#define MCPDM_PDM_DN_MASK (0x1f << 3)
|
||||
|
||||
|
||||
#define MCPDM_PDMOUTFORMAT_LJUST (0 << 8)
|
||||
#define MCPDM_PDMOUTFORMAT_RJUST (1 << 8)
|
||||
|
||||
/*
|
||||
* MCPDM_FIFO_CTRL bit fields
|
||||
*/
|
||||
|
||||
#define MCPDM_UP_THRES_MAX 0xF
|
||||
#define MCPDM_DN_THRES_MAX 0xF
|
||||
|
||||
#endif /* End of __OMAP_MCPDM_H__ */
|
||||
@@ -32,7 +32,7 @@
|
||||
#include <plat/hardware.h>
|
||||
#include <plat/mux.h>
|
||||
|
||||
#include "mcpdm.h"
|
||||
#include "omap-mcpdm.h"
|
||||
#include "omap-pcm.h"
|
||||
#include "../codecs/twl6040.h"
|
||||
|
||||
|
||||
Reference in New Issue
Block a user