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Merge tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups from Olof Johansson:
"This is the branch where we usually queue up cleanup efforts, moving
drivers out of the architecture directory, header file restructuring,
etc. Sometimes they tangle with new development so it's hard to keep
it strictly to cleanups.
Some of the things included in this branch are:
* Atmel SAMA5 conversion to common clock
* Reset framework conversion for tegra platforms
- Some of this depends on tegra clock driver reworks that are shared
with Mike Turquette's clk tree.
* Tegra DMA refactoring, which are shared branches with the DMA tree.
* Removal of some header files on exynos to prepare for
multiplatform"
* tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (169 commits)
ARM: mvebu: move Armada 370/XP specific definitions to armada-370-xp.h
ARM: mvebu: remove prototypes of non-existing functions from common.h
ARM: mvebu: move ARMADA_XP_MAX_CPUS to armada-370-xp.h
serial: sh-sci: Rework baud rate calculation
serial: sh-sci: Compute overrun_bit without using baud rate algo
serial: sh-sci: Remove unused GPIO request code
serial: sh-sci: Move overrun_bit and error_mask fields out of pdata
serial: sh-sci: Support resources passed through platform resources
serial: sh-sci: Don't check IRQ in verify port operation
serial: sh-sci: Set the UPF_FIXED_PORT flag
serial: sh-sci: Remove duplicate interrupt check in verify port op
serial: sh-sci: Simplify baud rate calculation algorithms
serial: sh-sci: Remove baud rate calculation algorithm 5
serial: sh-sci: Sort headers alphabetically
ARM: EXYNOS: Kill exynos_pm_late_initcall()
ARM: EXYNOS: Consolidate selection of PM_GENERIC_DOMAINS for Exynos4
ARM: at91: switch Calao QIL-A9260 board to DT
clk: at91: fix pmc_clk_ids data type attriubte
PM / devfreq: use inclusion <mach/map.h> instead of <plat/map-s5p.h>
ARM: EXYNOS: remove <mach/regs-clock.h> for exynos
...
This commit is contained in:
Linus Torvalds
@@ -9,6 +9,7 @@ Required properties:
|
||||
- compatible : Should contain "nvidia,tegra<chip>-pmc".
|
||||
- reg : Offset and length of the register set for the device
|
||||
- clocks : Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names : Must include the following entries:
|
||||
"pclk" (The Tegra clock of that name),
|
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"clk32k_in" (The 32KHz clock input to Tegra).
|
||||
|
||||
@@ -0,0 +1,339 @@
|
||||
Device Tree Clock bindings for arch-at91
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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||||
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
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"atmel,at91rm9200-pmc" or
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"atmel,at91sam9g45-pmc" or
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"atmel,at91sam9n12-pmc" or
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"atmel,at91sam9x5-pmc" or
|
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"atmel,sama5d3-pmc":
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at91 PMC (Power Management Controller)
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All at91 specific clocks (clocks defined below) must be child
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||||
node of the PMC node.
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||||
|
||||
"atmel,at91rm9200-clk-main":
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||||
at91 main oscillator
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||||
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||||
"atmel,at91rm9200-clk-master" or
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"atmel,at91sam9x5-clk-master":
|
||||
at91 master clock
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||||
|
||||
"atmel,at91sam9x5-clk-peripheral" or
|
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"atmel,at91rm9200-clk-peripheral":
|
||||
at91 peripheral clocks
|
||||
|
||||
"atmel,at91rm9200-clk-pll" or
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"atmel,at91sam9g45-clk-pll" or
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"atmel,at91sam9g20-clk-pllb" or
|
||||
"atmel,sama5d3-clk-pll":
|
||||
at91 pll clocks
|
||||
|
||||
"atmel,at91sam9x5-clk-plldiv":
|
||||
at91 plla divisor
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||||
|
||||
"atmel,at91rm9200-clk-programmable" or
|
||||
"atmel,at91sam9g45-clk-programmable" or
|
||||
"atmel,at91sam9x5-clk-programmable":
|
||||
at91 programmable clocks
|
||||
|
||||
"atmel,at91sam9x5-clk-smd":
|
||||
at91 SMD (Soft Modem) clock
|
||||
|
||||
"atmel,at91rm9200-clk-system":
|
||||
at91 system clocks
|
||||
|
||||
"atmel,at91rm9200-clk-usb" or
|
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"atmel,at91sam9x5-clk-usb" or
|
||||
"atmel,at91sam9n12-clk-usb":
|
||||
at91 usb clock
|
||||
|
||||
"atmel,at91sam9x5-clk-utmi":
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||||
at91 utmi clock
|
||||
|
||||
Required properties for PMC node:
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- reg : defines the IO memory reserved for the PMC.
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- #size-cells : shall be 0 (reg is used to encode clk id).
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- #address-cells : shall be 1 (reg is used to encode clk id).
|
||||
- interrupts : shall be set to PMC interrupt line.
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- interrupt-controller : tell that the PMC is an interrupt controller.
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||||
- #interrupt-cells : must be set to 1. The first cell encodes the interrupt id,
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||||
and reflect the bit position in the PMC_ER/DR/SR registers.
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You can use the dt macros defined in dt-bindings/clk/at91.h.
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0 (AT91_PMC_MOSCS) -> main oscillator ready
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1 (AT91_PMC_LOCKA) -> PLL A ready
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2 (AT91_PMC_LOCKB) -> PLL B ready
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3 (AT91_PMC_MCKRDY) -> master clock ready
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6 (AT91_PMC_LOCKU) -> UTMI PLL clock ready
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8 .. 15 (AT91_PMC_PCKRDY(id)) -> programmable clock ready
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16 (AT91_PMC_MOSCSELS) -> main oscillator selected
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17 (AT91_PMC_MOSCRCS) -> RC main oscillator stabilized
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18 (AT91_PMC_CFDEV) -> clock failure detected
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||||
|
||||
For example:
|
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pmc: pmc@fffffc00 {
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compatible = "atmel,sama5d3-pmc";
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interrupts = <1 4 7>;
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interrupt-controller;
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#interrupt-cells = <2>;
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#size-cells = <0>;
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#address-cells = <1>;
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/* put at91 clocks here */
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||||
};
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Required properties for main clock:
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- interrupt-parent : must reference the PMC node.
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- interrupts : shall be set to "<0>".
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- #clock-cells : from common clock binding; shall be set to 0.
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- clocks (optional if clock-frequency is provided) : shall be the slow clock
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phandle. This clock is used to calculate the main clock rate if
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"clock-frequency" is not provided.
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- clock-frequency : the main oscillator frequency.Prefer the use of
|
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"clock-frequency" over automatic clock rate calculation.
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||||
|
||||
For example:
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main: mainck {
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compatible = "atmel,at91rm9200-clk-main";
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interrupt-parent = <&pmc>;
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interrupts = <0>;
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#clock-cells = <0>;
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clocks = <&ck32k>;
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clock-frequency = <18432000>;
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};
|
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||||
Required properties for master clock:
|
||||
- interrupt-parent : must reference the PMC node.
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- interrupts : shall be set to "<3>".
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- #clock-cells : from common clock binding; shall be set to 0.
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||||
- clocks : shall be the master clock sources (see atmel datasheet) phandles.
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||||
e.g. "<&ck32k>, <&main>, <&plla>, <&pllb>".
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- atmel,clk-output-range : minimum and maximum clock frequency (two u32
|
||||
fields).
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e.g. output = <0 133000000>; <=> 0 to 133MHz.
|
||||
- atmel,clk-divisors : master clock divisors table (four u32 fields).
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||||
0 <=> reserved value.
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||||
e.g. divisors = <1 2 4 6>;
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||||
- atmel,master-clk-have-div3-pres : some SoC use the reserved value 7 in the
|
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PRES field as CLOCK_DIV3 (e.g sam9x5).
|
||||
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||||
For example:
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mck: mck {
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compatible = "atmel,at91rm9200-clk-master";
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interrupt-parent = <&pmc>;
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interrupts = <3>;
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#clock-cells = <0>;
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atmel,clk-output-range = <0 133000000>;
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atmel,clk-divisors = <1 2 4 0>;
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};
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Required properties for peripheral clocks:
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||||
- #size-cells : shall be 0 (reg is used to encode clk id).
|
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- #address-cells : shall be 1 (reg is used to encode clk id).
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- clocks : shall be the master clock phandle.
|
||||
e.g. clocks = <&mck>;
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- name: device tree node describing a specific system clock.
|
||||
* #clock-cells : from common clock binding; shall be set to 0.
|
||||
* reg: peripheral id. See Atmel's datasheets to get a full
|
||||
list of peripheral ids.
|
||||
* atmel,clk-output-range : minimum and maximum clock frequency
|
||||
(two u32 fields). Only valid on at91sam9x5-clk-peripheral
|
||||
compatible IPs.
|
||||
|
||||
For example:
|
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periph: periphck {
|
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compatible = "atmel,at91sam9x5-clk-peripheral";
|
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#size-cells = <0>;
|
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#address-cells = <1>;
|
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clocks = <&mck>;
|
||||
|
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ssc0_clk {
|
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#clock-cells = <0>;
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reg = <2>;
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atmel,clk-output-range = <0 133000000>;
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};
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usart0_clk {
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#clock-cells = <0>;
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reg = <3>;
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atmel,clk-output-range = <0 66000000>;
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};
|
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};
|
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|
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|
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Required properties for pll clocks:
|
||||
- interrupt-parent : must reference the PMC node.
|
||||
- interrupts : shall be set to "<1>".
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
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- clocks : shall be the main clock phandle.
|
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- reg : pll id.
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0 -> PLL A
|
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1 -> PLL B
|
||||
- atmel,clk-input-range : minimum and maximum source clock frequency (two u32
|
||||
fields).
|
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e.g. input = <1 32000000>; <=> 1 to 32MHz.
|
||||
- #atmel,pll-clk-output-range-cells : number of cells reserved for pll output
|
||||
range description. Sould be set to 2, 3
|
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or 4.
|
||||
* 1st and 2nd cells represent the frequency range (min-max).
|
||||
* 3rd cell is optional and represents the OUT field value for the given
|
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range.
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* 4th cell is optional and represents the ICPLL field (PLLICPR
|
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register)
|
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- atmel,pll-clk-output-ranges : pll output frequency ranges + optional parameter
|
||||
depending on #atmel,pll-output-range-cells
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property value.
|
||||
|
||||
For example:
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plla: pllack {
|
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compatible = "atmel,at91sam9g45-clk-pll";
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interrupt-parent = <&pmc>;
|
||||
interrupts = <1>;
|
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#clock-cells = <0>;
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clocks = <&main>;
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reg = <0>;
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atmel,clk-input-range = <2000000 32000000>;
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#atmel,pll-clk-output-range-cells = <4>;
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atmel,pll-clk-output-ranges = <74500000 800000000 0 0
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69500000 750000000 1 0
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64500000 700000000 2 0
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59500000 650000000 3 0
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54500000 600000000 0 1
|
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49500000 550000000 1 1
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44500000 500000000 2 1
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40000000 450000000 3 1>;
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};
|
||||
|
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Required properties for plldiv clocks (plldiv = pll / 2):
|
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- #clock-cells : from common clock binding; shall be set to 0.
|
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- clocks : shall be the plla clock phandle.
|
||||
|
||||
The pll divisor is equal to 2 and cannot be changed.
|
||||
|
||||
For example:
|
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plladiv: plladivck {
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compatible = "atmel,at91sam9x5-clk-plldiv";
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#clock-cells = <0>;
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clocks = <&plla>;
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};
|
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Required properties for programmable clocks:
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||||
- interrupt-parent : must reference the PMC node.
|
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- #size-cells : shall be 0 (reg is used to encode clk id).
|
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- #address-cells : shall be 1 (reg is used to encode clk id).
|
||||
- clocks : shall be the programmable clock source phandles.
|
||||
e.g. clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
|
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- name: device tree node describing a specific prog clock.
|
||||
* #clock-cells : from common clock binding; shall be set to 0.
|
||||
* reg : programmable clock id (register offset from PCKx
|
||||
register).
|
||||
* interrupts : shall be set to "<(8 + id)>".
|
||||
|
||||
For example:
|
||||
prog: progck {
|
||||
compatible = "atmel,at91sam9g45-clk-programmable";
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
interrupt-parent = <&pmc>;
|
||||
clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
|
||||
|
||||
prog0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0>;
|
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interrupts = <8>;
|
||||
};
|
||||
|
||||
prog1 {
|
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#clock-cells = <0>;
|
||||
reg = <1>;
|
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interrupts = <9>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Required properties for smd clock:
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : shall be the smd clock source phandles.
|
||||
e.g. clocks = <&plladiv>, <&utmi>;
|
||||
|
||||
For example:
|
||||
smd: smdck {
|
||||
compatible = "atmel,at91sam9x5-clk-smd";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&plladiv>, <&utmi>;
|
||||
};
|
||||
|
||||
Required properties for system clocks:
|
||||
- #size-cells : shall be 0 (reg is used to encode clk id).
|
||||
- #address-cells : shall be 1 (reg is used to encode clk id).
|
||||
- name: device tree node describing a specific system clock.
|
||||
* #clock-cells : from common clock binding; shall be set to 0.
|
||||
* reg: system clock id (bit position in SCER/SCDR/SCSR registers).
|
||||
See Atmel's datasheet to get a full list of system clock ids.
|
||||
|
||||
For example:
|
||||
system: systemck {
|
||||
compatible = "atmel,at91rm9200-clk-system";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ddrck {
|
||||
#clock-cells = <0>;
|
||||
reg = <2>;
|
||||
clocks = <&mck>;
|
||||
};
|
||||
|
||||
uhpck {
|
||||
#clock-cells = <0>;
|
||||
reg = <6>;
|
||||
clocks = <&usb>;
|
||||
};
|
||||
|
||||
udpck {
|
||||
#clock-cells = <0>;
|
||||
reg = <7>;
|
||||
clocks = <&usb>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Required properties for usb clock:
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : shall be the smd clock source phandles.
|
||||
e.g. clocks = <&pllb>;
|
||||
- atmel,clk-divisors (only available for "atmel,at91rm9200-clk-usb"):
|
||||
usb clock divisor table.
|
||||
e.g. divisors = <1 2 4 0>;
|
||||
|
||||
For example:
|
||||
usb: usbck {
|
||||
compatible = "atmel,at91sam9x5-clk-usb";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&plladiv>, <&utmi>;
|
||||
};
|
||||
|
||||
usb: usbck {
|
||||
compatible = "atmel,at91rm9200-clk-usb";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&pllb>;
|
||||
atmel,clk-divisors = <1 2 4 0>;
|
||||
};
|
||||
|
||||
|
||||
Required properties for utmi clock:
|
||||
- interrupt-parent : must reference the PMC node.
|
||||
- interrupts : shall be set to "<AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>".
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : shall be the main clock source phandle.
|
||||
|
||||
For example:
|
||||
utmi: utmick {
|
||||
compatible = "atmel,at91sam9x5-clk-utmi";
|
||||
interrupt-parent = <&pmc>;
|
||||
interrupts = <AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&main>;
|
||||
};
|
||||
@@ -15,6 +15,9 @@ Required properties :
|
||||
In clock consumers, this cell represents the clock ID exposed by the
|
||||
CAR. The assignments may be found in header file
|
||||
<dt-bindings/clock/tegra114-car.h>.
|
||||
- #reset-cells : Should be 1.
|
||||
In clock consumers, this cell represents the bit number in the CAR's
|
||||
array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
|
||||
|
||||
Example SoC include file:
|
||||
|
||||
@@ -23,6 +26,7 @@ Example SoC include file:
|
||||
compatible = "nvidia,tegra114-car";
|
||||
reg = <0x60006000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
usb@c5004000 {
|
||||
|
||||
@@ -0,0 +1,63 @@
|
||||
NVIDIA Tegra124 Clock And Reset Controller
|
||||
|
||||
This binding uses the common clock binding:
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
|
||||
for muxing and gating Tegra's clocks, and setting their rates.
|
||||
|
||||
Required properties :
|
||||
- compatible : Should be "nvidia,tegra124-car"
|
||||
- reg : Should contain CAR registers location and length
|
||||
- clocks : Should contain phandle and clock specifiers for two clocks:
|
||||
the 32 KHz "32k_in", and the board-specific oscillator "osc".
|
||||
- #clock-cells : Should be 1.
|
||||
In clock consumers, this cell represents the clock ID exposed by the
|
||||
CAR. The assignments may be found in header file
|
||||
<dt-bindings/clock/tegra124-car.h>.
|
||||
- #reset-cells : Should be 1.
|
||||
In clock consumers, this cell represents the bit number in the CAR's
|
||||
array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
|
||||
|
||||
Example SoC include file:
|
||||
|
||||
/ {
|
||||
tegra_car: clock {
|
||||
compatible = "nvidia,tegra124-car";
|
||||
reg = <0x60006000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
usb@c5004000 {
|
||||
clocks = <&tegra_car TEGRA124_CLK_USB2>;
|
||||
};
|
||||
};
|
||||
|
||||
Example board file:
|
||||
|
||||
/ {
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
osc: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <112400000>;
|
||||
};
|
||||
|
||||
clk_32k: clock@1 {
|
||||
compatible = "fixed-clock";
|
||||
reg = <1>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
&tegra_car {
|
||||
clocks = <&clk_32k> <&osc>;
|
||||
};
|
||||
};
|
||||
@@ -15,6 +15,9 @@ Required properties :
|
||||
In clock consumers, this cell represents the clock ID exposed by the
|
||||
CAR. The assignments may be found in header file
|
||||
<dt-bindings/clock/tegra20-car.h>.
|
||||
- #reset-cells : Should be 1.
|
||||
In clock consumers, this cell represents the bit number in the CAR's
|
||||
array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
|
||||
|
||||
Example SoC include file:
|
||||
|
||||
@@ -23,6 +26,7 @@ Example SoC include file:
|
||||
compatible = "nvidia,tegra20-car";
|
||||
reg = <0x60006000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
usb@c5004000 {
|
||||
|
||||
@@ -15,6 +15,9 @@ Required properties :
|
||||
In clock consumers, this cell represents the clock ID exposed by the
|
||||
CAR. The assignments may be found in header file
|
||||
<dt-bindings/clock/tegra30-car.h>.
|
||||
- #reset-cells : Should be 1.
|
||||
In clock consumers, this cell represents the bit number in the CAR's
|
||||
array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
|
||||
|
||||
Example SoC include file:
|
||||
|
||||
@@ -23,6 +26,7 @@ Example SoC include file:
|
||||
compatible = "nvidia,tegra30-car";
|
||||
reg = <0x60006000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
usb@c5004000 {
|
||||
|
||||
@@ -5,6 +5,16 @@ Required properties:
|
||||
- reg: Should contain DMA registers location and length. This shuld include
|
||||
all of the per-channel registers.
|
||||
- interrupts: Should contain all of the per-channel DMA interrupts.
|
||||
- clocks: Must contain one entry, for the module clock.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- resets : Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names : Must include the following entries:
|
||||
- dma
|
||||
- #dma-cells : Must be <1>. This dictates the length of DMA specifiers in
|
||||
client nodes' dmas properties. The specifier represents the DMA request
|
||||
select value for the peripheral. For more details, consult the Tegra TRM's
|
||||
documentation of the APB DMA channel control register REQ_SEL field.
|
||||
|
||||
Examples:
|
||||
|
||||
@@ -27,4 +37,8 @@ apbdma: dma@6000a000 {
|
||||
0 149 0x04
|
||||
0 150 0x04
|
||||
0 151 0x04 >;
|
||||
clocks = <&tegra_car 34>;
|
||||
resets = <&tegra_car 34>;
|
||||
reset-names = "dma";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
@@ -9,6 +9,12 @@ Required properties:
|
||||
- #size-cells: The number of cells used to represent the size of an address
|
||||
range in the host1x address space. Should be 1.
|
||||
- ranges: The mapping of the host1x address space to the CPU address space.
|
||||
- clocks: Must contain one entry, for the module clock.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- host1x
|
||||
|
||||
The host1x top-level node defines a number of children, each representing one
|
||||
of the following host1x client modules:
|
||||
@@ -19,6 +25,12 @@ of the following host1x client modules:
|
||||
- compatible: "nvidia,tegra<chip>-mpe"
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt outputs from the controller.
|
||||
- clocks: Must contain one entry, for the module clock.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- mpe
|
||||
|
||||
- vi: video input
|
||||
|
||||
@@ -26,6 +38,12 @@ of the following host1x client modules:
|
||||
- compatible: "nvidia,tegra<chip>-vi"
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt outputs from the controller.
|
||||
- clocks: Must contain one entry, for the module clock.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- vi
|
||||
|
||||
- epp: encoder pre-processor
|
||||
|
||||
@@ -33,6 +51,12 @@ of the following host1x client modules:
|
||||
- compatible: "nvidia,tegra<chip>-epp"
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt outputs from the controller.
|
||||
- clocks: Must contain one entry, for the module clock.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- epp
|
||||
|
||||
- isp: image signal processor
|
||||
|
||||
@@ -40,6 +64,12 @@ of the following host1x client modules:
|
||||
- compatible: "nvidia,tegra<chip>-isp"
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt outputs from the controller.
|
||||
- clocks: Must contain one entry, for the module clock.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- isp
|
||||
|
||||
- gr2d: 2D graphics engine
|
||||
|
||||
@@ -47,12 +77,30 @@ of the following host1x client modules:
|
||||
- compatible: "nvidia,tegra<chip>-gr2d"
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt outputs from the controller.
|
||||
- clocks: Must contain one entry, for the module clock.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- 2d
|
||||
|
||||
- gr3d: 3D graphics engine
|
||||
|
||||
Required properties:
|
||||
- compatible: "nvidia,tegra<chip>-gr3d"
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
(This property may be omitted if the only clock in the list is "3d")
|
||||
- 3d
|
||||
This MUST be the first entry.
|
||||
- 3d2 (Only required on SoCs with two 3D clocks)
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- 3d
|
||||
- 3d2 (Only required on SoCs with two 3D clocks)
|
||||
|
||||
- dc: display controller
|
||||
|
||||
@@ -60,6 +108,16 @@ of the following host1x client modules:
|
||||
- compatible: "nvidia,tegra<chip>-dc"
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt outputs from the controller.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
- dc
|
||||
This MUST be the first entry.
|
||||
- parent
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- dc
|
||||
|
||||
Each display controller node has a child node, named "rgb", that represents
|
||||
the RGB output associated with the controller. It can take the following
|
||||
@@ -76,6 +134,16 @@ of the following host1x client modules:
|
||||
- interrupts: The interrupt outputs from the controller.
|
||||
- vdd-supply: regulator for supply voltage
|
||||
- pll-supply: regulator for PLL
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
- hdmi
|
||||
This MUST be the first entry.
|
||||
- parent
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- hdmi
|
||||
|
||||
Optional properties:
|
||||
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
|
||||
@@ -88,12 +156,24 @@ of the following host1x client modules:
|
||||
- compatible: "nvidia,tegra<chip>-tvo"
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt outputs from the controller.
|
||||
- clocks: Must contain one entry, for the module clock.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
|
||||
- dsi: display serial interface
|
||||
|
||||
Required properties:
|
||||
- compatible: "nvidia,tegra<chip>-dsi"
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
- dsi
|
||||
This MUST be the first entry.
|
||||
- parent
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- dsi
|
||||
|
||||
Example:
|
||||
|
||||
@@ -105,6 +185,9 @@ Example:
|
||||
reg = <0x50000000 0x00024000>;
|
||||
interrupts = <0 65 0x04 /* mpcore syncpt */
|
||||
0 67 0x04>; /* mpcore general */
|
||||
clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
|
||||
resets = <&tegra_car 28>;
|
||||
reset-names = "host1x";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
@@ -115,41 +198,64 @@ Example:
|
||||
compatible = "nvidia,tegra20-mpe";
|
||||
reg = <0x54040000 0x00040000>;
|
||||
interrupts = <0 68 0x04>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_MPE>;
|
||||
resets = <&tegra_car 60>;
|
||||
reset-names = "mpe";
|
||||
};
|
||||
|
||||
vi {
|
||||
compatible = "nvidia,tegra20-vi";
|
||||
reg = <0x54080000 0x00040000>;
|
||||
interrupts = <0 69 0x04>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_VI>;
|
||||
resets = <&tegra_car 100>;
|
||||
reset-names = "vi";
|
||||
};
|
||||
|
||||
epp {
|
||||
compatible = "nvidia,tegra20-epp";
|
||||
reg = <0x540c0000 0x00040000>;
|
||||
interrupts = <0 70 0x04>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_EPP>;
|
||||
resets = <&tegra_car 19>;
|
||||
reset-names = "epp";
|
||||
};
|
||||
|
||||
isp {
|
||||
compatible = "nvidia,tegra20-isp";
|
||||
reg = <0x54100000 0x00040000>;
|
||||
interrupts = <0 71 0x04>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_ISP>;
|
||||
resets = <&tegra_car 23>;
|
||||
reset-names = "isp";
|
||||
};
|
||||
|
||||
gr2d {
|
||||
compatible = "nvidia,tegra20-gr2d";
|
||||
reg = <0x54140000 0x00040000>;
|
||||
interrupts = <0 72 0x04>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_GR2D>;
|
||||
resets = <&tegra_car 21>;
|
||||
reset-names = "2d";
|
||||
};
|
||||
|
||||
gr3d {
|
||||
compatible = "nvidia,tegra20-gr3d";
|
||||
reg = <0x54180000 0x00040000>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
|
||||
resets = <&tegra_car 24>;
|
||||
reset-names = "3d";
|
||||
};
|
||||
|
||||
dc@54200000 {
|
||||
compatible = "nvidia,tegra20-dc";
|
||||
reg = <0x54200000 0x00040000>;
|
||||
interrupts = <0 73 0x04>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_DISP1>,
|
||||
<&tegra_car TEGRA20_CLK_PLL_P>;
|
||||
clock-names = "disp1", "parent";
|
||||
resets = <&tegra_car 27>;
|
||||
reset-names = "dc";
|
||||
|
||||
rgb {
|
||||
status = "disabled";
|
||||
@@ -160,6 +266,11 @@ Example:
|
||||
compatible = "nvidia,tegra20-dc";
|
||||
reg = <0x54240000 0x00040000>;
|
||||
interrupts = <0 74 0x04>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_DISP2>,
|
||||
<&tegra_car TEGRA20_CLK_PLL_P>;
|
||||
clock-names = "disp2", "parent";
|
||||
resets = <&tegra_car 26>;
|
||||
reset-names = "dc";
|
||||
|
||||
rgb {
|
||||
status = "disabled";
|
||||
@@ -170,6 +281,11 @@ Example:
|
||||
compatible = "nvidia,tegra20-hdmi";
|
||||
reg = <0x54280000 0x00040000>;
|
||||
interrupts = <0 75 0x04>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_HDMI>,
|
||||
<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
|
||||
clock-names = "hdmi", "parent";
|
||||
resets = <&tegra_car 51>;
|
||||
reset-names = "hdmi";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -177,12 +293,18 @@ Example:
|
||||
compatible = "nvidia,tegra20-tvo";
|
||||
reg = <0x542c0000 0x00040000>;
|
||||
interrupts = <0 76 0x04>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_TVO>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dsi {
|
||||
compatible = "nvidia,tegra20-dsi";
|
||||
reg = <0x54300000 0x00040000>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_DSI>,
|
||||
<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
|
||||
clock-names = "dsi", "parent";
|
||||
resets = <&tegra_car 48>;
|
||||
reset-names = "dsi";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -39,12 +39,23 @@ Required properties:
|
||||
- interrupts: Should contain I2C controller interrupts.
|
||||
- address-cells: Address cells for I2C device address.
|
||||
- size-cells: Size of the I2C device address.
|
||||
- clocks: Clock ID as per
|
||||
Documentation/devicetree/bindings/clock/tegra<chip-id>.txt
|
||||
for I2C controller.
|
||||
- clock-names: Name of the clock:
|
||||
Tegra20/Tegra30 I2C controller: "div-clk and "fast-clk".
|
||||
Tegra114 I2C controller: "div-clk".
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
Tegra20/Tegra30:
|
||||
- div-clk
|
||||
- fast-clk
|
||||
Tegra114:
|
||||
- div-clk
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- i2c
|
||||
- dmas: Must contain an entry for each entry in clock-names.
|
||||
See ../dma/dma.txt for details.
|
||||
- dma-names: Must include the following entries:
|
||||
- rx
|
||||
- tx
|
||||
|
||||
Example:
|
||||
|
||||
@@ -56,5 +67,9 @@ Example:
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car 12>, <&tegra_car 124>;
|
||||
clock-names = "div-clk", "fast-clk";
|
||||
resets = <&tegra_car 12>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 16>, <&apbdma 16>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -13,6 +13,12 @@ Required properties:
|
||||
array of pin numbers which is used as column.
|
||||
- linux,keymap: The keymap for keys as described in the binding document
|
||||
devicetree/bindings/input/matrix-keymap.txt.
|
||||
- clocks: Must contain one entry, for the module clock.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- kbc
|
||||
|
||||
Optional properties, in addition to those specified by the shared
|
||||
matrix-keyboard bindings:
|
||||
@@ -31,6 +37,9 @@ keyboard: keyboard {
|
||||
compatible = "nvidia,tegra20-kbc";
|
||||
reg = <0x7000e200 0x100>;
|
||||
interrupts = <0 85 0x04>;
|
||||
clocks = <&tegra_car 36>;
|
||||
resets = <&tegra_car 36>;
|
||||
reset-names = "kbc";
|
||||
nvidia,ghost-filter;
|
||||
nvidia,debounce-delay-ms = <640>;
|
||||
nvidia,kbc-row-pins = <0 1 2>; /* pin 0, 1, 2 as rows */
|
||||
|
||||
@@ -8,6 +8,12 @@ by mmc.txt and the properties used by the sdhci-tegra driver.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "nvidia,<chip>-sdhci"
|
||||
- clocks : Must contain one entry, for the module clock.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- resets : Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names : Must include the following entries:
|
||||
- sdhci
|
||||
|
||||
Optional properties:
|
||||
- power-gpios : Specify GPIOs for power control
|
||||
@@ -18,6 +24,9 @@ sdhci@c8000200 {
|
||||
compatible = "nvidia,tegra20-sdhci";
|
||||
reg = <0xc8000200 0x200>;
|
||||
interrupts = <47>;
|
||||
clocks = <&tegra_car 14>;
|
||||
resets = <&tegra_car 14>;
|
||||
reset-names = "sdhci";
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 155 0>; /* gpio PT3 */
|
||||
|
||||
@@ -7,3 +7,15 @@ Required properties:
|
||||
- clock-frequency : the frequency of the i2c bus
|
||||
- gpios : the gpio used for ec request
|
||||
- slave-addr: the i2c address of the slave controller
|
||||
- clocks : Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names : Must include the following entries:
|
||||
Tegra20/Tegra30:
|
||||
- div-clk
|
||||
- fast-clk
|
||||
Tegra114:
|
||||
- div-clk
|
||||
- resets : Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names : Must include the following entries:
|
||||
- i2c
|
||||
|
||||
@@ -42,14 +42,19 @@ Required properties:
|
||||
- 0xc2000000: prefetchable memory region
|
||||
Please refer to the standard PCI bus binding document for a more detailed
|
||||
explanation.
|
||||
- clocks: List of clock inputs of the controller. Must contain an entry for
|
||||
each entry in the clock-names property.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
"pex": The Tegra clock of that name
|
||||
"afi": The Tegra clock of that name
|
||||
"pcie_xclk": The Tegra clock of that name
|
||||
"pll_e": The Tegra clock of that name
|
||||
"cml": The Tegra clock of that name (not required for Tegra20)
|
||||
- pex
|
||||
- afi
|
||||
- pll_e
|
||||
- cml (not required for Tegra20)
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- pex
|
||||
- afi
|
||||
- pcie_x
|
||||
|
||||
Root ports are defined as subnodes of the PCIe controller node.
|
||||
|
||||
@@ -91,9 +96,10 @@ SoC DTSI:
|
||||
0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable memory */
|
||||
0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
|
||||
|
||||
clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>,
|
||||
<&tegra_car 118>;
|
||||
clock-names = "pex", "afi", "pcie_xclk", "pll_e";
|
||||
clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>;
|
||||
clock-names = "pex", "afi", "pll_e";
|
||||
resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>;
|
||||
reset-names = "pex", "afi", "pcie_x";
|
||||
status = "disabled";
|
||||
|
||||
pci@1,0 {
|
||||
|
||||
@@ -7,6 +7,12 @@ Required properties:
|
||||
- reg: physical base address and length of the controller's registers
|
||||
- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
|
||||
the cells format.
|
||||
- clocks: Must contain one entry, for the module clock.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- pwm
|
||||
|
||||
Example:
|
||||
|
||||
@@ -14,4 +20,7 @@ Example:
|
||||
compatible = "nvidia,tegra20-pwm";
|
||||
reg = <0x7000a000 0x100>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&tegra_car 17>;
|
||||
resets = <&tegra_car 17>;
|
||||
reset-names = "pwm";
|
||||
};
|
||||
|
||||
@@ -9,6 +9,8 @@ Required properties:
|
||||
- compatible : should be "nvidia,tegra20-rtc".
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
- interrupts : A single interrupt specifier.
|
||||
- clocks : Must contain one entry, for the module clock.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
|
||||
Example:
|
||||
|
||||
@@ -16,4 +18,5 @@ timer {
|
||||
compatible = "nvidia,tegra20-rtc";
|
||||
reg = <0x7000e000 0x100>;
|
||||
interrupts = <0 2 0x04>;
|
||||
clocks = <&tegra_car 4>;
|
||||
};
|
||||
|
||||
@@ -4,8 +4,17 @@ Required properties:
|
||||
- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
|
||||
- reg: Should contain UART controller registers location and length.
|
||||
- interrupts: Should contain UART controller interrupts.
|
||||
- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
|
||||
request selector for this UART controller.
|
||||
- clocks: Must contain one entry, for the module clock.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- resets : Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names : Must include the following entries:
|
||||
- serial
|
||||
- dmas : Must contain an entry for each entry in clock-names.
|
||||
See ../dma/dma.txt for details.
|
||||
- dma-names : Must include the following entries:
|
||||
- rx
|
||||
- tx
|
||||
|
||||
Optional properties:
|
||||
- nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable
|
||||
@@ -18,7 +27,11 @@ serial@70006000 {
|
||||
reg = <0x70006000 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <0 36 0x04>;
|
||||
nvidia,dma-request-selector = <&apbdma 8>;
|
||||
nvidia,enable-modem-interrupt;
|
||||
clocks = <&tegra_car 6>;
|
||||
resets = <&tegra_car 6>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 8>, <&apbdma 8>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
|
||||
Required properties:
|
||||
- compatible : "nvidia,tegra-audio-alc5632"
|
||||
- clocks : Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names : Must include the following entries:
|
||||
"pll_a" (The Tegra clock of that name),
|
||||
"pll_a_out0" (The Tegra clock of that name),
|
||||
"mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
|
||||
- pll_a
|
||||
- pll_a_out0
|
||||
- mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
|
||||
- nvidia,model : The user-visible name of this sound complex.
|
||||
- nvidia,audio-routing : A list of the connections between audio components.
|
||||
Each entry is a pair of strings, the first being the connection's sink,
|
||||
|
||||
@@ -3,10 +3,11 @@ NVIDIA Tegra audio complex, with RT5640 CODEC
|
||||
Required properties:
|
||||
- compatible : "nvidia,tegra-audio-rt5640"
|
||||
- clocks : Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names : Must include the following entries:
|
||||
"pll_a" (The Tegra clock of that name),
|
||||
"pll_a_out0" (The Tegra clock of that name),
|
||||
"mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
|
||||
- pll_a
|
||||
- pll_a_out0
|
||||
- mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
|
||||
- nvidia,model : The user-visible name of this sound complex.
|
||||
- nvidia,audio-routing : A list of the connections between audio components.
|
||||
Each entry is a pair of strings, the first being the connection's sink,
|
||||
|
||||
@@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
|
||||
Required properties:
|
||||
- compatible : "nvidia,tegra-audio-wm8753"
|
||||
- clocks : Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names : Must include the following entries:
|
||||
"pll_a" (The Tegra clock of that name),
|
||||
"pll_a_out0" (The Tegra clock of that name),
|
||||
"mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
|
||||
- pll_a
|
||||
- pll_a_out0
|
||||
- mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
|
||||
- nvidia,model : The user-visible name of this sound complex.
|
||||
- nvidia,audio-routing : A list of the connections between audio components.
|
||||
Each entry is a pair of strings, the first being the connection's sink,
|
||||
|
||||
@@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
|
||||
Required properties:
|
||||
- compatible : "nvidia,tegra-audio-wm8903"
|
||||
- clocks : Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names : Must include the following entries:
|
||||
"pll_a" (The Tegra clock of that name),
|
||||
"pll_a_out0" (The Tegra clock of that name),
|
||||
"mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
|
||||
- pll_a
|
||||
- pll_a_out0
|
||||
- mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
|
||||
- nvidia,model : The user-visible name of this sound complex.
|
||||
- nvidia,audio-routing : A list of the connections between audio components.
|
||||
Each entry is a pair of strings, the first being the connection's sink,
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user