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Merge tag 'newsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull support for three new arm SoC types from Arnd Bergmann: - The mvebu platform includes Marvell's Armada XP and Armada 370 chips, made by the mvebu business unit inside of Marvell. Since the same group also made the older but similar platforms we call "orion5x", "kirkwood", "mv78xx0" and "dove", we plan to move all of them into the mach-mvebu directory in the future. - socfpga is Altera's platform based on Cortex-A9 cores and a lot of FPGA space. This is similar to the Xilinx zynq platform we already support. The code is particularly clean, which is helped by the fact that the hardware doesn't do much besides the parts that are expected to get added in the FPGA. - The OMAP subarchitecture gains support for the latest generation, the OMAP5 based on the new Cortex-A15 core. Support is rather rudimentary for now, but will be extended in the future. * tag 'newsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (25 commits) ARM: socfpga: initial support for Altera's SOCFPGA platform arm: mvebu: generate DTBs for supported SoCs ARM: mvebu: MPIC: read number of interrupts from control register arm: mach-mvebu: add entry to MAINTAINERS arm: mach-mvebu: add compilation/configuration change arm: mach-mvebu: add defconfig arm: mach-mvebu: add documentation for new device tree bindings arm: mach-mvebu: add support for Armada 370 and Armada XP with DT arm: mach-mvebu: add source files arm: mach-mvebu: add header clocksource: time-armada-370-xp: Marvell Armada 370/XP SoC timer driver ARM: Kconfig update to support additional GPIOs in OMAP5 ARM: OMAP5: Add the build support arm/dts: OMAP5: Add omap5 dts files ARM: OMAP5: board-generic: Add device tree support ARM: omap2+: board-generic: clean up the irq data from board file ARM: OMAP5: Add SMP support ARM: OMAP5: Add the WakeupGen IP updates ARM: OMAP5: l3: Add l3 error handler support for omap5 ARM: OMAP5: gpmc: Update gpmc_init() ... Conflicts: Documentation/devicetree/bindings/arm/omap/omap.txt arch/arm/mach-omap2/Makefile drivers/clocksource/Kconfig drivers/clocksource/Makefile
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,23 @@
|
||||
Marvell Armada 370 and Armada XP Interrupt Controller
|
||||
-----------------------------------------------------
|
||||
|
||||
Required properties:
|
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- compatible: Should be "marvell,mpic"
|
||||
- interrupt-controller: Identifies the node as an interrupt controller.
|
||||
- #interrupt-cells: The number of cells to define the interrupts. Should be 1.
|
||||
The cell is the IRQ number
|
||||
- reg: Should contain PMIC registers location and length. First pair
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for the main interrupt registers, second pair for the per-CPU
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||||
interrupt registers
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||||
|
||||
Example:
|
||||
|
||||
mpic: interrupt-controller@d0020000 {
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||||
compatible = "marvell,mpic";
|
||||
#interrupt-cells = <1>;
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||||
#address-cells = <1>;
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||||
#size-cells = <1>;
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interrupt-controller;
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reg = <0xd0020000 0x1000>,
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<0xd0021000 0x1000>;
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};
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@@ -0,0 +1,11 @@
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Marvell Armada 370 and Armada XP Global Timers
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----------------------------------------------
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|
||||
Required properties:
|
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- compatible: Should be "marvell,armada-370-xp-timer"
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||||
- interrupts: Should contain the list of Global Timer interrupts
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- reg: Should contain the base address of the Global Timer registers
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||||
|
||||
Optional properties:
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||||
- marvell,timer-25Mhz: Tells whether the Global timer supports the 25
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||||
Mhz fixed mode (available on Armada XP and not on Armada 370)
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||||
@@ -0,0 +1,24 @@
|
||||
Marvell Armada 370 and Armada XP Platforms Device Tree Bindings
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---------------------------------------------------------------
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||||
|
||||
Boards with a SoC of the Marvell Armada 370 and Armada XP families
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shall have the following property:
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|
||||
Required root node property:
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|
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compatible: must contain "marvell,armada-370-xp"
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||||
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||||
In addition, boards using the Marvell Armada 370 SoC shall have the
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following property:
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||||
|
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Required root node property:
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||||
|
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compatible: must contain "marvell,armada370"
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In addition, boards using the Marvell Armada XP SoC shall have the
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following property:
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Required root node property:
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|
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compatible: must contain "marvell,armadaxp"
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|
||||
@@ -0,0 +1,17 @@
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MVEBU System Controller
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-----------------------
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MVEBU (Marvell SOCs: Armada 370/XP, Dove, mv78xx0, Kirkwood, Orion5x)
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|
||||
Required properties:
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- compatible: one of:
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- "marvell,orion-system-controller"
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- "marvell,armada-370-xp-system-controller"
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- reg: Should contain system controller registers location and length.
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|
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Example:
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|
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system-controller@d0018200 {
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compatible = "marvell,armada-370-xp-system-controller";
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reg = <0xd0018200 0x500>;
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};
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@@ -50,3 +50,6 @@ Boards:
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|
||||
- AM335X Bone : Low cost community board
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compatible = "ti,am335x-bone", "ti,am33xx", "ti,omap3"
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||||
|
||||
- OMAP5 EVM : Evaluation Module
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compatible = "ti,omap5-evm", "ti,omap5"
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|
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+18
@@ -894,6 +894,14 @@ ARM/MAGICIAN MACHINE SUPPORT
|
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M: Philipp Zabel <philipp.zabel@gmail.com>
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S: Maintained
|
||||
|
||||
ARM/Marvell Armada 370 and Armada XP SOC support
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M: Jason Cooper <jason@lakedaemon.net>
|
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M: Andrew Lunn <andrew@lunn.ch>
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M: Gregory Clement <gregory.clement@free-electrons.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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||||
F: arch/arm/mach-mvebu/
|
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|
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ARM/Marvell Dove/Kirkwood/MV78xx0/Orion SOC support
|
||||
M: Jason Cooper <jason@lakedaemon.net>
|
||||
M: Andrew Lunn <andrew@lunn.ch>
|
||||
@@ -1103,6 +1111,16 @@ S: Supported
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F: arch/arm/mach-shmobile/
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F: drivers/sh/
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||||
|
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ARM/SOCFPGA ARCHITECTURE
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||||
M: Dinh Nguyen <dinguyen@altera.com>
|
||||
S: Maintained
|
||||
F: arch/arm/mach-socfpga/
|
||||
|
||||
ARM/SOCFPGA CLOCK FRAMEWORK SUPPORT
|
||||
M: Dinh Nguyen <dinguyen@altera.com>
|
||||
S: Maintained
|
||||
F: drivers/clk/socfpga/
|
||||
|
||||
ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
|
||||
M: Lennert Buytenhek <kernel@wantstofly.org>
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||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
|
||||
@@ -250,6 +250,25 @@ choice
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||||
prompt "ARM system type"
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||||
default ARCH_VERSATILE
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|
||||
config ARCH_SOCFPGA
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||||
bool "Altera SOCFPGA family"
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||||
select ARCH_WANT_OPTIONAL_GPIOLIB
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||||
select ARM_AMBA
|
||||
select ARM_GIC
|
||||
select CACHE_L2X0
|
||||
select CLKDEV_LOOKUP
|
||||
select COMMON_CLK
|
||||
select CPU_V7
|
||||
select DW_APB_TIMER
|
||||
select DW_APB_TIMER_OF
|
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select GENERIC_CLOCKEVENTS
|
||||
select GPIO_PL061 if GPIOLIB
|
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select HAVE_ARM_SCU
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select SPARSE_IRQ
|
||||
select USE_OF
|
||||
help
|
||||
This enables support for Altera SOCFPGA Cyclone V platform
|
||||
|
||||
config ARCH_INTEGRATOR
|
||||
bool "ARM Ltd. Integrator family"
|
||||
select ARM_AMBA
|
||||
@@ -537,6 +556,18 @@ config ARCH_IXP4XX
|
||||
help
|
||||
Support for Intel's IXP4XX (XScale) family of processors.
|
||||
|
||||
config ARCH_MVEBU
|
||||
bool "Marvell SOCs with Device Tree support"
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select MULTI_IRQ_HANDLER
|
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select SPARSE_IRQ
|
||||
select CLKSRC_MMIO
|
||||
select GENERIC_IRQ_CHIP
|
||||
select IRQ_DOMAIN
|
||||
select COMMON_CLK
|
||||
help
|
||||
Support for the Marvell SoC Family with device tree support
|
||||
|
||||
config ARCH_DOVE
|
||||
bool "Marvell Dove"
|
||||
select CPU_V7
|
||||
@@ -994,6 +1025,8 @@ endchoice
|
||||
# Kconfigs may be included either alphabetically (according to the
|
||||
# plat- suffix) or along side the corresponding mach-* source.
|
||||
#
|
||||
source "arch/arm/mach-mvebu/Kconfig"
|
||||
|
||||
source "arch/arm/mach-at91/Kconfig"
|
||||
|
||||
source "arch/arm/mach-bcmring/Kconfig"
|
||||
@@ -1586,6 +1619,7 @@ config ARCH_NR_GPIO
|
||||
default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
|
||||
default 355 if ARCH_U8500
|
||||
default 264 if MACH_H4700
|
||||
default 512 if SOC_OMAP5
|
||||
default 0
|
||||
help
|
||||
Maximum number of GPIOs in the system.
|
||||
|
||||
@@ -157,6 +157,7 @@ machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0
|
||||
machine-$(CONFIG_ARCH_IMX_V4_V5) := imx
|
||||
machine-$(CONFIG_ARCH_IMX_V6_V7) := imx
|
||||
machine-$(CONFIG_ARCH_MXS) := mxs
|
||||
machine-$(CONFIG_ARCH_MVEBU) := mvebu
|
||||
machine-$(CONFIG_ARCH_NETX) := netx
|
||||
machine-$(CONFIG_ARCH_NOMADIK) := nomadik
|
||||
machine-$(CONFIG_ARCH_OMAP1) := omap1
|
||||
@@ -186,6 +187,7 @@ machine-$(CONFIG_ARCH_VEXPRESS) := vexpress
|
||||
machine-$(CONFIG_ARCH_VT8500) := vt8500
|
||||
machine-$(CONFIG_ARCH_W90X900) := w90x900
|
||||
machine-$(CONFIG_FOOTBRIDGE) := footbridge
|
||||
machine-$(CONFIG_ARCH_SOCFPGA) := socfpga
|
||||
machine-$(CONFIG_MACH_SPEAR1310) := spear13xx
|
||||
machine-$(CONFIG_MACH_SPEAR1340) := spear13xx
|
||||
machine-$(CONFIG_MACH_SPEAR300) := spear3xx
|
||||
|
||||
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Device Tree file for Marvell Armada 370 evaluation board
|
||||
* (DB-88F6710-BP-DDR3)
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "armada-370.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 370 Evaluation Board";
|
||||
compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x20000000>; /* 512 MB */
|
||||
};
|
||||
|
||||
soc {
|
||||
serial@d0012000 {
|
||||
clock-frequency = <200000000>;
|
||||
status = "okay";
|
||||
};
|
||||
timer@d0020300 {
|
||||
clock-frequency = <600000000>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,68 @@
|
||||
/*
|
||||
* Device Tree Include file for Marvell Armada 370 and Armada XP SoC
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
* Ben Dooks <ben.dooks@codethink.co.uk>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*
|
||||
* This file contains the definitions that are common to the Armada
|
||||
* 370 and Armada XP SoC.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 370 and XP SoC";
|
||||
compatible = "marvell,armada_370_xp";
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "marvell,sheeva-v7";
|
||||
};
|
||||
};
|
||||
|
||||
mpic: interrupt-controller@d0020000 {
|
||||
compatible = "marvell,mpic";
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&mpic>;
|
||||
ranges;
|
||||
|
||||
serial@d0012000 {
|
||||
compatible = "ns16550";
|
||||
reg = <0xd0012000 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <41>;
|
||||
status = "disabled";
|
||||
};
|
||||
serial@d0012100 {
|
||||
compatible = "ns16550";
|
||||
reg = <0xd0012100 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <42>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@d0020300 {
|
||||
compatible = "marvell,armada-370-xp-timer";
|
||||
reg = <0xd0020300 0x30>;
|
||||
interrupts = <37>, <38>, <39>, <40>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* Device Tree Include file for Marvell Armada 370 family SoC
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*
|
||||
* Contains definitions specific to the Armada 370 SoC that are not
|
||||
* common to all Armada SoCs.
|
||||
*/
|
||||
|
||||
/include/ "armada-370-xp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 370 family SoC";
|
||||
compatible = "marvell,armada370", "marvell,armada-370-xp";
|
||||
|
||||
mpic: interrupt-controller@d0020000 {
|
||||
reg = <0xd0020a00 0x1d0>,
|
||||
<0xd0021870 0x58>;
|
||||
};
|
||||
|
||||
soc {
|
||||
system-controller@d0018200 {
|
||||
compatible = "marvell,armada-370-xp-system-controller";
|
||||
reg = <0xd0018200 0x100>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,50 @@
|
||||
/*
|
||||
* Device Tree file for Marvell Armada XP evaluation board
|
||||
* (DB-78460-BP)
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "armada-xp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP Evaluation Board";
|
||||
compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x80000000>; /* 2 GB */
|
||||
};
|
||||
|
||||
soc {
|
||||
serial@d0012000 {
|
||||
clock-frequency = <250000000>;
|
||||
status = "okay";
|
||||
};
|
||||
serial@d0012100 {
|
||||
clock-frequency = <250000000>;
|
||||
status = "okay";
|
||||
};
|
||||
serial@d0012200 {
|
||||
clock-frequency = <250000000>;
|
||||
status = "okay";
|
||||
};
|
||||
serial@d0012300 {
|
||||
clock-frequency = <250000000>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,55 @@
|
||||
/*
|
||||
* Device Tree Include file for Marvell Armada XP family SoC
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
* Ben Dooks <ben.dooks@codethink.co.uk>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*
|
||||
* Contains definitions specific to the Armada 370 SoC that are not
|
||||
* common to all Armada SoCs.
|
||||
*/
|
||||
|
||||
/include/ "armada-370-xp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP family SoC";
|
||||
compatible = "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
mpic: interrupt-controller@d0020000 {
|
||||
reg = <0xd0020a00 0x1d0>,
|
||||
<0xd0021870 0x58>;
|
||||
};
|
||||
|
||||
soc {
|
||||
serial@d0012200 {
|
||||
compatible = "ns16550";
|
||||
reg = <0xd0012200 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <43>;
|
||||
status = "disabled";
|
||||
};
|
||||
serial@d0012300 {
|
||||
compatible = "ns16550";
|
||||
reg = <0xd0012300 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <44>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@d0020300 {
|
||||
marvell,timer-25Mhz;
|
||||
};
|
||||
|
||||
system-controller@d0018200 {
|
||||
compatible = "marvell,armada-370-xp-system-controller";
|
||||
reg = <0xd0018200 0x500>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "omap5.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI OMAP5 EVM board";
|
||||
compatible = "ti,omap5-evm", "ti,omap5";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x40000000>; /* 1 GB */
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,184 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
* Based on "omap4.dtsi"
|
||||
*/
|
||||
|
||||
/*
|
||||
* Carveout for multimedia usecases
|
||||
* It should be the last 48MB of the first 512MB memory part
|
||||
* In theory, it should not even exist. That zone should be reserved
|
||||
* dynamically during the .reserve callback.
|
||||
*/
|
||||
/memreserve/ 0x9d000000 0x03000000;
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,omap5";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
serial3 = &uart4;
|
||||
serial4 = &uart5;
|
||||
serial5 = &uart6;
|
||||
};
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a15";
|
||||
};
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a15";
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* The soc node represents the soc top level view. It is uses for IPs
|
||||
* that are not memory mapped in the MPU view or for the MPU itself.
|
||||
*/
|
||||
soc {
|
||||
compatible = "ti,omap-infra";
|
||||
mpu {
|
||||
compatible = "ti,omap5-mpu";
|
||||
ti,hwmods = "mpu";
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX: Use a flat representation of the OMAP3 interconnect.
|
||||
* The real OMAP interconnect network is quite complex.
|
||||
* Since that will not bring real advantage to represent that in DT for
|
||||
* the moment, just use a fake OCP bus entry to represent the whole bus
|
||||
* hierarchy.
|
||||
*/
|
||||
ocp {
|
||||
compatible = "ti,omap4-l3-noc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
|
||||
|
||||
gic: interrupt-controller@48211000 {
|
||||
compatible = "arm,cortex-a15-gic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x48211000 0x1000>,
|
||||
<0x48212000 0x1000>;
|
||||
};
|
||||
|
||||
gpio1: gpio@4ae10000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
ti,hwmods = "gpio1";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio2: gpio@48055000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
ti,hwmods = "gpio2";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio3: gpio@48057000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
ti,hwmods = "gpio3";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio4: gpio@48059000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
ti,hwmods = "gpio4";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio5: gpio@4805b000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
ti,hwmods = "gpio5";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio6: gpio@4805d000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
ti,hwmods = "gpio6";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio7: gpio@48051000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
ti,hwmods = "gpio7";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio8: gpio@48053000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
ti,hwmods = "gpio8";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
uart1: serial@4806a000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
ti,hwmods = "uart1";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
uart2: serial@4806c000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
ti,hwmods = "uart2";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
uart3: serial@48020000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
ti,hwmods = "uart3";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
uart4: serial@4806e000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
ti,hwmods = "uart4";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
uart5: serial@48066000 {
|
||||
compatible = "ti,omap5-uart";
|
||||
ti,hwmods = "uart5";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
uart6: serial@48068000 {
|
||||
compatible = "ti,omap6-uart";
|
||||
ti,hwmods = "uart6";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,147 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Altera <www.altera.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a9";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a9";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
intc: intc@fffed000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0xfffed000 0x1000>,
|
||||
<0xfffec100 0x100>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
device_type = "soc";
|
||||
interrupt-parent = <&intc>;
|
||||
ranges;
|
||||
|
||||
amba {
|
||||
compatible = "arm,amba-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
pdma: pdma@ffe01000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0xffe01000 0x1000>;
|
||||
interrupts = <0 180 4>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac0: stmmac@ff700000 {
|
||||
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
|
||||
reg = <0xff700000 0x2000>;
|
||||
interrupts = <0 115 4>;
|
||||
interrupt-names = "macirq";
|
||||
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
|
||||
phy-mode = "gmii";
|
||||
};
|
||||
|
||||
L2: l2-cache@fffef000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0xfffef000 0x1000>;
|
||||
interrupts = <0 38 0x04>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
/* Local timer */
|
||||
timer@fffec600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0xfffec600 0x100>;
|
||||
interrupts = <1 13 0xf04>;
|
||||
};
|
||||
|
||||
timer0: timer@ffc08000 {
|
||||
compatible = "snps,dw-apb-timer-sp";
|
||||
interrupts = <0 167 4>;
|
||||
clock-frequency = <200000000>;
|
||||
reg = <0xffc08000 0x1000>;
|
||||
};
|
||||
|
||||
timer1: timer@ffc09000 {
|
||||
compatible = "snps,dw-apb-timer-sp";
|
||||
interrupts = <0 168 4>;
|
||||
clock-frequency = <200000000>;
|
||||
reg = <0xffc09000 0x1000>;
|
||||
};
|
||||
|
||||
timer2: timer@ffd00000 {
|
||||
compatible = "snps,dw-apb-timer-osc";
|
||||
interrupts = <0 169 4>;
|
||||
clock-frequency = <200000000>;
|
||||
reg = <0xffd00000 0x1000>;
|
||||
};
|
||||
|
||||
timer3: timer@ffd01000 {
|
||||
compatible = "snps,dw-apb-timer-osc";
|
||||
interrupts = <0 170 4>;
|
||||
clock-frequency = <200000000>;
|
||||
reg = <0xffd01000 0x1000>;
|
||||
};
|
||||
|
||||
uart0: uart@ffc02000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0xffc02000 0x1000>;
|
||||
clock-frequency = <7372800>;
|
||||
interrupts = <0 162 4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
uart1: uart@ffc03000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0xffc03000 0x1000>;
|
||||
clock-frequency = <7372800>;
|
||||
interrupts = <0 163 4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,34 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "socfpga.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Altera SOCFPGA Cyclone V";
|
||||
compatible = "altr,socfpga-cyclone5";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,57600";
|
||||
};
|
||||
|
||||
memory {
|
||||
name = "memory";
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x10000000>; /* 256MB */
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,46 @@
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_EXPERT=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_ARCH_MVEBU=y
|
||||
CONFIG_MACH_ARMADA_370_XP=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_USE_OF=y
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_ARM_APPENDED_DTB=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_FS_XATTR is not set
|
||||
CONFIG_ISO9660_FS=y
|
||||
CONFIG_JOLIET=y
|
||||
CONFIG_UDF_FS=m
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_CODEPAGE_850=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NLS_ISO8859_2=y
|
||||
CONFIG_NLS_UTF8=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
CONFIG_TIMER_STATS=y
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_DEBUG_LL=y
|
||||
CONFIG_EARLY_PRINTK=y
|
||||
@@ -236,3 +236,4 @@ CONFIG_CRC_T10DIF=y
|
||||
CONFIG_CRC_ITU_T=y
|
||||
CONFIG_CRC7=y
|
||||
CONFIG_LIBCRC32C=y
|
||||
CONFIG_SOC_OMAP5=y
|
||||
|
||||
@@ -0,0 +1,83 @@
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_CPUSETS=y
|
||||
CONFIG_NAMESPACES=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_OPROFILE=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_LBDAF is not set
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_ARCH_SOCFPGA=y
|
||||
CONFIG_MACH_SOCFPGA_CYCLONE5=y
|
||||
CONFIG_ARM_THUMBEE=y
|
||||
# CONFIG_CACHE_L2X0 is not set
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_VMSPLIT_2G=y
|
||||
CONFIG_NR_CPUS=2
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_CMDLINE=""
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_NET_KEY=y
|
||||
CONFIG_NET_KEY_MIGRATE=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_IP_PNP_RARP=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_PROC_DEVICETREE=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_COUNT=2
|
||||
CONFIG_BLK_DEV_RAM_SIZE=8192
|
||||
CONFIG_SCSI=y
|
||||
# CONFIG_SCSI_PROC_FS is not set
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_STMMAC_ETH=y
|
||||
# CONFIG_STMMAC_PHY_ID_ZERO_WORKAROUND is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
# CONFIG_SERIO_SERPORT is not set
|
||||
CONFIG_SERIO_AMBAKMI=y
|
||||
CONFIG_LEGACY_PTY_COUNT=16
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=2
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
# CONFIG_RTC_HCTOSYS is not set
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT2_FS_POSIX_ACL=y
|
||||
# CONFIG_DNOTIFY is not set
|
||||
# CONFIG_INOTIFY_USER is not set
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_NTFS_FS=y
|
||||
CONFIG_NTFS_RW=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_ENABLE_DEFAULT_TRACERS=y
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_XZ_DEC=y
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user