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drm/i915: correct FBC update when pipe base update occurs

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We usually don't have an SAREA, and we always want to update the FBC
status anyway, so move the update up above the various master/sarea
checks.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
This commit is contained in:
Jesse Barnes
2009-09-17 17:06:47 -07:00
parent 7121413f2a
commit edb8195642
1 changed files with 3 additions and 3 deletions
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drivers/gpu/drm/i915/intel_display.c
+3 -3
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@@ -1260,6 +1260,9 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
I915_READ(dspbase);
}
if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
intel_update_fbc(crtc, &crtc->mode);
intel_wait_for_vblank(dev);
if (old_fb) {
@@ -1286,9 +1289,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
master_priv->sarea_priv->pipeA_y = y;
}
if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
intel_update_fbc(crtc, &crtc->mode);
return 0;
}