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Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull 64-bit ARM DT updates from Olof Johansson:
"Just as the 32-bit contents, the 64-bit device tree branch also
contains a number of additions this release cycle.
New platforms:
- LG LG1313
- Mediatek MT6755
- Renesas r8a7796
- Broadcom 2837
Other platforms with larger updates are:
- Nvidia X1 platforms (USB 3.0, regulators, display subsystem)
- Mediatek MT8173 (display subsystem added)
- Rockchip RK3399 (a lot of new peripherals)
- ARM Juno reference implementation (SCPI power domains, coresight,
thermal)"
* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (118 commits)
arm64: tegra: Enable HDMI on Jetson TX1
arm64: tegra: Add sor1_src clock
arm64: tegra: Add XUSB powergates on Tegra210
arm64: tegra: Add DPAUX pinctrl bindings
arm64: tegra: Add ACONNECT bus node for Tegra210
arm64: tegra: Add audio powergate node for Tegra210
arm64: tegra: Add regulators for Tegra210 Smaug
arm64: tegra: Correct Tegra210 XUSB mailbox interrupt
arm64: tegra: Enable XUSB controller on Jetson TX1
arm64: tegra: Enable debug serial on Jetson TX1
arm64: tegra: Add Tegra210 XUSB controller
arm64: tegra: Add Tegra210 XUSB pad controller
arm64: tegra: Add DSI panel on Jetson TX1
arm64: tegra: p2597: Add SDMMC power supplies
arm64: tegra: Add PMIC support on Jetson TX1
Revert "ARM64: DTS: meson-gxbb: switch ethernet to real clock"
arm64: dts: hi6220: Add pl031 RTC support
arm64: dts: r8a7796/salvator-x: Enable watchdog timer
arm64: dts: r8a7796: Add RWDT node
arm64: dts: r8a7796: Use SYSC "always-on" PM Domain
...
This commit is contained in:
Linus Torvalds
@@ -30,6 +30,10 @@ Raspberry Pi 2 Model B
|
||||
Required root node properties:
|
||||
compatible = "raspberrypi,2-model-b", "brcm,bcm2836";
|
||||
|
||||
Raspberry Pi 3 Model B
|
||||
Required root node properties:
|
||||
compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
|
||||
|
||||
Raspberry Pi Compute Module
|
||||
Required root node properties:
|
||||
compatible = "raspberrypi,compute-module", "brcm,bcm2835";
|
||||
|
||||
@@ -10,6 +10,7 @@ compatible: Must contain one of
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"mediatek,mt6580"
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"mediatek,mt6589"
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"mediatek,mt6592"
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"mediatek,mt6755"
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"mediatek,mt6795"
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"mediatek,mt7623"
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"mediatek,mt8127"
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||||
@@ -31,6 +32,9 @@ Supported boards:
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- Evaluation board for MT6592:
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Required root node properties:
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||||
- compatible = "mediatek,mt6592-evb", "mediatek,mt6592";
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- Evaluation phone for MT6755(Helio P10):
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Required root node properties:
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- compatible = "mediatek,mt6755-evb", "mediatek,mt6755";
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- Evaluation board for MT6795(Helio X10):
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Required root node properties:
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- compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
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||||
@@ -29,6 +29,8 @@ SoCs:
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compatible = "renesas,r8a7794"
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- R-Car H3 (R8A77950)
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compatible = "renesas,r8a7795"
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- R-Car M3-W (R8A77960)
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compatible = "renesas,r8a7796"
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Boards:
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@@ -63,5 +65,7 @@ Boards:
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compatible = "renesas,porter", "renesas,r8a7791"
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- Salvator-X (RTP0RC7795SIPB0010S)
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compatible = "renesas,salvator-x", "renesas,r8a7795";
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- Salvator-X
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compatible = "renesas,salvator-x", "renesas,r8a7796";
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- SILK (RTP0RC7794LCB00011S)
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compatible = "renesas,silk", "renesas,r8a7794"
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@@ -10,6 +10,7 @@ PHYs.
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Required properties:
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||||
- compatible : compatible string, one of:
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- "allwinner,sun4i-a10-ahci"
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- "brcm,iproc-ahci"
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- "hisilicon,hisi-ahci"
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- "cavium,octeon-7130-ahci"
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- "ibm,476gtr-ahci"
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@@ -9,6 +9,7 @@ Required properties:
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"mediatek,mt8135-sysirq"
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"mediatek,mt8127-sysirq"
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"mediatek,mt6795-sysirq"
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"mediatek,mt6755-sysirq"
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"mediatek,mt6592-sysirq"
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"mediatek,mt6589-sysirq"
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"mediatek,mt6582-sysirq"
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@@ -59,8 +59,8 @@ Example:
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compatible = "apm,xgene-enet";
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status = "disabled";
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reg = <0x0 0x17020000 0x0 0xd100>,
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<0x0 0X17030000 0x0 0X400>,
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<0x0 0X10000000 0x0 0X200>;
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<0x0 0x17030000 0x0 0x400>,
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<0x0 0x10000000 0x0 0x200>;
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reg-names = "enet_csr", "ring_csr", "ring_cmd";
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interrupts = <0x0 0x3c 0x4>;
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port-id = <0>;
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@@ -24,6 +24,9 @@ Required properties:
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The first entry must be a link to the SCFG device node
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The second entry must be '0' or '1' based on physical PCIe controller index.
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This is used to get SCFG PEXN registers
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- dma-coherent: Indicates that the hardware IP block can ensure the coherency
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of the data transferred from/to the IP block. This can avoid the software
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cache flush/invalid actions, and improve the performance significantly.
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Example:
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@@ -38,6 +41,7 @@ Example:
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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dma-coherent;
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num-lanes = <4>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
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@@ -5,6 +5,8 @@ Required properties for the root node:
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"amlogic,meson8b-cbus-pinctrl"
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"amlogic,meson8-aobus-pinctrl"
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"amlogic,meson8b-aobus-pinctrl"
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"amlogic,meson-gxbb-periphs-pinctrl"
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"amlogic,meson-gxbb-aobus-pinctrl"
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- reg: address and size of registers controlling irq functionality
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=== GPIO sub-nodes ===
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@@ -0,0 +1,14 @@
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Amlogic Meson Random number generator
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=====================================
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Required properties:
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||||
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- compatible : should be "amlogic,meson-rng"
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- reg : Specifies base physical address and size of the registers.
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Example:
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rng {
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compatible = "amlogic,meson-rng";
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reg = <0x0 0xc8834000 0x0 0x4>;
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};
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@@ -6,6 +6,7 @@ Required properties:
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* "mediatek,mt6580-uart" for MT6580 compatible UARTS
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* "mediatek,mt6582-uart" for MT6582 compatible UARTS
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* "mediatek,mt6589-uart" for MT6589 compatible UARTS
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* "mediatek,mt6755-uart" for MT6755 compatible UARTS
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* "mediatek,mt6795-uart" for MT6795 compatible UARTS
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* "mediatek,mt7623-uart" for MT7623 compatible UARTS
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* "mediatek,mt8127-uart" for MT8127 compatible UARTS
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@@ -140,6 +140,12 @@ config ARCH_R8A7795
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help
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This enables support for the Renesas R-Car H3 SoC.
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config ARCH_R8A7796
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bool "Renesas R-Car M3-W SoC Platform"
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depends on ARCH_RENESAS
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help
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This enables support for the Renesas R-Car M3-W SoC.
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config ARCH_STRATIX10
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bool "Altera's Stratix 10 SoCFPGA Family"
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help
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||||
|
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@@ -45,6 +45,7 @@
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/dts-v1/;
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#include "meson-gxbb.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
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@@ -62,8 +63,27 @@
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
|
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};
|
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leds {
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compatible = "gpio-leds";
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blue {
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label = "c2:blue:alive";
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gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "heartbeat";
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default-state = "off";
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};
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};
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};
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&uart_AO {
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status = "okay";
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pinctrl-0 = <&uart_ao_a_pins>;
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pinctrl-names = "default";
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};
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ðmac {
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status = "okay";
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pinctrl-0 = <ð_pins>;
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pinctrl-names = "default";
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};
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||||
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@@ -62,4 +62,13 @@
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/* This UART is brought out to the DB9 connector */
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&uart_AO {
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status = "okay";
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pinctrl-0 = <&uart_ao_a_pins>;
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pinctrl-names = "default";
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};
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||||
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ðmac {
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||||
status = "okay";
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||||
pinctrl-0 = <ð_pins>;
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||||
pinctrl-names = "default";
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||||
};
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||||
|
||||
|
||||
@@ -56,4 +56,7 @@
|
||||
|
||||
&uart_AO {
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status = "okay";
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pinctrl-0 = <&uart_ao_a_pins>;
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pinctrl-names = "default";
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||||
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||||
};
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||||
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@@ -43,6 +43,8 @@
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||||
#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/meson-gxbb-gpio.h>
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#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
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/ {
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compatible = "amlogic,meson-gxbb";
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@@ -129,13 +131,35 @@
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
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||||
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reset: reset-controller@4404 {
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compatible = "amlogic,meson-gxbb-reset";
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reg = <0x0 0x04404 0x0 0x20>;
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#reset-cells = <1>;
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};
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uart_A: serial@84c0 {
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compatible = "amlogic,meson-uart";
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reg = <0x0 0x084c0 0x0 0x14>;
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reg = <0x0 0x84c0 0x0 0x14>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>;
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status = "disabled";
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};
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uart_B: serial@84dc {
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compatible = "amlogic,meson-uart";
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reg = <0x0 0x84dc 0x0 0x14>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>;
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status = "disabled";
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};
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uart_C: serial@8700 {
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compatible = "amlogic,meson-uart";
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reg = <0x0 0x8700 0x0 0x14>;
|
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interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>;
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status = "disabled";
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||||
};
|
||||
};
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|
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gic: interrupt-controller@c4301000 {
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@@ -158,6 +182,29 @@
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||||
#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
|
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|
||||
pinctrl_aobus: pinctrl@14 {
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compatible = "amlogic,meson-gxbb-aobus-pinctrl";
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#address-cells = <2>;
|
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#size-cells = <2>;
|
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ranges;
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|
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gpio_ao: bank@14 {
|
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reg = <0x0 0x00014 0x0 0x8>,
|
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<0x0 0x0002c 0x0 0x4>,
|
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<0x0 0x00024 0x0 0x8>;
|
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reg-names = "mux", "pull", "gpio";
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gpio-controller;
|
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#gpio-cells = <2>;
|
||||
};
|
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|
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uart_ao_a_pins: uart_ao_a {
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mux {
|
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groups = "uart_tx_ao_a", "uart_rx_ao_a";
|
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function = "uart_ao";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uart_AO: serial@4c0 {
|
||||
compatible = "amlogic,meson-uart";
|
||||
reg = <0x0 0x004c0 0x0 0x14>;
|
||||
@@ -167,6 +214,115 @@
|
||||
};
|
||||
};
|
||||
|
||||
periphs: periphs@c8834000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x0 0xc8834000 0x0 0x2000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
|
||||
|
||||
rng {
|
||||
compatible = "amlogic,meson-rng";
|
||||
reg = <0x0 0x0 0x0 0x4>;
|
||||
};
|
||||
|
||||
pinctrl_periphs: pinctrl@4b0 {
|
||||
compatible = "amlogic,meson-gxbb-periphs-pinctrl";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
gpio: bank@4b0 {
|
||||
reg = <0x0 0x004b0 0x0 0x28>,
|
||||
<0x0 0x004e8 0x0 0x14>,
|
||||
<0x0 0x00120 0x0 0x14>,
|
||||
<0x0 0x00430 0x0 0x40>;
|
||||
reg-names = "mux", "pull", "pull-enable", "gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
emmc_pins: emmc {
|
||||
mux {
|
||||
groups = "emmc_nand_d07",
|
||||
"emmc_cmd",
|
||||
"emmc_clk";
|
||||
function = "emmc";
|
||||
};
|
||||
};
|
||||
|
||||
sdcard_pins: sdcard {
|
||||
mux {
|
||||
groups = "sdcard_d0",
|
||||
"sdcard_d1",
|
||||
"sdcard_d2",
|
||||
"sdcard_d3",
|
||||
"sdcard_cmd",
|
||||
"sdcard_clk";
|
||||
function = "sdcard";
|
||||
};
|
||||
};
|
||||
|
||||
uart_a_pins: uart_a {
|
||||
mux {
|
||||
groups = "uart_tx_a",
|
||||
"uart_rx_a";
|
||||
function = "uart_a";
|
||||
};
|
||||
};
|
||||
|
||||
uart_b_pins: uart_b {
|
||||
mux {
|
||||
groups = "uart_tx_b",
|
||||
"uart_rx_b";
|
||||
function = "uart_b";
|
||||
};
|
||||
};
|
||||
|
||||
uart_c_pins: uart_c {
|
||||
mux {
|
||||
groups = "uart_tx_c",
|
||||
"uart_rx_c";
|
||||
function = "uart_c";
|
||||
};
|
||||
};
|
||||
|
||||
eth_pins: eth_c {
|
||||
mux {
|
||||
groups = "eth_mdio",
|
||||
"eth_mdc",
|
||||
"eth_clk_rx_clk",
|
||||
"eth_rx_dv",
|
||||
"eth_rxd0",
|
||||
"eth_rxd1",
|
||||
"eth_rxd2",
|
||||
"eth_rxd3",
|
||||
"eth_rgmii_tx_clk",
|
||||
"eth_tx_en",
|
||||
"eth_txd0",
|
||||
"eth_txd1",
|
||||
"eth_txd2",
|
||||
"eth_txd3";
|
||||
function = "eth";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hiubus: hiubus@c883c000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x0 0xc883c000 0x0 0x2000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
|
||||
|
||||
clkc: clock-controller@0 {
|
||||
compatible = "amlogic,gxbb-clkc";
|
||||
#clock-cells = <1>;
|
||||
reg = <0x0 0x0 0x0 0x3db>;
|
||||
};
|
||||
};
|
||||
|
||||
apb: apb@d0000000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x0 0xd0000000 0x0 0x200000>;
|
||||
@@ -174,5 +330,17 @@
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
|
||||
};
|
||||
|
||||
ethmac: ethernet@c9410000 {
|
||||
compatible = "amlogic,meson6-dwmac", "snps,dwmac";
|
||||
reg = <0x0 0xc9410000 0x0 0x10000
|
||||
0x0 0xc8834540 0x0 0x4>;
|
||||
interrupts = <0 8 1>;
|
||||
interrupt-names = "macirq";
|
||||
clocks = <&xtal>;
|
||||
clock-names = "stmmaceth";
|
||||
phy-mode = "rgmii";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -106,88 +106,88 @@
|
||||
interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
|
||||
ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */
|
||||
reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
|
||||
<0x0 0x780A0000 0x0 0x20000>, /* GIC CPU */
|
||||
<0x0 0x780C0000 0x0 0x10000>, /* GIC VCPU Control */
|
||||
<0x0 0x780E0000 0x0 0x20000>; /* GIC VCPU */
|
||||
v2m0: v2m@0x00000 {
|
||||
<0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */
|
||||
<0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */
|
||||
<0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */
|
||||
v2m0: v2m@00000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0x0 0x0 0x1000>;
|
||||
};
|
||||
v2m1: v2m@0x10000 {
|
||||
v2m1: v2m@10000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0x10000 0x0 0x1000>;
|
||||
};
|
||||
v2m2: v2m@0x20000 {
|
||||
v2m2: v2m@20000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0x20000 0x0 0x1000>;
|
||||
};
|
||||
v2m3: v2m@0x30000 {
|
||||
v2m3: v2m@30000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0x30000 0x0 0x1000>;
|
||||
};
|
||||
v2m4: v2m@0x40000 {
|
||||
v2m4: v2m@40000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0x40000 0x0 0x1000>;
|
||||
};
|
||||
v2m5: v2m@0x50000 {
|
||||
v2m5: v2m@50000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0x50000 0x0 0x1000>;
|
||||
};
|
||||
v2m6: v2m@0x60000 {
|
||||
v2m6: v2m@60000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0x60000 0x0 0x1000>;
|
||||
};
|
||||
v2m7: v2m@0x70000 {
|
||||
v2m7: v2m@70000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0x70000 0x0 0x1000>;
|
||||
};
|
||||
v2m8: v2m@0x80000 {
|
||||
v2m8: v2m@80000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0x80000 0x0 0x1000>;
|
||||
};
|
||||
v2m9: v2m@0x90000 {
|
||||
v2m9: v2m@90000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0x90000 0x0 0x1000>;
|
||||
};
|
||||
v2m10: v2m@0xA0000 {
|
||||
v2m10: v2m@a0000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0xA0000 0x0 0x1000>;
|
||||
reg = <0x0 0xa0000 0x0 0x1000>;
|
||||
};
|
||||
v2m11: v2m@0xB0000 {
|
||||
v2m11: v2m@b0000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0xB0000 0x0 0x1000>;
|
||||
reg = <0x0 0xb0000 0x0 0x1000>;
|
||||
};
|
||||
v2m12: v2m@0xC0000 {
|
||||
v2m12: v2m@c0000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0xC0000 0x0 0x1000>;
|
||||
reg = <0x0 0xc0000 0x0 0x1000>;
|
||||
};
|
||||
v2m13: v2m@0xD0000 {
|
||||
v2m13: v2m@d0000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0xD0000 0x0 0x1000>;
|
||||
reg = <0x0 0xd0000 0x0 0x1000>;
|
||||
};
|
||||
v2m14: v2m@0xE0000 {
|
||||
v2m14: v2m@e0000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0xE0000 0x0 0x1000>;
|
||||
reg = <0x0 0xe0000 0x0 0x1000>;
|
||||
};
|
||||
v2m15: v2m@0xF0000 {
|
||||
v2m15: v2m@f0000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0xF0000 0x0 0x1000>;
|
||||
reg = <0x0 0xf0000 0x0 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -198,10 +198,10 @@
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <1 0 0xff04>, /* Secure Phys IRQ */
|
||||
<1 13 0xff04>, /* Non-secure Phys IRQ */
|
||||
<1 14 0xff04>, /* Virt IRQ */
|
||||
<1 15 0xff04>; /* Hyp IRQ */
|
||||
interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
|
||||
<1 13 0xff08>, /* Non-secure Phys IRQ */
|
||||
<1 14 0xff08>, /* Virt IRQ */
|
||||
<1 15 0xff08>; /* Hyp IRQ */
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
|
||||
@@ -637,8 +637,8 @@
|
||||
compatible = "apm,xgene2-sgenet";
|
||||
status = "disabled";
|
||||
reg = <0x0 0x1f610000 0x0 0xd100>,
|
||||
<0x0 0x1f600000 0x0 0Xd100>,
|
||||
<0x0 0x20000000 0x0 0X20000>;
|
||||
<0x0 0x1f600000 0x0 0xd100>,
|
||||
<0x0 0x20000000 0x0 0x20000>;
|
||||
interrupts = <0 96 4>,
|
||||
<0 97 4>;
|
||||
dma-coherent;
|
||||
@@ -652,8 +652,8 @@
|
||||
compatible = "apm,xgene2-xgenet";
|
||||
status = "disabled";
|
||||
reg = <0x0 0x1f620000 0x0 0x10000>,
|
||||
<0x0 0x1f600000 0x0 0Xd100>,
|
||||
<0x0 0x20000000 0x0 0X220000>;
|
||||
<0x0 0x1f600000 0x0 0xd100>,
|
||||
<0x0 0x20000000 0x0 0x220000>;
|
||||
interrupts = <0 108 4>,
|
||||
<0 109 4>,
|
||||
<0 110 4>,
|
||||
@@ -693,7 +693,7 @@
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x0 0x10640000 0x0 0x1000>;
|
||||
interrupts = <0 0x3A 0x4>;
|
||||
interrupts = <0 0x3a 0x4>;
|
||||
clocks = <&i2c4clk 0>;
|
||||
bus_num = <4>;
|
||||
};
|
||||
|
||||
@@ -199,16 +199,6 @@
|
||||
clock-output-names = "sdioclk";
|
||||
};
|
||||
|
||||
qmlclk: qmlclk {
|
||||
compatible = "apm,xgene-device-clock";
|
||||
#clock-cells = <1>;
|
||||
clocks = <&socplldiv2 0>;
|
||||
clock-names = "qmlclk";
|
||||
reg = <0x0 0x1703C000 0x0 0x1000>;
|
||||
reg-names = "csr-reg";
|
||||
clock-output-names = "qmlclk";
|
||||
};
|
||||
|
||||
ethclk: ethclk {
|
||||
compatible = "apm,xgene-device-clock";
|
||||
#clock-cells = <1>;
|
||||
@@ -226,7 +216,7 @@
|
||||
compatible = "apm,xgene-device-clock";
|
||||
#clock-cells = <1>;
|
||||
clocks = <ðclk 0>;
|
||||
reg = <0x0 0x1702C000 0x0 0x1000>;
|
||||
reg = <0x0 0x1702c000 0x0 0x1000>;
|
||||
reg-names = "csr-reg";
|
||||
clock-output-names = "menetclk";
|
||||
};
|
||||
@@ -924,8 +914,8 @@
|
||||
compatible = "apm,xgene-enet";
|
||||
status = "disabled";
|
||||
reg = <0x0 0x17020000 0x0 0xd100>,
|
||||
<0x0 0X17030000 0x0 0Xc300>,
|
||||
<0x0 0X10000000 0x0 0X200>;
|
||||
<0x0 0x17030000 0x0 0xc300>,
|
||||
<0x0 0x10000000 0x0 0x200>;
|
||||
reg-names = "enet_csr", "ring_csr", "ring_cmd";
|
||||
interrupts = <0x0 0x3c 0x4>;
|
||||
dma-coherent;
|
||||
@@ -950,11 +940,11 @@
|
||||
compatible = "apm,xgene1-sgenet";
|
||||
status = "disabled";
|
||||
reg = <0x0 0x1f210000 0x0 0xd100>,
|
||||
<0x0 0x1f200000 0x0 0Xc300>,
|
||||
<0x0 0x1B000000 0x0 0X200>;
|
||||
<0x0 0x1f200000 0x0 0xc300>,
|
||||
<0x0 0x1b000000 0x0 0x200>;
|
||||
reg-names = "enet_csr", "ring_csr", "ring_cmd";
|
||||
interrupts = <0x0 0xA0 0x4>,
|
||||
<0x0 0xA1 0x4>;
|
||||
interrupts = <0x0 0xa0 0x4>,
|
||||
<0x0 0xa1 0x4>;
|
||||
dma-coherent;
|
||||
clocks = <&sge0clk 0>;
|
||||
local-mac-address = [00 00 00 00 00 00];
|
||||
@@ -966,11 +956,11 @@
|
||||
compatible = "apm,xgene1-sgenet";
|
||||
status = "disabled";
|
||||
reg = <0x0 0x1f210030 0x0 0xd100>,
|
||||
<0x0 0x1f200000 0x0 0Xc300>,
|
||||
<0x0 0x1B000000 0x0 0X8000>;
|
||||
<0x0 0x1f200000 0x0 0xc300>,
|
||||
<0x0 0x1b000000 0x0 0x8000>;
|
||||
reg-names = "enet_csr", "ring_csr", "ring_cmd";
|
||||
interrupts = <0x0 0xAC 0x4>,
|
||||
<0x0 0xAD 0x4>;
|
||||
interrupts = <0x0 0xac 0x4>,
|
||||
<0x0 0xad 0x4>;
|
||||
port-id = <1>;
|
||||
dma-coherent;
|
||||
local-mac-address = [00 00 00 00 00 00];
|
||||
@@ -982,8 +972,8 @@
|
||||
compatible = "apm,xgene1-xgenet";
|
||||
status = "disabled";
|
||||
reg = <0x0 0x1f610000 0x0 0xd100>,
|
||||
<0x0 0x1f600000 0x0 0Xc300>,
|
||||
<0x0 0x18000000 0x0 0X200>;
|
||||
<0x0 0x1f600000 0x0 0xc300>,
|
||||
<0x0 0x18000000 0x0 0x200>;
|
||||
reg-names = "enet_csr", "ring_csr", "ring_cmd";
|
||||
interrupts = <0x0 0x60 0x4>,
|
||||
<0x0 0x61 0x4>,
|
||||
@@ -1005,11 +995,11 @@
|
||||
compatible = "apm,xgene1-xgenet";
|
||||
status = "disabled";
|
||||
reg = <0x0 0x1f620000 0x0 0xd100>,
|
||||
<0x0 0x1f600000 0x0 0Xc300>,
|
||||
<0x0 0x18000000 0x0 0X8000>;
|
||||
<0x0 0x1f600000 0x0 0xc300>,
|
||||
<0x0 0x18000000 0x0 0x8000>;
|
||||
reg-names = "enet_csr", "ring_csr", "ring_cmd";
|
||||
interrupts = <0x0 0x6C 0x4>,
|
||||
<0x0 0x6D 0x4>;
|
||||
interrupts = <0x0 0x6c 0x4>,
|
||||
<0x0 0x6d 0x4>;
|
||||
port-id = <1>;
|
||||
dma-coherent;
|
||||
clocks = <&xge1clk 0>;
|
||||
|
||||
@@ -56,6 +56,315 @@
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Juno TRMs specify the size for these coresight components as 64K.
|
||||
* The actual size is just 4K though 64K is reserved. Access to the
|
||||
* unmapped reserved region results in a DECERR response.
|
||||
*/
|
||||
etf@20010000 {
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0 0x20010000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* input port */
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
etf_in_port: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&main_funnel_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
/* output port */
|
||||
port@1 {
|
||||
reg = <0>;
|
||||
etf_out_port: endpoint {
|
||||
remote-endpoint = <&replicator_in_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tpiu@20030000 {
|
||||
compatible = "arm,coresight-tpiu", "arm,primecell";
|
||||
reg = <0 0x20030000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
port {
|
||||
tpiu_in_port: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&replicator_out_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
main-funnel@20040000 {
|
||||
compatible = "arm,coresight-funnel", "arm,primecell";
|
||||
reg = <0 0x20040000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
main_funnel_out_port: endpoint {
|
||||
remote-endpoint = <&etf_in_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <0>;
|
||||
main_funnel_in_port0: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&cluster0_funnel_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <1>;
|
||||
main_funnel_in_port1: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&cluster1_funnel_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
etr@20070000 {
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0 0x20070000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
port {
|
||||
etr_in_port: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&replicator_out_port1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm0: etm@22040000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x22040000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
port {
|
||||
cluster0_etm0_out_port: endpoint {
|
||||
remote-endpoint = <&cluster0_funnel_in_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cluster0-funnel@220c0000 {
|
||||
compatible = "arm,coresight-funnel", "arm,primecell";
|
||||
reg = <0 0x220c0000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
cluster0_funnel_out_port: endpoint {
|
||||
remote-endpoint = <&main_funnel_in_port0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <0>;
|
||||
cluster0_funnel_in_port0: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&cluster0_etm0_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <1>;
|
||||
cluster0_funnel_in_port1: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&cluster0_etm1_out_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm1: etm@22140000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x22140000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
port {
|
||||
cluster0_etm1_out_port: endpoint {
|
||||
remote-endpoint = <&cluster0_funnel_in_port1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm2: etm@23040000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x23040000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
port {
|
||||
cluster1_etm0_out_port: endpoint {
|
||||
remote-endpoint = <&cluster1_funnel_in_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cluster1-funnel@230c0000 {
|
||||
compatible = "arm,coresight-funnel", "arm,primecell";
|
||||
reg = <0 0x230c0000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
cluster1_funnel_out_port: endpoint {
|
||||
remote-endpoint = <&main_funnel_in_port1>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <0>;
|
||||
cluster1_funnel_in_port0: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&cluster1_etm0_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <1>;
|
||||
cluster1_funnel_in_port1: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&cluster1_etm1_out_port>;
|
||||
};
|
||||
};
|
||||
port@3 {
|
||||
reg = <2>;
|
||||
cluster1_funnel_in_port2: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&cluster1_etm2_out_port>;
|
||||
};
|
||||
};
|
||||
port@4 {
|
||||
reg = <3>;
|
||||
cluster1_funnel_in_port3: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&cluster1_etm3_out_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm3: etm@23140000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x23140000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
port {
|
||||
cluster1_etm1_out_port: endpoint {
|
||||
remote-endpoint = <&cluster1_funnel_in_port1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm4: etm@23240000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x23240000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
port {
|
||||
cluster1_etm2_out_port: endpoint {
|
||||
remote-endpoint = <&cluster1_funnel_in_port2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm5: etm@23340000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x23340000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
port {
|
||||
cluster1_etm3_out_port: endpoint {
|
||||
remote-endpoint = <&cluster1_funnel_in_port3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
coresight-replicator {
|
||||
/*
|
||||
* Non-configurable replicators don't show up on the
|
||||
* AMBA bus. As such no need to add "arm,primecell".
|
||||
*/
|
||||
compatible = "arm,coresight-replicator";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* replicator output ports */
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
replicator_out_port0: endpoint {
|
||||
remote-endpoint = <&tpiu_in_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
replicator_out_port1: endpoint {
|
||||
remote-endpoint = <&etr_in_port>;
|
||||
};
|
||||
};
|
||||
|
||||
/* replicator input port */
|
||||
port@2 {
|
||||
reg = <0>;
|
||||
replicator_in_port0: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&etf_out_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sram: sram@2e000000 {
|
||||
compatible = "arm,juno-sram-ns", "mmio-sram";
|
||||
reg = <0x0 0x2e000000 0x0 0x8000>;
|
||||
@@ -119,12 +428,60 @@
|
||||
};
|
||||
};
|
||||
|
||||
scpi_devpd: scpi-power-domains {
|
||||
compatible = "arm,scpi-power-domains";
|
||||
num-domains = <2>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
scpi_sensors0: sensors {
|
||||
compatible = "arm,scpi-sensors";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
pmic {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <100>;
|
||||
thermal-sensors = <&scpi_sensors0 0>;
|
||||
};
|
||||
|
||||
soc {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <100>;
|
||||
thermal-sensors = <&scpi_sensors0 3>;
|
||||
};
|
||||
|
||||
big_cluster_thermal_zone: big_cluster {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <100>;
|
||||
thermal-sensors = <&scpi_sensors0 21>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
little_cluster_thermal_zone: little_cluster {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <100>;
|
||||
thermal-sensors = <&scpi_sensors0 22>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpu0_thermal_zone: gpu0 {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <100>;
|
||||
thermal-sensors = <&scpi_sensors0 23>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpu1_thermal_zone: gpu1 {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <100>;
|
||||
thermal-sensors = <&scpi_sensors0 24>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "juno-clocks.dtsi"
|
||||
|
||||
dma@7ff00000 {
|
||||
|
||||
@@ -181,3 +181,43 @@
|
||||
&pcie_ctlr {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&etm0 {
|
||||
cpu = <&A57_0>;
|
||||
};
|
||||
|
||||
&etm1 {
|
||||
cpu = <&A57_1>;
|
||||
};
|
||||
|
||||
&etm2 {
|
||||
cpu = <&A53_0>;
|
||||
};
|
||||
|
||||
&etm3 {
|
||||
cpu = <&A53_1>;
|
||||
};
|
||||
|
||||
&etm4 {
|
||||
cpu = <&A53_2>;
|
||||
};
|
||||
|
||||
&etm5 {
|
||||
cpu = <&A53_3>;
|
||||
};
|
||||
|
||||
&big_cluster_thermal_zone {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&little_cluster_thermal_zone {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu0_thermal_zone {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu1_thermal_zone {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -181,3 +181,43 @@
|
||||
&pcie_ctlr {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&etm0 {
|
||||
cpu = <&A72_0>;
|
||||
};
|
||||
|
||||
&etm1 {
|
||||
cpu = <&A72_1>;
|
||||
};
|
||||
|
||||
&etm2 {
|
||||
cpu = <&A53_0>;
|
||||
};
|
||||
|
||||
&etm3 {
|
||||
cpu = <&A53_1>;
|
||||
};
|
||||
|
||||
&etm4 {
|
||||
cpu = <&A53_2>;
|
||||
};
|
||||
|
||||
&etm5 {
|
||||
cpu = <&A53_3>;
|
||||
};
|
||||
|
||||
&big_cluster_thermal_zone {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&little_cluster_thermal_zone {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu0_thermal_zone {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu1_thermal_zone {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user