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Merge tag 'usb-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
Pull USB updates from Greg KH: "Here's the big set of USB and PHY patches for 3.19-rc1. The normal churn in the USB gadget area is in here, as well as xhci and other individual USB driver updates. The PHY tree is also in here, as there were dependancies on the USB tree. All of these have been in linux-next" * tag 'usb-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (351 commits) arm: omap3: twl: remove usb phy init data usbip: fix error handling in stub_probe() usb: gadget: udc: missing curly braces USB: mos7720: delete some unneeded code wusb: replace memset by memzero_explicit usbip: remove unneeded structure usb: xhci: fix comment for PORT_DEV_REMOVE xhci: don't use the same variable for stopped and halted rings current TD xhci: clear extra bits from slot context when setting max exit latency xhci: cleanup finish_td function USB: adutux: NULL dereferences on disconnect usb: chipidea: fix platform_no_drv_owner.cocci warnings usb: chipidea: Fixed a few typos in comments Documentation: bindings: add doc for the USB2 ChipIdea USB driver usb: chipidea: add a usb2 driver for ci13xxx usb: chipidea: fix phy handling usb: chipidea: remove duplicate dev_set_drvdata for host_start usb: chipidea: parameter 'mode' isn't needed for hw_device_reset usb: chipidea: add controller reset API usb: chipidea: remove flag CI_HDRC_REQUIRE_TRANSCEIVER ...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,93 @@
|
||||
What: /sys/class/udc/<udc>/a_alt_hnp_support
|
||||
Date: June 2011
|
||||
KernelVersion: 3.1
|
||||
Contact: Felipe Balbi <balbi@kernel.org>
|
||||
Description:
|
||||
Indicates if an OTG A-Host supports HNP at an alternate port.
|
||||
Users:
|
||||
|
||||
What: /sys/class/udc/<udc>/a_hnp_support
|
||||
Date: June 2011
|
||||
KernelVersion: 3.1
|
||||
Contact: Felipe Balbi <balbi@kernel.org>
|
||||
Description:
|
||||
Indicates if an OTG A-Host supports HNP at this port.
|
||||
Users:
|
||||
|
||||
What: /sys/class/udc/<udc>/b_hnp_enable
|
||||
Date: June 2011
|
||||
KernelVersion: 3.1
|
||||
Contact: Felipe Balbi <balbi@kernel.org>
|
||||
Description:
|
||||
Indicates if an OTG A-Host enabled HNP support.
|
||||
Users:
|
||||
|
||||
What: /sys/class/udc/<udc>/current_speed
|
||||
Date: June 2011
|
||||
KernelVersion: 3.1
|
||||
Contact: Felipe Balbi <balbi@kernel.org>
|
||||
Description:
|
||||
Indicates the current negotiated speed at this port.
|
||||
Users:
|
||||
|
||||
What: /sys/class/udc/<udc>/is_a_peripheral
|
||||
Date: June 2011
|
||||
KernelVersion: 3.1
|
||||
Contact: Felipe Balbi <balbi@kernel.org>
|
||||
Description:
|
||||
Indicates that this port is the default Host on an OTG session
|
||||
but HNP was used to switch roles.
|
||||
Users:
|
||||
|
||||
What: /sys/class/udc/<udc>/is_otg
|
||||
Date: June 2011
|
||||
KernelVersion: 3.1
|
||||
Contact: Felipe Balbi <balbi@kernel.org>
|
||||
Description:
|
||||
Indicates that this port support OTG.
|
||||
Users:
|
||||
|
||||
What: /sys/class/udc/<udc>/maximum_speed
|
||||
Date: June 2011
|
||||
KernelVersion: 3.1
|
||||
Contact: Felipe Balbi <balbi@kernel.org>
|
||||
Description:
|
||||
Indicates the maximum USB speed supported by this port.
|
||||
Users:
|
||||
|
||||
What: /sys/class/udc/<udc>/maximum_speed
|
||||
Date: June 2011
|
||||
KernelVersion: 3.1
|
||||
Contact: Felipe Balbi <balbi@kernel.org>
|
||||
Description:
|
||||
Indicates the maximum USB speed supported by this port.
|
||||
Users:
|
||||
|
||||
What: /sys/class/udc/<udc>/soft_connect
|
||||
Date: June 2011
|
||||
KernelVersion: 3.1
|
||||
Contact: Felipe Balbi <balbi@kernel.org>
|
||||
Description:
|
||||
Allows users to disconnect data pullup resistors thus causing a
|
||||
logical disconnection from the USB Host.
|
||||
Users:
|
||||
|
||||
What: /sys/class/udc/<udc>/srp
|
||||
Date: June 2011
|
||||
KernelVersion: 3.1
|
||||
Contact: Felipe Balbi <balbi@kernel.org>
|
||||
Description:
|
||||
Allows users to manually start Session Request Protocol.
|
||||
Users:
|
||||
|
||||
What: /sys/class/udc/<udc>/state
|
||||
Date: June 2011
|
||||
KernelVersion: 3.1
|
||||
Contact: Felipe Balbi <balbi@kernel.org>
|
||||
Description:
|
||||
Indicates current state of the USB Device Controller. Valid
|
||||
states are: 'not-attached', 'attached', 'powered',
|
||||
'reconnecting', 'unauthenticated', 'default', 'addressed',
|
||||
'configured', and 'suspended'; however not all USB Device
|
||||
Controllers support reporting all states.
|
||||
Users:
|
||||
@@ -0,0 +1,11 @@
|
||||
What: /config/usb-gadget/gadget/functions/hid.name
|
||||
Date: Nov 2014
|
||||
KernelVersion: 3.19
|
||||
Description:
|
||||
The attributes:
|
||||
|
||||
protocol - HID protocol to use
|
||||
report_desc - blob corresponding to HID report descriptors
|
||||
except the data passed through /dev/hidg<N>
|
||||
report_length - HID report length
|
||||
subclass - HID device subclass to use
|
||||
@@ -0,0 +1,12 @@
|
||||
What: /config/usb-gadget/gadget/functions/midi.name
|
||||
Date: Nov 2014
|
||||
KernelVersion: 3.19
|
||||
Description:
|
||||
The attributes:
|
||||
|
||||
index - index value for the USB MIDI adapter
|
||||
id - ID string for the USB MIDI adapter
|
||||
buflen - MIDI buffer length
|
||||
qlen - USB read request queue length
|
||||
in_ports - number of MIDI input ports
|
||||
out_ports - number of MIDI output ports
|
||||
@@ -6,11 +6,17 @@ Required Properties:
|
||||
- interrupts : Interrupt controller is using
|
||||
- nr-ports : Number of SATA ports in use.
|
||||
|
||||
Optional Properties:
|
||||
- phys : List of phandles to sata phys
|
||||
- phy-names : Should be "0", "1", etc, one number per phandle
|
||||
|
||||
Example:
|
||||
|
||||
sata@80000 {
|
||||
compatible = "marvell,orion-sata";
|
||||
reg = <0x80000 0x5000>;
|
||||
interrupts = <21>;
|
||||
phys = <&sata_phy0>, <&sata_phy1>;
|
||||
phy-names = "0", "1";
|
||||
nr-ports = <2>;
|
||||
}
|
||||
|
||||
@@ -2,7 +2,9 @@ Berlin SATA PHY
|
||||
---------------
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "marvell,berlin2q-sata-phy"
|
||||
- compatible: should be one of
|
||||
"marvell,berlin2-sata-phy"
|
||||
"marvell,berlin2q-sata-phy"
|
||||
- address-cells: should be 1
|
||||
- size-cells: should be 0
|
||||
- phy-cells: from the generic PHY bindings, must be 1
|
||||
|
||||
@@ -0,0 +1,16 @@
|
||||
* Marvell Berlin USB PHY
|
||||
|
||||
Required properties:
|
||||
- compatible: "marvell,berlin2-usb-phy" or "marvell,berlin2cd-usb-phy"
|
||||
- reg: base address and length of the registers
|
||||
- #phys-cells: should be 0
|
||||
- resets: reference to the reset controller
|
||||
|
||||
Example:
|
||||
|
||||
usb-phy@f774000 {
|
||||
compatible = "marvell,berlin2-usb-phy";
|
||||
reg = <0xf774000 0x128>;
|
||||
#phy-cells = <0>;
|
||||
resets = <&chip 0x104 14>;
|
||||
};
|
||||
@@ -0,0 +1,128 @@
|
||||
STMicroelectronics STi MIPHY28LP PHY binding
|
||||
============================================
|
||||
|
||||
This binding describes a miphy device that is used to control PHY hardware
|
||||
for SATA, PCIe or USB3.
|
||||
|
||||
Required properties (controller (parent) node):
|
||||
- compatible : Should be "st,miphy28lp-phy".
|
||||
- st,syscfg : Should be a phandle of the system configuration register group
|
||||
which contain the SATA, PCIe or USB3 mode setting bits.
|
||||
|
||||
Required nodes : A sub-node is required for each channel the controller
|
||||
provides. Address range information including the usual
|
||||
'reg' and 'reg-names' properties are used inside these
|
||||
nodes to describe the controller's topology. These nodes
|
||||
are translated by the driver's .xlate() function.
|
||||
|
||||
Required properties (port (child) node):
|
||||
- #phy-cells : Should be 1 (See second example)
|
||||
Cell after port phandle is device type from:
|
||||
- PHY_TYPE_SATA
|
||||
- PHY_TYPE_PCI
|
||||
- PHY_TYPE_USB3
|
||||
- reg : Address and length of the register set for the device.
|
||||
- reg-names : The names of the register addresses corresponding to the registers
|
||||
filled in "reg". It can also contain the offset of the system configuration
|
||||
registers used as glue-logic to setup the device for SATA/PCIe or USB3
|
||||
devices.
|
||||
- resets : phandle to the parent reset controller.
|
||||
- reset-names : Associated name must be "miphy-sw-rst".
|
||||
|
||||
Optional properties (port (child) node):
|
||||
- st,osc-rdy : to check the MIPHY0_OSC_RDY status in the glue-logic. This
|
||||
is not available in all the MiPHY. For example, for STiH407, only the
|
||||
MiPHY0 has this bit.
|
||||
- st,osc-force-ext : to select the external oscillator. This can change from
|
||||
different MiPHY inside the same SoC.
|
||||
- st,sata_gen : to select which SATA_SPDMODE has to be set in the SATA system config
|
||||
register.
|
||||
- st,px_rx_pol_inv : to invert polarity of RXn/RXp (respectively negative line and positive
|
||||
line).
|
||||
- st,scc-on : enable ssc to reduce effects of EMI (only for sata or PCIe).
|
||||
- st,tx-impedance-comp : to compensate tx impedance avoiding out of range values.
|
||||
|
||||
example:
|
||||
|
||||
miphy28lp_phy: miphy28lp@9b22000 {
|
||||
compatible = "st,miphy28lp-phy";
|
||||
st,syscfg = <&syscfg_core>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
phy_port0: port@9b22000 {
|
||||
reg = <0x9b22000 0xff>,
|
||||
<0x9b09000 0xff>,
|
||||
<0x9b04000 0xff>,
|
||||
<0x114 0x4>, /* sysctrl MiPHY cntrl */
|
||||
<0x818 0x4>, /* sysctrl MiPHY status*/
|
||||
<0xe0 0x4>, /* sysctrl PCIe */
|
||||
<0xec 0x4>; /* sysctrl SATA */
|
||||
reg-names = "sata-up",
|
||||
"pcie-up",
|
||||
"pipew",
|
||||
"miphy-ctrl-glue",
|
||||
"miphy-status-glue",
|
||||
"pcie-glue",
|
||||
"sata-glue";
|
||||
#phy-cells = <1>;
|
||||
st,osc-rdy;
|
||||
reset-names = "miphy-sw-rst";
|
||||
resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
|
||||
};
|
||||
|
||||
phy_port1: port@9b2a000 {
|
||||
reg = <0x9b2a000 0xff>,
|
||||
<0x9b19000 0xff>,
|
||||
<0x9b14000 0xff>,
|
||||
<0x118 0x4>,
|
||||
<0x81c 0x4>,
|
||||
<0xe4 0x4>,
|
||||
<0xf0 0x4>;
|
||||
reg-names = "sata-up",
|
||||
"pcie-up",
|
||||
"pipew",
|
||||
"miphy-ctrl-glue",
|
||||
"miphy-status-glue",
|
||||
"pcie-glue",
|
||||
"sata-glue";
|
||||
#phy-cells = <1>;
|
||||
st,osc-force-ext;
|
||||
reset-names = "miphy-sw-rst";
|
||||
resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
|
||||
};
|
||||
|
||||
phy_port2: port@8f95000 {
|
||||
reg = <0x8f95000 0xff>,
|
||||
<0x8f90000 0xff>,
|
||||
<0x11c 0x4>,
|
||||
<0x820 0x4>;
|
||||
reg-names = "pipew",
|
||||
"usb3-up",
|
||||
"miphy-ctrl-glue",
|
||||
"miphy-status-glue";
|
||||
#phy-cells = <1>;
|
||||
reset-names = "miphy-sw-rst";
|
||||
resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Specifying phy control of devices
|
||||
=================================
|
||||
|
||||
Device nodes should specify the configuration required in their "phys"
|
||||
property, containing a phandle to the miphy device node and an index
|
||||
specifying which configuration to use, as described in phy-bindings.txt.
|
||||
|
||||
example:
|
||||
sata0: sata@9b20000 {
|
||||
...
|
||||
phys = <&phy_port0 PHY_TYPE_SATA>;
|
||||
...
|
||||
};
|
||||
|
||||
Macro definitions for the supported miphy configuration can be found in:
|
||||
|
||||
include/dt-bindings/phy/phy-miphy28lp.h
|
||||
@@ -0,0 +1,43 @@
|
||||
* Marvell MVEBU SATA PHY
|
||||
|
||||
Power control for the SATA phy found on Marvell MVEBU SoCs.
|
||||
|
||||
This document extends the binding described in phy-bindings.txt
|
||||
|
||||
Required properties :
|
||||
|
||||
- reg : Offset and length of the register set for the SATA device
|
||||
- compatible : Should be "marvell,mvebu-sata-phy"
|
||||
- clocks : phandle of clock and specifier that supplies the device
|
||||
- clock-names : Should be "sata"
|
||||
|
||||
Example:
|
||||
sata-phy@84000 {
|
||||
compatible = "marvell,mvebu-sata-phy";
|
||||
reg = <0x84000 0x0334>;
|
||||
clocks = <&gate_clk 15>;
|
||||
clock-names = "sata";
|
||||
#phy-cells = <0>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
Armada 375 USB cluster
|
||||
----------------------
|
||||
|
||||
Armada 375 comes with an USB2 host and device controller and an USB3
|
||||
controller. The USB cluster control register allows to manage common
|
||||
features of both USB controllers.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: "marvell,armada-375-usb-cluster"
|
||||
- reg: Should contain usb cluster register location and length.
|
||||
- #phy-cells : from the generic phy bindings, must be 1. Possible
|
||||
values are 1 (USB2), 2 (USB3).
|
||||
|
||||
Example:
|
||||
usbcluster: usb-cluster@18400 {
|
||||
compatible = "marvell,armada-375-usb-cluster";
|
||||
reg = <0x18400 0x4>;
|
||||
#phy-cells = <1>
|
||||
};
|
||||
@@ -128,6 +128,7 @@ Required properties:
|
||||
- compatible : Should be set to one of the following supported values:
|
||||
- "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
|
||||
- "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
|
||||
- "samsung,exynos7-usbdrd-phy" - for exynos7 SoC.
|
||||
- reg : Register offset and length of USB DRD PHY register set;
|
||||
- clocks: Clock IDs array as required by the controller
|
||||
- clock-names: names of clocks correseponding to IDs in the clock property;
|
||||
@@ -138,6 +139,11 @@ Required properties:
|
||||
PHY operations, associated by phy name. It is used to
|
||||
determine bit values for clock settings register.
|
||||
For Exynos5420 this is given as 'sclk_usbphy30' in CMU.
|
||||
- optional clocks: Exynos7 SoC has now following additional
|
||||
gate clocks available:
|
||||
- phy_pipe: for PIPE3 phy
|
||||
- phy_utmi: for UTMI+ phy
|
||||
- itp: for ITP generation
|
||||
- samsung,pmu-syscon: phandle for PMU system controller interface, used to
|
||||
control pmu registers for power isolation.
|
||||
- #phy-cells : from the generic PHY bindings, must be 1;
|
||||
|
||||
@@ -0,0 +1,24 @@
|
||||
* USB2 ChipIdea USB controller for ci13xxx
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "chipidea,usb2"
|
||||
- reg: base address and length of the registers
|
||||
- interrupts: interrupt for the USB controller
|
||||
|
||||
Optional properties:
|
||||
- clocks: reference to the USB clock
|
||||
- phys: reference to the USB PHY
|
||||
- phy-names: should be "usb-phy"
|
||||
- vbus-supply: reference to the VBUS regulator
|
||||
|
||||
Example:
|
||||
|
||||
usb@f7ed0000 {
|
||||
compatible = "chipidea,usb2";
|
||||
reg = <0xf7ed0000 0x10000>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&chip CLKID_USB0>;
|
||||
phys = <&usb_phy0>;
|
||||
phy-names = "usb-phy";
|
||||
vbus-supply = <®_usb0_vbus>;
|
||||
};
|
||||
@@ -14,6 +14,29 @@ Optional properties:
|
||||
- phys: from the *Generic PHY* bindings
|
||||
- phy-names: from the *Generic PHY* bindings
|
||||
- tx-fifo-resize: determines if the FIFO *has* to be reallocated.
|
||||
- snps,disable_scramble_quirk: true when SW should disable data scrambling.
|
||||
Only really useful for FPGA builds.
|
||||
- snps,has-lpm-erratum: true when DWC3 was configured with LPM Erratum enabled
|
||||
- snps,lpm-nyet-threshold: LPM NYET threshold
|
||||
- snps,u2exit_lfps_quirk: set if we want to enable u2exit lfps quirk
|
||||
- snps,u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
|
||||
- snps,req_p1p2p3_quirk: when set, the core will always request for
|
||||
P1/P2/P3 transition sequence.
|
||||
- snps,del_p1p2p3_quirk: when set core will delay P1/P2/P3 until a certain
|
||||
amount of 8B10B errors occur.
|
||||
- snps,del_phy_power_chg_quirk: when set core will delay PHY power change
|
||||
from P0 to P1/P2/P3.
|
||||
- snps,lfps_filter_quirk: when set core will filter LFPS reception.
|
||||
- snps,rx_detect_poll_quirk: when set core will disable a 400us delay to start
|
||||
Polling LFPS after RX.Detect.
|
||||
- snps,tx_de_emphasis_quirk: when set core will set Tx de-emphasis value.
|
||||
- snps,tx_de_emphasis: the value driven to the PHY is controlled by the
|
||||
LTSSM during USB3 Compliance mode.
|
||||
- snps,dis_u3_susphy_quirk: when set core will disable USB3 suspend phy.
|
||||
- snps,dis_u2_susphy_quirk: when set core will disable USB2 suspend phy.
|
||||
- snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
|
||||
utmi_l1_suspend_n, false when asserts utmi_sleep_n
|
||||
- snps,hird-threshold: HIRD threshold
|
||||
|
||||
This is usually a subnode to DWC3 glue to which it is connected.
|
||||
|
||||
|
||||
@@ -82,8 +82,10 @@ Example:
|
||||
|
||||
DWC3
|
||||
Required properties:
|
||||
- compatible: should be "samsung,exynos5250-dwusb3" for USB 3.0 DWC3
|
||||
controller.
|
||||
- compatible: should be one of the following -
|
||||
"samsung,exynos5250-dwusb3": for USB 3.0 DWC3 controller on
|
||||
Exynos5250/5420.
|
||||
"samsung,exynos7-dwusb3": for USB 3.0 DWC3 controller on Exynos7.
|
||||
- #address-cells, #size-cells : should be '1' if the device has sub-nodes
|
||||
with 'reg' property.
|
||||
- ranges: allows valid 1:1 translation between child's address space and
|
||||
|
||||
@@ -29,3 +29,25 @@ Example:
|
||||
marvell,port-mode = <2>; /* PMM_GLOBAL_MODE */
|
||||
};
|
||||
|
||||
UDC
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "marvell,pxa270-udc" for USB controllers
|
||||
used in device mode.
|
||||
- reg: usb device MMIO address space
|
||||
- interrupts: single interrupt generated by the UDC IP
|
||||
- clocks: input clock of the UDC IP (see clock-bindings.txt)
|
||||
|
||||
Optional properties:
|
||||
- gpios:
|
||||
- gpio activated to control the USB D+ pullup (see gpio.txt)
|
||||
|
||||
Example:
|
||||
|
||||
pxa27x_udc: udc@40600000 {
|
||||
compatible = "marvell,pxa270-udc";
|
||||
reg = <0x40600000 0x10000>;
|
||||
interrupts = <11>;
|
||||
clocks = <&pxa2xx_clks 11>;
|
||||
gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
@@ -9,6 +9,8 @@ Optional properties:
|
||||
- big-endian-regs : boolean, set this for hcds with big-endian registers
|
||||
- big-endian-desc : boolean, set this for hcds with big-endian descriptors
|
||||
- big-endian : boolean, for hcds with big-endian-regs + big-endian-desc
|
||||
- no-big-frame-no : boolean, set if frame_no lives in bits [15:0] of HCCA
|
||||
- num-ports : u32, to override the detected port count
|
||||
- clocks : a list of phandle + clock specifier pairs
|
||||
- phys : phandle + phy specifier pair
|
||||
- phy-names : "usb"
|
||||
|
||||
+13
-41
@@ -54,18 +54,14 @@ The PHY driver should create the PHY in order for other peripheral controllers
|
||||
to make use of it. The PHY framework provides 2 APIs to create the PHY.
|
||||
|
||||
struct phy *phy_create(struct device *dev, struct device_node *node,
|
||||
const struct phy_ops *ops,
|
||||
struct phy_init_data *init_data);
|
||||
const struct phy_ops *ops);
|
||||
struct phy *devm_phy_create(struct device *dev, struct device_node *node,
|
||||
const struct phy_ops *ops,
|
||||
struct phy_init_data *init_data);
|
||||
const struct phy_ops *ops);
|
||||
|
||||
The PHY drivers can use one of the above 2 APIs to create the PHY by passing
|
||||
the device pointer, phy ops and init_data.
|
||||
the device pointer and phy ops.
|
||||
phy_ops is a set of function pointers for performing PHY operations such as
|
||||
init, exit, power_on and power_off. *init_data* is mandatory to get a reference
|
||||
to the PHY in the case of non-dt boot. See section *Board File Initialization*
|
||||
on how init_data should be used.
|
||||
init, exit, power_on and power_off.
|
||||
|
||||
Inorder to dereference the private data (in phy_ops), the phy provider driver
|
||||
can use phy_set_drvdata() after creating the PHY and use phy_get_drvdata() in
|
||||
@@ -137,42 +133,18 @@ There are exported APIs like phy_pm_runtime_get, phy_pm_runtime_get_sync,
|
||||
phy_pm_runtime_put, phy_pm_runtime_put_sync, phy_pm_runtime_allow and
|
||||
phy_pm_runtime_forbid for performing PM operations.
|
||||
|
||||
8. Board File Initialization
|
||||
8. PHY Mappings
|
||||
|
||||
Certain board file initialization is necessary in order to get a reference
|
||||
to the PHY in the case of non-dt boot.
|
||||
Say we have a single device that implements 3 PHYs that of USB, SATA and PCIe,
|
||||
then in the board file the following initialization should be done.
|
||||
In order to get reference to a PHY without help from DeviceTree, the framework
|
||||
offers lookups which can be compared to clkdev that allow clk structures to be
|
||||
bound to devices. A lookup can be made be made during runtime when a handle to
|
||||
the struct phy already exists.
|
||||
|
||||
struct phy_consumer consumers[] = {
|
||||
PHY_CONSUMER("dwc3.0", "usb"),
|
||||
PHY_CONSUMER("pcie.0", "pcie"),
|
||||
PHY_CONSUMER("sata.0", "sata"),
|
||||
};
|
||||
PHY_CONSUMER takes 2 parameters, first is the device name of the controller
|
||||
(PHY consumer) and second is the port name.
|
||||
The framework offers the following API for registering and unregistering the
|
||||
lookups.
|
||||
|
||||
struct phy_init_data init_data = {
|
||||
.consumers = consumers,
|
||||
.num_consumers = ARRAY_SIZE(consumers),
|
||||
};
|
||||
|
||||
static const struct platform_device pipe3_phy_dev = {
|
||||
.name = "pipe3-phy",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = {
|
||||
.init_data = &init_data,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
then, while doing phy_create, the PHY driver should pass this init_data
|
||||
phy_create(dev, ops, pdata->init_data);
|
||||
|
||||
and the controller driver (phy consumer) should pass the port name along with
|
||||
the device to get a reference to the PHY
|
||||
phy_get(dev, "pcie");
|
||||
int phy_create_lookup(struct phy *phy, const char *con_id, const char *dev_id);
|
||||
void phy_remove_lookup(struct phy *phy, const char *con_id, const char *dev_id);
|
||||
|
||||
9. DeviceTree Binding
|
||||
|
||||
|
||||
@@ -74,6 +74,13 @@ static struct platform_device my_hid = {
|
||||
You can add as many HID functions as you want, only limited by
|
||||
the amount of interrupt endpoints your gadget driver supports.
|
||||
|
||||
Configuration with configfs
|
||||
|
||||
Instead of adding fake platform devices and drivers in order to pass
|
||||
some data to the kernel, if HID is a part of a gadget composed with
|
||||
configfs the hidg_func_descriptor.report_desc is passed to the kernel
|
||||
by writing the appropriate stream of bytes to a configfs attribute.
|
||||
|
||||
Send and receive HID reports
|
||||
|
||||
HID reports can be sent/received using read/write on the
|
||||
|
||||
@@ -145,7 +145,7 @@ Keyspan PDA Serial Adapter
|
||||
Single port DB-9 serial adapter, pushed as a PDA adapter for iMacs (mostly
|
||||
sold in Macintosh catalogs, comes in a translucent white/green dongle).
|
||||
Fairly simple device. Firmware is homebrew.
|
||||
This driver also works for the Xircom/Entrgra single port serial adapter.
|
||||
This driver also works for the Xircom/Entrega single port serial adapter.
|
||||
|
||||
Current status:
|
||||
Things that work:
|
||||
|
||||
@@ -843,6 +843,8 @@
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "otg";
|
||||
status = "disabled";
|
||||
snps,dis_u3_susphy_quirk;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -865,6 +867,8 @@
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "otg";
|
||||
status = "disabled";
|
||||
snps,dis_u3_susphy_quirk;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -91,18 +91,8 @@ void __init omap_pmic_late_init(void)
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP3)
|
||||
struct phy_consumer consumers[] = {
|
||||
PHY_CONSUMER("musb-hdrc.0", "usb"),
|
||||
};
|
||||
|
||||
struct phy_init_data init_data = {
|
||||
.consumers = consumers,
|
||||
.num_consumers = ARRAY_SIZE(consumers),
|
||||
};
|
||||
|
||||
static struct twl4030_usb_data omap3_usb_pdata = {
|
||||
.usb_mode = T2_USB_MODE_ULPI,
|
||||
.init_data = &init_data,
|
||||
.usb_mode = T2_USB_MODE_ULPI,
|
||||
};
|
||||
|
||||
static int omap3_batt_table[] = {
|
||||
|
||||
@@ -7,22 +7,27 @@
|
||||
* Copyright (C) 2008 Wind River Systems
|
||||
*/
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/usb.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/libfdt.h>
|
||||
#include <linux/usb/ehci_pdriver.h>
|
||||
#include <linux/usb/ohci_pdriver.h>
|
||||
|
||||
#include <asm/octeon/octeon.h>
|
||||
#include <asm/octeon/cvmx-rnm-defs.h>
|
||||
#include <asm/octeon/cvmx-helper.h>
|
||||
#include <asm/octeon/cvmx-helper-board.h>
|
||||
#include <asm/octeon/cvmx-uctlx-defs.h>
|
||||
|
||||
/* Octeon Random Number Generator. */
|
||||
static int __init octeon_rng_device_init(void)
|
||||
@@ -68,6 +73,229 @@ device_initcall(octeon_rng_device_init);
|
||||
|
||||
#ifdef CONFIG_USB
|
||||
|
||||
static DEFINE_MUTEX(octeon2_usb_clocks_mutex);
|
||||
|
||||
static int octeon2_usb_clock_start_cnt;
|
||||
|
||||
static void octeon2_usb_clocks_start(void)
|
||||
{
|
||||
u64 div;
|
||||
union cvmx_uctlx_if_ena if_ena;
|
||||
union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
|
||||
union cvmx_uctlx_uphy_ctl_status uphy_ctl_status;
|
||||
union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status;
|
||||
int i;
|
||||
unsigned long io_clk_64_to_ns;
|
||||
|
||||
|
||||
mutex_lock(&octeon2_usb_clocks_mutex);
|
||||
|
||||
octeon2_usb_clock_start_cnt++;
|
||||
if (octeon2_usb_clock_start_cnt != 1)
|
||||
goto exit;
|
||||
|
||||
io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate();
|
||||
|
||||
/*
|
||||
* Step 1: Wait for voltages stable. That surely happened
|
||||
* before starting the kernel.
|
||||
*
|
||||
* Step 2: Enable SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1
|
||||
*/
|
||||
if_ena.u64 = 0;
|
||||
if_ena.s.en = 1;
|
||||
cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
|
||||
|
||||
/* Step 3: Configure the reference clock, PHY, and HCLK */
|
||||
clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
|
||||
|
||||
/*
|
||||
* If the UCTL looks like it has already been started, skip
|
||||
* the initialization, otherwise bus errors are obtained.
|
||||
*/
|
||||
if (clk_rst_ctl.s.hrst)
|
||||
goto end_clock;
|
||||
/* 3a */
|
||||
clk_rst_ctl.s.p_por = 1;
|
||||
clk_rst_ctl.s.hrst = 0;
|
||||
clk_rst_ctl.s.p_prst = 0;
|
||||
clk_rst_ctl.s.h_clkdiv_rst = 0;
|
||||
clk_rst_ctl.s.o_clkdiv_rst = 0;
|
||||
clk_rst_ctl.s.h_clkdiv_en = 0;
|
||||
clk_rst_ctl.s.o_clkdiv_en = 0;
|
||||
cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
|
||||
|
||||
/* 3b */
|
||||
/* 12MHz crystal. */
|
||||
clk_rst_ctl.s.p_refclk_sel = 0;
|
||||
clk_rst_ctl.s.p_refclk_div = 0;
|
||||
cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
|
||||
|
||||
/* 3c */
|
||||
div = octeon_get_io_clock_rate() / 130000000ull;
|
||||
|
||||
switch (div) {
|
||||
case 0:
|
||||
div = 1;
|
||||
break;
|
||||
case 1:
|
||||
case 2:
|
||||
case 3:
|
||||
case 4:
|
||||
break;
|
||||
case 5:
|
||||
div = 4;
|
||||
break;
|
||||
case 6:
|
||||
case 7:
|
||||
div = 6;
|
||||
break;
|
||||
case 8:
|
||||
case 9:
|
||||
case 10:
|
||||
case 11:
|
||||
div = 8;
|
||||
break;
|
||||
default:
|
||||
div = 12;
|
||||
break;
|
||||
}
|
||||
clk_rst_ctl.s.h_div = div;
|
||||
cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
|
||||
/* Read it back, */
|
||||
clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
|
||||
clk_rst_ctl.s.h_clkdiv_en = 1;
|
||||
cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
|
||||
/* 3d */
|
||||
clk_rst_ctl.s.h_clkdiv_rst = 1;
|
||||
cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
|
||||
|
||||
/* 3e: delay 64 io clocks */
|
||||
ndelay(io_clk_64_to_ns);
|
||||
|
||||
/*
|
||||
* Step 4: Program the power-on reset field in the UCTL
|
||||
* clock-reset-control register.
|
||||
*/
|
||||
clk_rst_ctl.s.p_por = 0;
|
||||
cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
|
||||
|
||||
/* Step 5: Wait 1 ms for the PHY clock to start. */
|
||||
mdelay(1);
|
||||
|
||||
/*
|
||||
* Step 6: Program the reset input from automatic test
|
||||
* equipment field in the UPHY CSR
|
||||
*/
|
||||
uphy_ctl_status.u64 = cvmx_read_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0));
|
||||
uphy_ctl_status.s.ate_reset = 1;
|
||||
cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64);
|
||||
|
||||
/* Step 7: Wait for at least 10ns. */
|
||||
ndelay(10);
|
||||
|
||||
/* Step 8: Clear the ATE_RESET field in the UPHY CSR. */
|
||||
uphy_ctl_status.s.ate_reset = 0;
|
||||
cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64);
|
||||
|
||||
/*
|
||||
* Step 9: Wait for at least 20ns for UPHY to output PHY clock
|
||||
* signals and OHCI_CLK48
|
||||
*/
|
||||
ndelay(20);
|
||||
|
||||
/* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */
|
||||
/* 10a */
|
||||
clk_rst_ctl.s.o_clkdiv_rst = 1;
|
||||
cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
|
||||
|
||||
/* 10b */
|
||||
clk_rst_ctl.s.o_clkdiv_en = 1;
|
||||
cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
|
||||
|
||||
/* 10c */
|
||||
ndelay(io_clk_64_to_ns);
|
||||
|
||||
/*
|
||||
* Step 11: Program the PHY reset field:
|
||||
* UCTL0_CLK_RST_CTL[P_PRST] = 1
|
||||
*/
|
||||
clk_rst_ctl.s.p_prst = 1;
|
||||
cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
|
||||
|
||||
/* Step 12: Wait 1 uS. */
|
||||
udelay(1);
|
||||
|
||||
/* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */
|
||||
clk_rst_ctl.s.hrst = 1;
|
||||
cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
|
||||
|
||||
end_clock:
|
||||
/* Now we can set some other registers. */
|
||||
|
||||
for (i = 0; i <= 1; i++) {
|
||||
port_ctl_status.u64 =
|
||||
cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0));
|
||||
/* Set txvreftune to 15 to obtain compliant 'eye' diagram. */
|
||||
port_ctl_status.s.txvreftune = 15;
|
||||
port_ctl_status.s.txrisetune = 1;
|
||||
port_ctl_status.s.txpreemphasistune = 1;
|
||||
cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0),
|
||||
port_ctl_status.u64);
|
||||
}
|
||||
|
||||
/* Set uSOF cycle period to 60,000 bits. */
|
||||
cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull);
|
||||
exit:
|
||||
mutex_unlock(&octeon2_usb_clocks_mutex);
|
||||
}
|
||||
|
||||
static void octeon2_usb_clocks_stop(void)
|
||||
{
|
||||
mutex_lock(&octeon2_usb_clocks_mutex);
|
||||
octeon2_usb_clock_start_cnt--;
|
||||
mutex_unlock(&octeon2_usb_clocks_mutex);
|
||||
}
|
||||
|
||||
static int octeon_ehci_power_on(struct platform_device *pdev)
|
||||
{
|
||||
octeon2_usb_clocks_start();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void octeon_ehci_power_off(struct platform_device *pdev)
|
||||
{
|
||||
octeon2_usb_clocks_stop();
|
||||
}
|
||||
|
||||
static struct usb_ehci_pdata octeon_ehci_pdata = {
|
||||
/* Octeon EHCI matches CPU endianness. */
|
||||
#ifdef __BIG_ENDIAN
|
||||
.big_endian_mmio = 1,
|
||||
#endif
|
||||
.power_on = octeon_ehci_power_on,
|
||||
.power_off = octeon_ehci_power_off,
|
||||
};
|
||||
|
||||
static void __init octeon_ehci_hw_start(void)
|
||||
{
|
||||
union cvmx_uctlx_ehci_ctl ehci_ctl;
|
||||
|
||||
octeon2_usb_clocks_start();
|
||||
|
||||
ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0));
|
||||
/* Use 64-bit addressing. */
|
||||
ehci_ctl.s.ehci_64b_addr_en = 1;
|
||||
ehci_ctl.s.l2c_addr_msb = 0;
|
||||
ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
|
||||
ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
|
||||
cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64);
|
||||
|
||||
octeon2_usb_clocks_stop();
|
||||
}
|
||||
|
||||
static u64 octeon_ehci_dma_mask = DMA_BIT_MASK(64);
|
||||
|
||||
static int __init octeon_ehci_device_init(void)
|
||||
{
|
||||
struct platform_device *pd;
|
||||
@@ -88,7 +316,7 @@ static int __init octeon_ehci_device_init(void)
|
||||
if (octeon_is_simulation() || usb_disabled())
|
||||
return 0; /* No USB in the simulator. */
|
||||
|
||||
pd = platform_device_alloc("octeon-ehci", 0);
|
||||
pd = platform_device_alloc("ehci-platform", 0);
|
||||
if (!pd) {
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
@@ -105,6 +333,10 @@ static int __init octeon_ehci_device_init(void)
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
pd->dev.dma_mask = &octeon_ehci_dma_mask;
|
||||
pd->dev.platform_data = &octeon_ehci_pdata;
|
||||
octeon_ehci_hw_start();
|
||||
|
||||
ret = platform_device_add(pd);
|
||||
if (ret)
|
||||
goto fail;
|
||||
@@ -117,6 +349,41 @@ out:
|
||||
}
|
||||
device_initcall(octeon_ehci_device_init);
|
||||
|
||||
static int octeon_ohci_power_on(struct platform_device *pdev)
|
||||
{
|
||||
octeon2_usb_clocks_start();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void octeon_ohci_power_off(struct platform_device *pdev)
|
||||
{
|
||||
octeon2_usb_clocks_stop();
|
||||
}
|
||||
|
||||
static struct usb_ohci_pdata octeon_ohci_pdata = {
|
||||
/* Octeon OHCI matches CPU endianness. */
|
||||
#ifdef __BIG_ENDIAN
|
||||
.big_endian_mmio = 1,
|
||||
#endif
|
||||
.power_on = octeon_ohci_power_on,
|
||||
.power_off = octeon_ohci_power_off,
|
||||
};
|
||||
|
||||
static void __init octeon_ohci_hw_start(void)
|
||||
{
|
||||
union cvmx_uctlx_ohci_ctl ohci_ctl;
|
||||
|
||||
octeon2_usb_clocks_start();
|
||||
|
||||
ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0));
|
||||
ohci_ctl.s.l2c_addr_msb = 0;
|
||||
ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
|
||||
ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
|
||||
cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64);
|
||||
|
||||
octeon2_usb_clocks_stop();
|
||||
}
|
||||
|
||||
static int __init octeon_ohci_device_init(void)
|
||||
{
|
||||
struct platform_device *pd;
|
||||
@@ -137,7 +404,7 @@ static int __init octeon_ohci_device_init(void)
|
||||
if (octeon_is_simulation() || usb_disabled())
|
||||
return 0; /* No USB in the simulator. */
|
||||
|
||||
pd = platform_device_alloc("octeon-ohci", 0);
|
||||
pd = platform_device_alloc("ohci-platform", 0);
|
||||
if (!pd) {
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
@@ -154,6 +421,9 @@ static int __init octeon_ohci_device_init(void)
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
pd->dev.platform_data = &octeon_ohci_pdata;
|
||||
octeon_ohci_hw_start();
|
||||
|
||||
ret = platform_device_add(pd);
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user