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ethernet/arc/arc_emac - Add new driver
Driver for non-standard on-chip ethernet device ARC EMAC 10/100, instantiated in some legacy ARC (Synopsys) FPGA Boards such as ARCAngel4/ML50x. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: Francois Romieu <romieu@fr.zoreil.com> Cc: Joe Perches <joe@perches.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: linux-kernel@vger.kernel.org Cc: devicetree-discuss@lists.ozlabs.org Cc: Florian Fainelli <florian@openwrt.org> Cc: David Laight <david.laight@aculab.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
committed by
David S. Miller
parent
62208f1245
commit
e4f2379db6
@@ -0,0 +1,38 @@
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* Synopsys ARC EMAC 10/100 Ethernet driver (EMAC)
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Required properties:
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- compatible: Should be "snps,arc-emac"
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- reg: Address and length of the register set for the device
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- interrupts: Should contain the EMAC interrupts
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- clock-frequency: CPU frequency. It is needed to calculate and set polling
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period of EMAC.
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- max-speed: Maximum supported data-rate in Mbit/s. In some HW configurations
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bandwidth of external memory controller might be a limiting factor. That's why
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it's required to specify which data-rate is supported on current SoC or FPGA.
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For example if only 10 Mbit/s is supported (10BASE-T) set "10". If 100 Mbit/s is
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supported (100BASE-TX) set "100".
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- phy: PHY device attached to the EMAC via MDIO bus
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Child nodes of the driver are the individual PHY devices connected to the
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MDIO bus. They must have a "reg" property given the PHY address on the MDIO bus.
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Optional properties:
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- mac-address: 6 bytes, mac address
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Examples:
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ethernet@c0fc2000 {
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compatible = "snps,arc-emac";
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reg = <0xc0fc2000 0x3c>;
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interrupts = <6>;
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mac-address = [ 00 11 22 33 44 55 ];
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clock-frequency = <80000000>;
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max-speed = <100>;
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phy = <&phy0>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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reg = <1>;
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};
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};
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@@ -24,6 +24,7 @@ source "drivers/net/ethernet/allwinner/Kconfig"
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source "drivers/net/ethernet/alteon/Kconfig"
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source "drivers/net/ethernet/amd/Kconfig"
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source "drivers/net/ethernet/apple/Kconfig"
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source "drivers/net/ethernet/arc/Kconfig"
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source "drivers/net/ethernet/atheros/Kconfig"
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source "drivers/net/ethernet/cadence/Kconfig"
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source "drivers/net/ethernet/adi/Kconfig"
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@@ -10,6 +10,7 @@ obj-$(CONFIG_NET_VENDOR_ALLWINNER) += allwinner/
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obj-$(CONFIG_NET_VENDOR_ALTEON) += alteon/
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obj-$(CONFIG_NET_VENDOR_AMD) += amd/
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obj-$(CONFIG_NET_VENDOR_APPLE) += apple/
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obj-$(CONFIG_NET_VENDOR_ARC) += arc/
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obj-$(CONFIG_NET_VENDOR_ATHEROS) += atheros/
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obj-$(CONFIG_NET_CADENCE) += cadence/
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obj-$(CONFIG_NET_BFIN) += adi/
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@@ -0,0 +1,31 @@
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#
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# ARC EMAC network device configuration
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#
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config NET_VENDOR_ARC
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bool "ARC devices"
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default y
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---help---
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If you have a network (Ethernet) card belonging to this class, say Y
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and read the Ethernet-HOWTO, available from
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<http://www.tldp.org/docs.html#howto>.
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Note that the answer to this question doesn't directly affect the
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kernel: saying N will just cause the configurator to skip all
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the questions about ARC cards. If you say Y, you will be asked for
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your specific card in the following questions.
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if NET_VENDOR_ARC
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config ARC_EMAC
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tristate "ARC EMAC support"
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select MII
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select PHYLIB
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depends on OF_IRQ
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depends on OF_NET
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---help---
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On some legacy ARC (Synopsys) FPGA boards such as ARCAngel4/ML50x
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non-standard on-chip ethernet device ARC EMAC 10/100 is used.
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Say Y here if you have such a board. If unsure, say N.
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endif # NET_VENDOR_ARC
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@@ -0,0 +1,6 @@
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#
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# Makefile for the ARC network device drivers.
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#
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arc_emac-objs := emac_main.o emac_mdio.o
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obj-$(CONFIG_ARC_EMAC) += arc_emac.o
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@@ -0,0 +1,214 @@
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/*
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* Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
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*
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* Registers and bits definitions of ARC EMAC
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*/
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#ifndef ARC_EMAC_H
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#define ARC_EMAC_H
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/netdevice.h>
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#include <linux/phy.h>
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/* STATUS and ENABLE Register bit masks */
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#define TXINT_MASK (1<<0) /* Transmit interrupt */
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#define RXINT_MASK (1<<1) /* Receive interrupt */
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#define ERR_MASK (1<<2) /* Error interrupt */
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#define TXCH_MASK (1<<3) /* Transmit chaining error interrupt */
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#define MSER_MASK (1<<4) /* Missed packet counter error */
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#define RXCR_MASK (1<<8) /* RXCRCERR counter rolled over */
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#define RXFR_MASK (1<<9) /* RXFRAMEERR counter rolled over */
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#define RXFL_MASK (1<<10) /* RXOFLOWERR counter rolled over */
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#define MDIO_MASK (1<<12) /* MDIO complete interrupt */
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#define TXPL_MASK (1<<31) /* Force polling of BD by EMAC */
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/* CONTROL Register bit masks */
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#define EN_MASK (1<<0) /* VMAC enable */
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#define TXRN_MASK (1<<3) /* TX enable */
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#define RXRN_MASK (1<<4) /* RX enable */
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#define DSBC_MASK (1<<8) /* Disable receive broadcast */
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#define ENFL_MASK (1<<10) /* Enable Full-duplex */
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#define PROM_MASK (1<<11) /* Promiscuous mode */
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/* Buffer descriptor INFO bit masks */
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#define OWN_MASK (1<<31) /* 0-CPU owns buffer, 1-EMAC owns buffer */
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#define FIRST_MASK (1<<16) /* First buffer in chain */
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#define LAST_MASK (1<<17) /* Last buffer in chain */
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#define LEN_MASK 0x000007FF /* last 11 bits */
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#define CRLS (1<<21)
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#define DEFR (1<<22)
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#define DROP (1<<23)
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#define RTRY (1<<24)
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#define LTCL (1<<28)
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#define UFLO (1<<29)
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#define FOR_EMAC OWN_MASK
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#define FOR_CPU 0
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/* ARC EMAC register set combines entries for MAC and MDIO */
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enum {
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R_ID = 0,
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R_STATUS,
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R_ENABLE,
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R_CTRL,
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R_POLLRATE,
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R_RXERR,
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R_MISS,
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R_TX_RING,
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R_RX_RING,
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R_ADDRL,
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R_ADDRH,
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R_LAFL,
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R_LAFH,
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R_MDIO,
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};
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#define TX_TIMEOUT (400*HZ/1000) /* Transmission timeout */
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#define ARC_EMAC_NAPI_WEIGHT 40 /* Workload for NAPI */
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#define EMAC_BUFFER_SIZE 1536 /* EMAC buffer size */
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/**
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* struct arc_emac_bd - EMAC buffer descriptor (BD).
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*
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* @info: Contains status information on the buffer itself.
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* @data: 32-bit byte addressable pointer to the packet data.
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*/
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struct arc_emac_bd {
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__le32 info;
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dma_addr_t data;
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};
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/* Number of Rx/Tx BD's */
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#define RX_BD_NUM 128
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#define TX_BD_NUM 128
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#define RX_RING_SZ (RX_BD_NUM * sizeof(struct arc_emac_bd))
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#define TX_RING_SZ (TX_BD_NUM * sizeof(struct arc_emac_bd))
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/**
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* struct buffer_state - Stores Rx/Tx buffer state.
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* @sk_buff: Pointer to socket buffer.
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* @addr: Start address of DMA-mapped memory region.
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* @len: Length of DMA-mapped memory region.
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*/
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struct buffer_state {
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struct sk_buff *skb;
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DEFINE_DMA_UNMAP_ADDR(addr);
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DEFINE_DMA_UNMAP_LEN(len);
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};
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/**
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* struct arc_emac_priv - Storage of EMAC's private information.
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* @dev: Pointer to the current device.
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* @ndev: Pointer to the current network device.
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* @phy_dev: Pointer to attached PHY device.
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* @bus: Pointer to the current MII bus.
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* @regs: Base address of EMAC memory-mapped control registers.
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* @napi: Structure for NAPI.
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* @stats: Network device statistics.
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* @rxbd: Pointer to Rx BD ring.
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* @txbd: Pointer to Tx BD ring.
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* @rxbd_dma: DMA handle for Rx BD ring.
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* @txbd_dma: DMA handle for Tx BD ring.
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* @rx_buff: Storage for Rx buffers states.
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* @tx_buff: Storage for Tx buffers states.
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* @txbd_curr: Index of Tx BD to use on the next "ndo_start_xmit".
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* @txbd_dirty: Index of Tx BD to free on the next Tx interrupt.
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* @last_rx_bd: Index of the last Rx BD we've got from EMAC.
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* @link: PHY's last seen link state.
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* @duplex: PHY's last set duplex mode.
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* @speed: PHY's last set speed.
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* @max_speed: Maximum supported by current system network data-rate.
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*/
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struct arc_emac_priv {
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/* Devices */
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struct device *dev;
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struct net_device *ndev;
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struct phy_device *phy_dev;
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struct mii_bus *bus;
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void __iomem *regs;
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struct napi_struct napi;
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struct net_device_stats stats;
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struct arc_emac_bd *rxbd;
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struct arc_emac_bd *txbd;
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dma_addr_t rxbd_dma;
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dma_addr_t txbd_dma;
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struct buffer_state rx_buff[RX_BD_NUM];
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struct buffer_state tx_buff[TX_BD_NUM];
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unsigned int txbd_curr;
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unsigned int txbd_dirty;
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unsigned int last_rx_bd;
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unsigned int link;
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unsigned int duplex;
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unsigned int speed;
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unsigned int max_speed;
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};
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/**
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* arc_reg_set - Sets EMAC register with provided value.
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* @priv: Pointer to ARC EMAC private data structure.
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* @reg: Register offset from base address.
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* @value: Value to set in register.
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*/
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static inline void arc_reg_set(struct arc_emac_priv *priv, int reg, int value)
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{
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iowrite32(value, priv->regs + reg * sizeof(int));
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}
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/**
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* arc_reg_get - Gets value of specified EMAC register.
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* @priv: Pointer to ARC EMAC private data structure.
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* @reg: Register offset from base address.
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*
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* returns: Value of requested register.
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*/
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static inline unsigned int arc_reg_get(struct arc_emac_priv *priv, int reg)
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{
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return ioread32(priv->regs + reg * sizeof(int));
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}
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/**
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* arc_reg_or - Applies mask to specified EMAC register - ("reg" | "mask").
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* @priv: Pointer to ARC EMAC private data structure.
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* @reg: Register offset from base address.
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* @mask: Mask to apply to specified register.
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*
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* This function reads initial register value, then applies provided mask
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* to it and then writes register back.
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*/
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static inline void arc_reg_or(struct arc_emac_priv *priv, int reg, int mask)
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{
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unsigned int value = arc_reg_get(priv, reg);
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arc_reg_set(priv, reg, value | mask);
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}
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/**
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* arc_reg_clr - Applies mask to specified EMAC register - ("reg" & ~"mask").
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* @priv: Pointer to ARC EMAC private data structure.
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* @reg: Register offset from base address.
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* @mask: Mask to apply to specified register.
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*
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* This function reads initial register value, then applies provided mask
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* to it and then writes register back.
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*/
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static inline void arc_reg_clr(struct arc_emac_priv *priv, int reg, int mask)
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{
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unsigned int value = arc_reg_get(priv, reg);
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arc_reg_set(priv, reg, value & ~mask);
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}
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int arc_mdio_probe(struct platform_device *pdev, struct arc_emac_priv *priv);
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int arc_mdio_remove(struct arc_emac_priv *priv);
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#endif /* ARC_EMAC_H */
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,152 @@
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/*
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* Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
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*
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* MDIO implementation for ARC EMAC
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*/
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#include <linux/delay.h>
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#include <linux/of_mdio.h>
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#include <linux/platform_device.h>
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#include "emac.h"
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/* Number of seconds we wait for "MDIO complete" flag to appear */
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#define ARC_MDIO_COMPLETE_POLL_COUNT 1
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/**
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* arc_mdio_complete_wait - Waits until MDIO transaction is completed.
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* @priv: Pointer to ARC EMAC private data structure.
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*
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* returns: 0 on success, -ETIMEDOUT on a timeout.
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*/
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static int arc_mdio_complete_wait(struct arc_emac_priv *priv)
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{
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unsigned int i;
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for (i = 0; i < ARC_MDIO_COMPLETE_POLL_COUNT * 40; i++) {
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unsigned int status = arc_reg_get(priv, R_STATUS);
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status &= MDIO_MASK;
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if (status) {
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/* Reset "MDIO complete" flag */
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arc_reg_set(priv, R_STATUS, status);
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return 0;
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}
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msleep(25);
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}
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return -ETIMEDOUT;
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}
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/**
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* arc_mdio_read - MDIO interface read function.
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* @bus: Pointer to MII bus structure.
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* @phy_addr: Address of the PHY device.
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* @reg_num: PHY register to read.
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*
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* returns: The register contents on success, -ETIMEDOUT on a timeout.
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*
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* Reads the contents of the requested register from the requested PHY
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* address.
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*/
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static int arc_mdio_read(struct mii_bus *bus, int phy_addr, int reg_num)
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{
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struct arc_emac_priv *priv = bus->priv;
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unsigned int value;
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int error;
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arc_reg_set(priv, R_MDIO,
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0x60020000 | (phy_addr << 23) | (reg_num << 18));
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error = arc_mdio_complete_wait(priv);
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if (error < 0)
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return error;
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value = arc_reg_get(priv, R_MDIO) & 0xffff;
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dev_dbg(priv->dev, "arc_mdio_read(phy_addr=%i, reg_num=%x) = %x\n",
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phy_addr, reg_num, value);
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return value;
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}
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/**
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* arc_mdio_write - MDIO interface write function.
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* @bus: Pointer to MII bus structure.
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* @phy_addr: Address of the PHY device.
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* @reg_num: PHY register to write to.
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* @value: Value to be written into the register.
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*
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* returns: 0 on success, -ETIMEDOUT on a timeout.
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*
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* Writes the value to the requested register.
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*/
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static int arc_mdio_write(struct mii_bus *bus, int phy_addr,
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int reg_num, u16 value)
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{
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struct arc_emac_priv *priv = bus->priv;
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dev_dbg(priv->dev,
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"arc_mdio_write(phy_addr=%i, reg_num=%x, value=%x)\n",
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phy_addr, reg_num, value);
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arc_reg_set(priv, R_MDIO,
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0x50020000 | (phy_addr << 23) | (reg_num << 18) | value);
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return arc_mdio_complete_wait(priv);
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}
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/**
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* arc_mdio_probe - MDIO probe function.
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* @pdev: Pointer to platform device.
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* @priv: Pointer to ARC EMAC private data structure.
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*
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* returns: 0 on success, -ENOMEM when mdiobus_alloc
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* (to allocate memory for MII bus structure) fails.
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*
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* Sets up and registers the MDIO interface.
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*/
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int arc_mdio_probe(struct platform_device *pdev, struct arc_emac_priv *priv)
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{
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struct mii_bus *bus;
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int error;
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bus = mdiobus_alloc();
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if (!bus)
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return -ENOMEM;
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priv->bus = bus;
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bus->priv = priv;
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bus->parent = priv->dev;
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bus->name = "Synopsys MII Bus",
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bus->read = &arc_mdio_read;
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bus->write = &arc_mdio_write;
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snprintf(bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
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error = of_mdiobus_register(bus, pdev->dev.of_node);
|
||||
if (error) {
|
||||
dev_err(priv->dev, "cannot register MDIO bus %s\n", bus->name);
|
||||
mdiobus_free(bus);
|
||||
return error;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* arc_mdio_remove - MDIO remove function.
|
||||
* @priv: Pointer to ARC EMAC private data structure.
|
||||
*
|
||||
* Unregisters the MDIO and frees any associate memory for MII bus.
|
||||
*/
|
||||
int arc_mdio_remove(struct arc_emac_priv *priv)
|
||||
{
|
||||
mdiobus_unregister(priv->bus);
|
||||
mdiobus_free(priv->bus);
|
||||
priv->bus = NULL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
Reference in New Issue
Block a user