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Merge tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux
Pull clock framework updates from Mike Turquette:
"The clock framework changes for 3.17 are mostly additions of new clock
drivers and fixes/enhancements to existing clock drivers. There are
also some non-critical fixes and improvements to the framework core.
Changes to the clock framework core include:
- improvements to printks on errors
- flattening the previously hierarchal structure of per-clock entries
in debugfs
- allow per-clock debugfs entries that are specific to a particular
clock driver
- configure initial clock parent and/or initial clock rate from
Device Tree
- several feature enhancements to the composite clock type
- misc fixes
New clock drivers added include:
- TI Palmas PMIC
- Allwinner A23 SoC
- Qualcomm APQ8084 and IPQ8064 SoCs
- Rockchip rk3188, rk3066 and rk3288 SoCs
- STMicroelectronics STiH407 SoC
- Cirrus Logic CLPS711X SoC
Many fixes, feature enhancements and further clock tree support for
existing clock drivers also were merged, such as Samsung's "ARMCLK
down" power saving feature for their Exynos4 & Exynos5 SoCs"
* tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
clk: Add missing of_clk_set_defaults export
clk: checking wrong variable in __set_clk_parents()
clk: Propagate any error return from debug_init()
clk: clps711x: Add DT bindings documentation
clk: Add CLPS711X clk driver
clk: st: Use round to closest divider flag
clk: st: Update frequency tables for fs660c32 and fs432c65
clk: st: STiH407: Support for clockgenA9
clk: st: STiH407: Support for clockgenD0/D2/D3
clk: st: STiH407: Support for clockgenC0
clk: st: Add quadfs reset handling
clk: st: Add polarity bit indication
clk: st: STiH407: Support for clockgenA0
clk: st: STiH407: Support for A9 MUX Clocks
clk: st: STiH407: Support for Flexgen Clocks
clk: st: Adds Flexgen clock binding
clk: st: Remove uncessary (void *) cast
clk: st: use static const for clkgen_pll_data tables
clk: st: use static const for stm_fs tables
clk: st: Update ST clock binding documentation
...
This commit is contained in:
Linus Torvalds
@@ -12,8 +12,38 @@ Properties:
|
||||
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- reg : offset and length of the register set.
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- #clock-cells : must be <1>, since PMU requires once cell as clock specifier.
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The single specifier cell is used as index to list of clocks
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provided by PMU, which is currently:
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0 : SoC clock output (CLKOUT pin)
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- clock-names : list of clock names for particular CLKOUT mux inputs in
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following format:
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"clkoutN", where N is a decimal number corresponding to
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CLKOUT mux control bits value for given input, e.g.
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"clkout0", "clkout7", "clkout15".
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- clocks : list of phandles and specifiers to all input clocks listed in
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clock-names property.
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Example :
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pmu_system_controller: system-controller@10040000 {
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compatible = "samsung,exynos5250-pmu", "syscon";
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reg = <0x10040000 0x5000>;
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#clock-cells = <1>;
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clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
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"clkout4", "clkout8", "clkout9";
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clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
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<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
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<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
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<&clock CLK_XUSBXTI>;
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};
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Example of clock consumer :
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usb3503: usb3503@08 {
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/* ... */
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clock-names = "refclk";
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clocks = <&pmu_system_controller 0>;
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/* ... */
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};
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@@ -0,0 +1,35 @@
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* Palmas 32KHz clocks *
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Palmas device has two clock output pins for 32KHz, KG and KG_AUDIO.
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This binding uses the common clock binding ./clock-bindings.txt.
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Required properties:
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- compatible : "ti,palmas-clk32kg" for clk32kg clock
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"ti,palmas-clk32kgaudio" for clk32kgaudio clock
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- #clock-cells : shall be set to 0.
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Optional property:
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- ti,external-sleep-control: The external enable input pins controlled the
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enable/disable of clocks. The external enable input pins ENABLE1,
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ENABLE2 and NSLEEP. The valid values for the external pins are:
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PALMAS_EXT_CONTROL_PIN_ENABLE1 for ENABLE1 pin
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PALMAS_EXT_CONTROL_PIN_ENABLE2 for ENABLE2 pin
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PALMAS_EXT_CONTROL_PIN_NSLEEP for NSLEEP pin
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Option 0 or missing this property means the clock is enabled/disabled
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via register access and these pins do not have any control.
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The macros of external control pins for DTS is defined at
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dt-bindings/mfd/palmas.h
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Example:
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#include <dt-bindings/mfd/palmas.h>
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...
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palmas: tps65913@58 {
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...
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clk32kg: palmas_clk32k@0 {
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compatible = "ti,palmas-clk32kg";
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#clock-cells = <0>;
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ti,external-sleep-control = <PALMAS_EXT_CONTROL_PIN_NSLEEP>;
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};
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...
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};
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@@ -131,3 +131,39 @@ clock signal, and a UART.
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("pll" and "pll-switched").
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* The UART has its baud clock connected the external oscillator and its
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register clock connected to the PLL clock (the "pll-switched" signal)
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==Assigned clock parents and rates==
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Some platforms may require initial configuration of default parent clocks
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and clock frequencies. Such a configuration can be specified in a device tree
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node through assigned-clocks, assigned-clock-parents and assigned-clock-rates
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properties. The assigned-clock-parents property should contain a list of parent
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clocks in form of phandle and clock specifier pairs, the assigned-clock-parents
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property the list of assigned clock frequency values - corresponding to clocks
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listed in the assigned-clocks property.
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To skip setting parent or rate of a clock its corresponding entry should be
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set to 0, or can be omitted if it is not followed by any non-zero entry.
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uart@a000 {
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compatible = "fsl,imx-uart";
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reg = <0xa000 0x1000>;
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...
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clocks = <&osc 0>, <&pll 1>;
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clock-names = "baud", "register";
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assigned-clocks = <&clkcon 0>, <&pll 2>;
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assigned-clock-parents = <&pll 2>;
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assigned-clock-rates = <0>, <460800>;
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};
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In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and
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the <&pll 2> clock is assigned a frequency value of 460800 Hz.
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Configuring a clock's parent and rate through the device node that consumes
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the clock can be done only for clocks that have a single user. Specifying
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conflicting parent or rate configuration in multiple consumer nodes for
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a shared clock is forbidden.
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Configuration of common clocks, which affect multiple consumer devices can
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be similarly specified in the clock provider node.
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@@ -0,0 +1,19 @@
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* Clock bindings for the Cirrus Logic CLPS711X CPUs
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Required properties:
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- compatible : Shall contain "cirrus,clps711x-clk".
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- reg : Address of the internal register set.
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- startup-frequency: Factory set CPU startup frequency in HZ.
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- #clock-cells : Should be <1>.
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. See include/dt-bindings/clock/clps711x-clock.h
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for the full list of CLPS711X clock IDs.
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Example:
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clks: clks@80000000 {
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#clock-cells = <1>;
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compatible = "cirrus,ep7312-clk", "cirrus,clps711x-clk";
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reg = <0x80000000 0xc000>;
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startup-frequency = <73728000>;
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};
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@@ -5,6 +5,8 @@ Required properties :
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- compatible : shall contain only one of the following:
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"qcom,gcc-apq8064"
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"qcom,gcc-apq8084"
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"qcom,gcc-ipq8064"
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"qcom,gcc-msm8660"
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"qcom,gcc-msm8960"
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"qcom,gcc-msm8974"
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@@ -4,6 +4,8 @@ Qualcomm Multimedia Clock & Reset Controller Binding
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Required properties :
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- compatible : shall contain only one of the following:
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"qcom,mmcc-apq8064"
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"qcom,mmcc-apq8084"
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"qcom,mmcc-msm8660"
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"qcom,mmcc-msm8960"
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"qcom,mmcc-msm8974"
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@@ -0,0 +1,61 @@
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* Rockchip RK3188/RK3066 Clock and Reset Unit
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The RK3188/RK3066 clock controller generates and supplies clock to various
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controllers within the SoC and also implements a reset controller for SoC
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peripherals.
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Required Properties:
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- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
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"rockchip,rk3066a-cru"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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- #reset-cells: should be 1.
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Optional Properties:
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- rockchip,grf: phandle to the syscon managing the "general register files"
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If missing pll rates are not changable, due to the missing pll lock status.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
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dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
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Similar macros exist for the reset sources in these files.
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External clocks:
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There are several clocks that are generated outside the SoC. It is expected
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that they are defined using standard clock bindings with following
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clock-output-names:
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- "xin24m" - crystal input - required,
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- "xin32k" - rtc clock - optional,
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- "xin27m" - 27mhz crystal input on rk3066 - optional,
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- "ext_hsadc" - external HSADC clock - optional,
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- "ext_cif0" - external camera clock - optional,
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- "ext_rmii" - external RMII clock - optional,
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- "ext_jtag" - externalJTAG clock - optional
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Example: Clock controller node:
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cru: cru@20000000 {
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compatible = "rockchip,rk3188-cru";
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reg = <0x20000000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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Example: UART controller node that consumes the clock generated by the clock
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controller:
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uart0: serial@10124000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x10124000 0x400>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clocks = <&cru SCLK_UART0>;
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};
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@@ -0,0 +1,61 @@
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* Rockchip RK3288 Clock and Reset Unit
|
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|
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The RK3288 clock controller generates and supplies clock to various
|
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controllers within the SoC and also implements a reset controller for SoC
|
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peripherals.
|
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Required Properties:
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- compatible: should be "rockchip,rk3288-cru"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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- #reset-cells: should be 1.
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Optional Properties:
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- rockchip,grf: phandle to the syscon managing the "general register files"
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If missing pll rates are not changable, due to the missing pll lock status.
|
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|
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
|
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preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
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used in device tree sources. Similar macros exist for the reset sources in
|
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these files.
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|
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External clocks:
|
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|
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There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
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clock-output-names:
|
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- "xin24m" - crystal input - required,
|
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- "xin32k" - rtc clock - optional,
|
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- "ext_i2s" - external I2S clock - optional,
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- "ext_hsadc" - external HSADC clock - optional,
|
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- "ext_edp_24m" - external display port clock - optional,
|
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- "ext_vip" - external VIP clock - optional,
|
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- "ext_isp" - external ISP clock - optional,
|
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- "ext_jtag" - external JTAG clock - optional
|
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Example: Clock controller node:
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cru: cru@20000000 {
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compatible = "rockchip,rk3188-cru";
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reg = <0x20000000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
|
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Example: UART controller node that consumes the clock generated by the clock
|
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controller:
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|
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uart0: serial@10124000 {
|
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compatible = "snps,dw-apb-uart";
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reg = <0x10124000 0x400>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clocks = <&cru SCLK_UART0>;
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};
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@@ -6,6 +6,9 @@ This binding uses the common clock binding[1].
|
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|
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== Gate clocks ==
|
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|
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These bindings are deprecated!
|
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Please use the soc specific CRU bindings instead.
|
||||
|
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The gate registers form a continuos block which makes the dt node
|
||||
structure a matter of taste, as either all gates can be put into
|
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one gate clock spanning all registers or they can be divided into
|
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|
||||
@@ -24,26 +24,26 @@ Required properties:
|
||||
|
||||
Example:
|
||||
|
||||
clockgenA@fd345000 {
|
||||
clockgen-a@fd345000 {
|
||||
reg = <0xfd345000 0xb50>;
|
||||
|
||||
CLK_M_A1_DIV1: CLK_M_A1_DIV1 {
|
||||
clk_m_a1_div1: clk-m-a1-div1 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgena-divmux-c32-odf1",
|
||||
"st,clkgena-divmux";
|
||||
|
||||
clocks = <&CLK_M_A1_OSC_PREDIV>,
|
||||
<&CLK_M_A1_PLL0 1>, /* PLL0 PHI1 */
|
||||
<&CLK_M_A1_PLL1 1>; /* PLL1 PHI1 */
|
||||
clocks = <&clk_m_a1_osc_prediv>,
|
||||
<&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
|
||||
<&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
|
||||
|
||||
clock-output-names = "CLK_M_RX_ICN_TS",
|
||||
"CLK_M_RX_ICN_VDP_0",
|
||||
"", /* Unused */
|
||||
"CLK_M_PRV_T1_BUS",
|
||||
"CLK_M_ICN_REG_12",
|
||||
"CLK_M_ICN_REG_10",
|
||||
"", /* Unused */
|
||||
"CLK_M_ICN_ST231";
|
||||
clock-output-names = "clk-m-rx-icn-ts",
|
||||
"clk-m-rx-icn-vdp-0",
|
||||
"", /* unused */
|
||||
"clk-m-prv-t1-bus",
|
||||
"clk-m-icn-reg-12",
|
||||
"clk-m-icn-reg-10",
|
||||
"", /* unused */
|
||||
"clk-m-icn-st231";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -17,7 +17,7 @@ Required properties:
|
||||
"st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"
|
||||
"st,stih415-clkgen-a9-mux", "st,clkgen-mux"
|
||||
"st,stih416-clkgen-a9-mux", "st,clkgen-mux"
|
||||
|
||||
"st,stih407-clkgen-a9-mux", "st,clkgen-mux"
|
||||
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
|
||||
@@ -27,10 +27,10 @@ Required properties:
|
||||
|
||||
Example:
|
||||
|
||||
CLK_M_HVA: CLK_M_HVA {
|
||||
clk_m_hva: clk-m-hva@fd690868 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
|
||||
reg = <0xfd690868 4>;
|
||||
|
||||
clocks = <&CLOCKGEN_F 1>, <&CLK_M_A1_DIV0 3>;
|
||||
clocks = <&clockgen_f 1>, <&clk_m_a1_div0 3>;
|
||||
};
|
||||
|
||||
@@ -19,11 +19,14 @@ Required properties:
|
||||
"st,stih415-plls-c32-ddr", "st,clkgen-plls-c32"
|
||||
"st,stih416-plls-c32-a9", "st,clkgen-plls-c32"
|
||||
"st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
|
||||
"st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
|
||||
"st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
|
||||
"st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
|
||||
"st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"
|
||||
|
||||
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
|
||||
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
|
||||
|
||||
|
||||
- #clock-cells : From common clock binding; shall be set to 1.
|
||||
|
||||
- clocks : From common clock binding
|
||||
@@ -32,17 +35,17 @@ Required properties:
|
||||
|
||||
Example:
|
||||
|
||||
clockgenA@fee62000 {
|
||||
clockgen-a@fee62000 {
|
||||
reg = <0xfee62000 0xb48>;
|
||||
|
||||
CLK_S_A0_PLL: CLK_S_A0_PLL {
|
||||
clk_s_a0_pll: clk-s-a0-pll {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgena-plls-c65";
|
||||
|
||||
clocks = <&CLK_SYSIN>;
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "CLK_S_A0_PLL0_HS",
|
||||
"CLK_S_A0_PLL0_LS",
|
||||
"CLK_S_A0_PLL1";
|
||||
clock-output-names = "clk-s-a0-pll0-hs",
|
||||
"clk-s-a0-pll0-ls",
|
||||
"clk-s-a0-pll1";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -20,17 +20,17 @@ Required properties:
|
||||
|
||||
Example:
|
||||
|
||||
clockgenA@fd345000 {
|
||||
clockgen-a@fd345000 {
|
||||
reg = <0xfd345000 0xb50>;
|
||||
|
||||
CLK_M_A2_OSC_PREDIV: CLK_M_A2_OSC_PREDIV {
|
||||
clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,clkgena-prediv-c32",
|
||||
"st,clkgena-prediv";
|
||||
|
||||
clocks = <&CLK_SYSIN>;
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "CLK_M_A2_OSC_PREDIV";
|
||||
clock-output-names = "clk-m-a2-osc-prediv";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -32,22 +32,30 @@ Required properties:
|
||||
|
||||
Example:
|
||||
|
||||
CLOCKGEN_C_VCC: CLOCKGEN_C_VCC {
|
||||
clockgen_c_vcc: clockgen-c-vcc@0xfe8308ac {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
|
||||
reg = <0xfe8308ac 12>;
|
||||
|
||||
clocks = <&CLK_S_VCC_HD>, <&CLOCKGEN_C 1>,
|
||||
<&CLK_S_TMDS_FROMPHY>, <&CLOCKGEN_C 2>;
|
||||
clocks = <&clk_s_vcc_hd>,
|
||||
<&clockgen_c 1>,
|
||||
<&clk_s_tmds_fromphy>,
|
||||
<&clockgen_c 2>;
|
||||
|
||||
clock-output-names =
|
||||
"CLK_S_PIX_HDMI", "CLK_S_PIX_DVO",
|
||||
"CLK_S_OUT_DVO", "CLK_S_PIX_HD",
|
||||
"CLK_S_HDDAC", "CLK_S_DENC",
|
||||
"CLK_S_SDDAC", "CLK_S_PIX_MAIN",
|
||||
"CLK_S_PIX_AUX", "CLK_S_STFE_FRC_0",
|
||||
"CLK_S_REF_MCRU", "CLK_S_SLAVE_MCRU",
|
||||
"CLK_S_TMDS_HDMI", "CLK_S_HDMI_REJECT_PLL",
|
||||
"CLK_S_THSENS";
|
||||
clock-output-names = "clk-s-pix-hdmi",
|
||||
"clk-s-pix-dvo",
|
||||
"clk-s-out-dvo",
|
||||
"clk-s-pix-hd",
|
||||
"clk-s-hddac",
|
||||
"clk-s-denc",
|
||||
"clk-s-sddac",
|
||||
"clk-s-pix-main",
|
||||
"clk-s-pix-aux",
|
||||
"clk-s-stfe-frc-0",
|
||||
"clk-s-ref-mcru",
|
||||
"clk-s-slave-mcru",
|
||||
"clk-s-tmds-hdmi",
|
||||
"clk-s-hdmi-reject-pll",
|
||||
"clk-s-thsens";
|
||||
};
|
||||
|
||||
|
||||
@@ -24,60 +24,77 @@ address is common of all subnode.
|
||||
quadfs_node {
|
||||
...
|
||||
};
|
||||
|
||||
mux_node {
|
||||
...
|
||||
};
|
||||
|
||||
vcc_node {
|
||||
...
|
||||
};
|
||||
|
||||
flexgen_node {
|
||||
...
|
||||
};
|
||||
...
|
||||
};
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
Each subnode should use the binding discribe in [2]..[4]
|
||||
Each subnode should use the binding discribe in [2]..[7]
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/st,quadfs.txt
|
||||
[3] Documentation/devicetree/bindings/clock/st,quadfs.txt
|
||||
[4] Documentation/devicetree/bindings/clock/st,quadfs.txt
|
||||
[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
|
||||
[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt
|
||||
[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
|
||||
[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
|
||||
[6] Documentation/devicetree/bindings/clock/st,vcc.txt
|
||||
[7] Documentation/devicetree/bindings/clock/st,quadfs.txt
|
||||
[8] Documentation/devicetree/bindings/clock/st,flexgen.txt
|
||||
|
||||
|
||||
Required properties:
|
||||
- reg : A Base address and length of the register set.
|
||||
|
||||
Example:
|
||||
|
||||
clockgenA@fee62000 {
|
||||
clockgen-a@fee62000 {
|
||||
|
||||
reg = <0xfee62000 0xb48>;
|
||||
|
||||
CLK_S_A0_PLL: CLK_S_A0_PLL {
|
||||
clk_s_a0_pll: clk-s-a0-pll {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgena-plls-c65";
|
||||
|
||||
clocks = <&CLK_SYSIN>;
|
||||
clocks = <&clk-sysin>;
|
||||
|
||||
clock-output-names = "CLK_S_A0_PLL0_HS",
|
||||
"CLK_S_A0_PLL0_LS",
|
||||
"CLK_S_A0_PLL1";
|
||||
clock-output-names = "clk-s-a0-pll0-hs",
|
||||
"clk-s-a0-pll0-ls",
|
||||
"clk-s-a0-pll1";
|
||||
};
|
||||
|
||||
CLK_S_A0_OSC_PREDIV: CLK_S_A0_OSC_PREDIV {
|
||||
clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,clkgena-prediv-c65",
|
||||
"st,clkgena-prediv";
|
||||
|
||||
clocks = <&CLK_SYSIN>;
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "CLK_S_A0_OSC_PREDIV";
|
||||
clock-output-names = "clk-s-a0-osc-prediv";
|
||||
};
|
||||
|
||||
CLK_S_A0_HS: CLK_S_A0_HS {
|
||||
clk_s_a0_hs: clk-s-a0-hs {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgena-divmux-c65-hs",
|
||||
"st,clkgena-divmux";
|
||||
|
||||
clocks = <&CLK_S_A0_OSC_PREDIV>,
|
||||
<&CLK_S_A0_PLL 0>, /* PLL0 HS */
|
||||
<&CLK_S_A0_PLL 2>; /* PLL1 */
|
||||
clocks = <&clk-s_a0_osc_prediv>,
|
||||
<&clk-s_a0_pll 0>, /* pll0 hs */
|
||||
<&clk-s_a0_pll 2>; /* pll1 */
|
||||
|
||||
clock-output-names = "CLK_S_FDMA_0",
|
||||
"CLK_S_FDMA_1",
|
||||
""; /* CLK_S_JIT_SENSE */
|
||||
/* Fourth output unused */
|
||||
clock-output-names = "clk-s-fdma-0",
|
||||
"clk-s-fdma-1",
|
||||
""; /* clk-s-jit-sense */
|
||||
/* fourth output unused */
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -0,0 +1,119 @@
|
||||
Binding for a type of flexgen structure found on certain
|
||||
STMicroelectronics consumer electronics SoC devices
|
||||
|
||||
This structure includes:
|
||||
- a clock cross bar (represented by a mux element)
|
||||
- a pre and final dividers (represented by a divider and gate elements)
|
||||
|
||||
Flexgen structure is a part of Clockgen[1].
|
||||
|
||||
Please find an example below:
|
||||
|
||||
Clockgen block diagram
|
||||
-------------------------------------------------------------------
|
||||
| Flexgen stucture |
|
||||
| --------------------------------------------- |
|
||||
| | ------- -------- -------- | |
|
||||
clk_sysin | | | | | | | | |
|
||||
---|-----------------|-->| | | | | | | |
|
||||
| | | | | | | | | | |
|
||||
| | ------- | | | |Pre | |Final | | |
|
||||
| | |PLL0 | | | | |Dividers| |Dividers| | |
|
||||
| |->| | | | | | x32 | | x32 | | |
|
||||
| | | odf_0|----|-->| | | | | | | |
|
||||
| | | | | | | | | | | | |
|
||||
| | | | | | | | | | | | |
|
||||
| | | | | | | | | | | | |
|
||||
| | | | | | | | | | | | |
|
||||
| | ------- | | | | | | | | |
|
||||
| | | | | | | | | | |
|
||||
| | ------- | | Clock | | | | | | |
|
||||
| | |PLL1 | | | | | | | | | |
|
||||
| |->| | | | Cross | | | | | | |
|
||||
| | | odf_0|----|-->| | | | | | CLK_DIV[31:0]
|
||||
| | | | | | Bar |====>| |====>| |===|=========>
|
||||
| | | | | | | | | | | | |
|
||||
| | | | | | | | | | | | |
|
||||
| | | | | | | | | | | | |
|
||||
| | ------- | | | | | | | | |
|
||||
| | | | | | | | | | |
|
||||
| | ------- | | | | | | | | |
|
||||
| | |QUADFS | | | | | | | | | |
|
||||
| |->| ch0|----|-->| | | | | | | |
|
||||
| | | | | | | | | | | |
|
||||
| | ch1|----|-->| | | | | | | |
|
||||
| | | | | | | | | | | |
|
||||
| | ch2|----|-->| | | DIV | | DIV | | |
|
||||
| | | | | | | 1 to | | 1 to | | |
|
||||
| | ch3|----|-->| | | 1024 | | 64 | | |
|
||||
| ------- | | | | | | | | |
|
||||
| | ------- -------- -------- | |
|
||||
| -------------------------------------------- |
|
||||
| |
|
||||
-------------------------------------------------------------------
|
||||
|
||||
This binding uses the common clock binding[2].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
|
||||
[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be:
|
||||
"st,flexgen"
|
||||
|
||||
- #clock-cells : from common clock binding; shall be set to 1 (multiple clock
|
||||
outputs).
|
||||
|
||||
- clocks : must be set to the parent's phandle. it's could be output clocks of
|
||||
a quadsfs or/and a pll or/and clk_sysin (up to 7 clocks)
|
||||
|
||||
- clock-output-names : List of strings used to name the clock outputs.
|
||||
|
||||
Example:
|
||||
|
||||
clk_s_c0_flexgen: clk-s-c0-flexgen {
|
||||
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,flexgen";
|
||||
|
||||
clocks = <&clk_s_c0_pll0 0>,
|
||||
<&clk_s_c0_pll1 0>,
|
||||
<&clk_s_c0_quadfs 0>,
|
||||
<&clk_s_c0_quadfs 1>,
|
||||
<&clk_s_c0_quadfs 2>,
|
||||
<&clk_s_c0_quadfs 3>,
|
||||
<&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-icn-gpu",
|
||||
"clk-fdma",
|
||||
"clk-nand",
|
||||
"clk-hva",
|
||||
"clk-proc-stfe",
|
||||
"clk-proc-tp",
|
||||
"clk-rx-icn-dmu",
|
||||
"clk-rx-icn-hva",
|
||||
"clk-icn-cpu",
|
||||
"clk-tx-icn-dmu",
|
||||
"clk-mmc-0",
|
||||
"clk-mmc-1",
|
||||
"clk-jpegdec",
|
||||
"clk-ext2fa9",
|
||||
"clk-ic-bdisp-0",
|
||||
"clk-ic-bdisp-1",
|
||||
"clk-pp-dmu",
|
||||
"clk-vid-dmu",
|
||||
"clk-dss-lpc",
|
||||
"clk-st231-aud-0",
|
||||
"clk-st231-gp-1",
|
||||
"clk-st231-dmu",
|
||||
"clk-icn-lmi",
|
||||
"clk-tx-icn-disp-1",
|
||||
"clk-icn-sbc",
|
||||
"clk-stfe-frc2",
|
||||
"clk-eth-phy",
|
||||
"clk-eth-ref-phyclk",
|
||||
"clk-flash-promip",
|
||||
"clk-main-disp",
|
||||
"clk-aux-disp",
|
||||
"clk-compo-dvp";
|
||||
};
|
||||
@@ -15,6 +15,9 @@ Required properties:
|
||||
"st,stih416-quadfs432", "st,quadfs"
|
||||
"st,stih416-quadfs660-E", "st,quadfs"
|
||||
"st,stih416-quadfs660-F", "st,quadfs"
|
||||
"st,stih407-quadfs660-C", "st,quadfs"
|
||||
"st,stih407-quadfs660-D", "st,quadfs"
|
||||
|
||||
|
||||
- #clock-cells : from common clock binding; shall be set to 1.
|
||||
|
||||
@@ -32,14 +35,14 @@ Required properties:
|
||||
|
||||
Example:
|
||||
|
||||
CLOCKGEN_E: CLOCKGEN_E {
|
||||
clockgen_e: clockgen-e@fd3208bc {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,stih416-quadfs660-E", "st,quadfs";
|
||||
reg = <0xfd3208bc 0xB0>;
|
||||
|
||||
clocks = <&CLK_SYSIN>;
|
||||
clock-output-names = "CLK_M_PIX_MDTP_0",
|
||||
"CLK_M_PIX_MDTP_1",
|
||||
"CLK_M_PIX_MDTP_2",
|
||||
"CLK_M_MPELPC";
|
||||
clocks = <&clk_sysin>;
|
||||
clock-output-names = "clk-m-pix-mdtp-0",
|
||||
"clk-m-pix-mdtp-1",
|
||||
"clk-m-pix-mdtp-2",
|
||||
"clk-m-mpelpc";
|
||||
};
|
||||
|
||||
@@ -9,11 +9,13 @@ Required properties:
|
||||
"allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
|
||||
"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
|
||||
"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
|
||||
"allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
|
||||
"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
|
||||
"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
|
||||
"allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
|
||||
"allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
|
||||
"allwinner,sun4i-a10-axi-clk" - for the AXI clock
|
||||
"allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
|
||||
"allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
|
||||
"allwinner,sun4i-a10-ahb-clk" - for the AHB clock
|
||||
"allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
|
||||
@@ -23,13 +25,16 @@ Required properties:
|
||||
"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
|
||||
"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
|
||||
"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
|
||||
"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
|
||||
"allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
|
||||
"allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
|
||||
"allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
|
||||
"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
|
||||
"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
|
||||
"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
|
||||
"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
|
||||
"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
|
||||
"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
|
||||
"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
|
||||
"allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
|
||||
"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
|
||||
@@ -37,8 +42,10 @@ Required properties:
|
||||
"allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
|
||||
"allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
|
||||
"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
|
||||
"allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
|
||||
"allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
|
||||
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
|
||||
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
|
||||
"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
|
||||
"allwinner,sun7i-a20-out-clk" - for the external output clocks
|
||||
"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
|
||||
|
||||
@@ -9057,6 +9057,13 @@ L: linux-pm@vger.kernel.org
|
||||
S: Supported
|
||||
F: drivers/thermal/ti-soc-thermal/
|
||||
|
||||
TI CLOCK DRIVER
|
||||
M: Tero Kristo <t-kristo@ti.com>
|
||||
L: linux-omap@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/clk/ti/
|
||||
F: include/linux/clk/ti.h
|
||||
|
||||
TI FLASH MEDIA INTERFACE DRIVER
|
||||
M: Alex Dubov <oakad@yahoo.com>
|
||||
S: Maintained
|
||||
|
||||
@@ -31,6 +31,16 @@
|
||||
pinctrl2 = &pinctrl_2;
|
||||
};
|
||||
|
||||
pmu_system_controller: system-controller@10020000 {
|
||||
clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
|
||||
"clkout4", "clkout8", "clkout9";
|
||||
clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
|
||||
<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
|
||||
<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
|
||||
<&clock CLK_XUSBXTI>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sysram@02020000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x02020000 0x20000>;
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user