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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Conflicts were simple overlapping changes in microchip driver. Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
+3
-4
@@ -11,6 +11,7 @@
|
||||
#
|
||||
.*
|
||||
*.a
|
||||
*.asn1.[ch]
|
||||
*.bin
|
||||
*.bz2
|
||||
*.c.[012]*.*
|
||||
@@ -22,6 +23,7 @@
|
||||
*.gz
|
||||
*.i
|
||||
*.ko
|
||||
*.lex.c
|
||||
*.ll
|
||||
*.lst
|
||||
*.lz4
|
||||
@@ -37,6 +39,7 @@
|
||||
*.so.dbg
|
||||
*.su
|
||||
*.symtypes
|
||||
*.tab.[ch]
|
||||
*.tar
|
||||
*.xz
|
||||
Module.symvers
|
||||
@@ -129,7 +132,3 @@ all.config
|
||||
|
||||
# Kdevelop4
|
||||
*.kdev4
|
||||
|
||||
#Automatically generated by ASN.1 compiler
|
||||
net/ipv4/netfilter/nf_nat_snmp_basic-asn1.c
|
||||
net/ipv4/netfilter/nf_nat_snmp_basic-asn1.h
|
||||
|
||||
+13
-3
@@ -268,9 +268,19 @@ The common clock framework uses two global locks, the prepare lock and the
|
||||
enable lock.
|
||||
|
||||
The enable lock is a spinlock and is held across calls to the .enable,
|
||||
.disable and .is_enabled operations. Those operations are thus not allowed to
|
||||
sleep, and calls to the clk_enable(), clk_disable() and clk_is_enabled() API
|
||||
functions are allowed in atomic context.
|
||||
.disable operations. Those operations are thus not allowed to sleep,
|
||||
and calls to the clk_enable(), clk_disable() API functions are allowed in
|
||||
atomic context.
|
||||
|
||||
For clk_is_enabled() API, it is also designed to be allowed to be used in
|
||||
atomic context. However, it doesn't really make any sense to hold the enable
|
||||
lock in core, unless you want to do something else with the information of
|
||||
the enable state with that lock held. Otherwise, seeing if a clk is enabled is
|
||||
a one-shot read of the enabled state, which could just as easily change after
|
||||
the function returns because the lock is released. Thus the user of this API
|
||||
needs to handle synchronizing the read of the state with whatever they're
|
||||
using it for to make sure that the enable state doesn't change during that
|
||||
time.
|
||||
|
||||
The prepare lock is a mutex and is held across calls to all other operations.
|
||||
All those operations are allowed to sleep, and calls to the corresponding API
|
||||
|
||||
@@ -136,6 +136,19 @@ Sorting
|
||||
.. kernel-doc:: lib/list_sort.c
|
||||
:export:
|
||||
|
||||
Text Searching
|
||||
--------------
|
||||
|
||||
.. kernel-doc:: lib/textsearch.c
|
||||
:doc: ts_intro
|
||||
|
||||
.. kernel-doc:: lib/textsearch.c
|
||||
:export:
|
||||
|
||||
.. kernel-doc:: include/linux/textsearch.h
|
||||
:functions: textsearch_find textsearch_next \
|
||||
textsearch_get_pattern textsearch_get_pattern_len
|
||||
|
||||
UUID/GUID
|
||||
---------
|
||||
|
||||
|
||||
@@ -6,6 +6,7 @@ The MediaTek AUDSYS controller provides various clocks to the system.
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-audsys", "syscon"
|
||||
- "mediatek,mt7622-audsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
@@ -13,10 +14,19 @@ The AUDSYS controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
Required sub-nodes:
|
||||
-------
|
||||
For common binding part and usage, refer to
|
||||
../sonud/mt2701-afe-pcm.txt.
|
||||
|
||||
Example:
|
||||
|
||||
audsys: audsys@11220000 {
|
||||
compatible = "mediatek,mt7622-audsys", "syscon";
|
||||
reg = <0 0x11220000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
audsys: clock-controller@11220000 {
|
||||
compatible = "mediatek,mt7622-audsys", "syscon";
|
||||
reg = <0 0x11220000 0 0x2000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
afe: audio-controller {
|
||||
...
|
||||
};
|
||||
};
|
||||
|
||||
@@ -0,0 +1,36 @@
|
||||
* Clock bindings for Freescale i.MX6 SLL
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx6sll-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
- clocks: list of clock specifiers, must contain an entry for each required
|
||||
entry in clock-names
|
||||
- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sll-clock.h
|
||||
for the full list of i.MX6 SLL clock IDs.
|
||||
|
||||
Examples:
|
||||
|
||||
#include <dt-bindings/clock/imx6sll-clock.h>
|
||||
|
||||
clks: clock-controller@20c4000 {
|
||||
compatible = "fsl,imx6sll-ccm";
|
||||
reg = <0x020c4000 0x4000>;
|
||||
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
|
||||
clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
|
||||
};
|
||||
|
||||
uart1: serial@2020000 {
|
||||
compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02020000 0x4000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SLL_CLK_UART1_IPG>,
|
||||
<&clks IMX6SLL_CLK_UART1_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
@@ -0,0 +1,20 @@
|
||||
Device Tree Clock bindings for Intel's SoCFPGA Stratix10 platform
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be
|
||||
"intel,stratix10-clkmgr"
|
||||
|
||||
- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
|
||||
|
||||
- #clock-cells : from common clock binding, shall be set to 1.
|
||||
|
||||
Example:
|
||||
clkmgr: clock-controller@ffd10000 {
|
||||
compatible = "intel,stratix10-clkmgr";
|
||||
reg = <0xffd10000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@@ -22,7 +22,9 @@ Required Properties:
|
||||
- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
|
||||
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
|
||||
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
|
||||
- "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
|
||||
- "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
|
||||
- "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
|
||||
- "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
|
||||
|
||||
- reg: Base address and length of the memory resource used by the CPG/MSSR
|
||||
@@ -32,8 +34,8 @@ Required Properties:
|
||||
clock-names
|
||||
- clock-names: List of external parent clock names. Valid names are:
|
||||
- "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
|
||||
r8a7795, r8a7796, r8a77970, r8a77995)
|
||||
- "extalr" (r8a7795, r8a7796, r8a77970)
|
||||
r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77995)
|
||||
- "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
|
||||
- "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
|
||||
|
||||
- #clock-cells: Must be 2
|
||||
|
||||
@@ -32,6 +32,7 @@ clock-output-names:
|
||||
- "clkin_i2s" - external I2S clock - optional,
|
||||
- "gmac_clkin" - external GMAC clock - optional
|
||||
- "phy_50m_out" - output clock of the pll in the mac phy
|
||||
- "hdmi_phy" - output clock of the hdmi phy pll - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
|
||||
@@ -0,0 +1,25 @@
|
||||
Binding for Silicon Labs 544 programmable I2C clock generator.
|
||||
|
||||
Reference
|
||||
This binding uses the common clock binding[1]. Details about the device can be
|
||||
found in the datasheet[2].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Si544 datasheet
|
||||
https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf
|
||||
|
||||
Required properties:
|
||||
- compatible: One of "silabs,si514a", "silabs,si514b" "silabs,si514c" according
|
||||
to the speed grade of the chip.
|
||||
- reg: I2C device address.
|
||||
- #clock-cells: From common clock bindings: Shall be 0.
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names: From common clock bindings. Recommended to be "si544".
|
||||
|
||||
Example:
|
||||
si544: clock-controller@55 {
|
||||
reg = <0x55>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si544b";
|
||||
};
|
||||
@@ -0,0 +1,60 @@
|
||||
STMicroelectronics STM32 Peripheral Reset Clock Controller
|
||||
==========================================================
|
||||
|
||||
The RCC IP is both a reset and a clock controller.
|
||||
|
||||
RCC makes also power management (resume/supend and wakeup interrupt).
|
||||
|
||||
Please also refer to reset.txt for common reset controller binding usage.
|
||||
|
||||
Please also refer to clock-bindings.txt for common clock controller
|
||||
binding usage.
|
||||
|
||||
|
||||
Required properties:
|
||||
- compatible: "st,stm32mp1-rcc", "syscon"
|
||||
- reg: should be register base and length as documented in the datasheet
|
||||
- #clock-cells: 1, device nodes should specify the clock in their
|
||||
"clocks" property, containing a phandle to the clock device node,
|
||||
an index specifying the clock to use.
|
||||
- #reset-cells: Shall be 1
|
||||
- interrupts: Should contain a general interrupt line and a interrupt line
|
||||
to the wake-up of processor (CSTOP).
|
||||
|
||||
Example:
|
||||
rcc: rcc@50000000 {
|
||||
compatible = "st,stm32mp1-rcc", "syscon";
|
||||
reg = <0x50000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>,
|
||||
<GIC_SPI 145 IRQ_TYPE_NONE>;
|
||||
};
|
||||
|
||||
Specifying clocks
|
||||
=================
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/stm32mp1-clks.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
Specifying softreset control of devices
|
||||
=======================================
|
||||
|
||||
Device nodes should specify the reset channel required in their "resets"
|
||||
property, containing a phandle to the reset device node and an index specifying
|
||||
which channel to use.
|
||||
The index is the bit number within the RCC registers bank, starting from RCC
|
||||
base address.
|
||||
It is calculated as: index = register_offset / 4 * 32 + bit_offset.
|
||||
Where bit_offset is the bit offset within the register.
|
||||
|
||||
For example on STM32MP1, for LTDC reset:
|
||||
ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset
|
||||
= 0x180 / 4 * 32 + 0 = 3072
|
||||
|
||||
The list of valid indices for STM32MP1 is available in:
|
||||
include/dt-bindings/reset-controller/stm32mp1-resets.h
|
||||
|
||||
This file implements defines like:
|
||||
#define LTDC_R 3072
|
||||
@@ -20,6 +20,7 @@ Required properties :
|
||||
- "allwinner,sun50i-a64-ccu"
|
||||
- "allwinner,sun50i-a64-r-ccu"
|
||||
- "allwinner,sun50i-h5-ccu"
|
||||
- "allwinner,sun50i-h6-ccu"
|
||||
- "nextthing,gr8-ccu"
|
||||
|
||||
- reg: Must contain the registers base address and length
|
||||
@@ -31,6 +32,9 @@ Required properties :
|
||||
- #clock-cells : must contain 1
|
||||
- #reset-cells : must contain 1
|
||||
|
||||
For the main CCU on H6, one more clock is needed:
|
||||
- "iosc": the SoC's internal frequency oscillator
|
||||
|
||||
For the PRCM CCUs on A83T/H3/A64, two more clocks are needed:
|
||||
- "pll-periph": the SoC's peripheral PLL from the main CCU
|
||||
- "iosc": the SoC's internal frequency oscillator
|
||||
|
||||
@@ -0,0 +1,93 @@
|
||||
Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP clocks
|
||||
|
||||
TI DA8XX/OMAP-L13X/AM17XX/AM18XX SoCs contain a general purpose set of
|
||||
registers call CFGCHIPn. Some of these registers function as clock
|
||||
gates. This document describes the bindings for those clocks.
|
||||
|
||||
All of the clock nodes described below must be child nodes of a CFGCHIP node
|
||||
(compatible = "ti,da830-cfgchip").
|
||||
|
||||
USB PHY clocks
|
||||
--------------
|
||||
Required properties:
|
||||
- compatible: shall be "ti,da830-usb-phy-clocks".
|
||||
- #clock-cells: from common clock binding; shall be set to 1.
|
||||
- clocks: phandles to the parent clocks corresponding to clock-names
|
||||
- clock-names: shall be "fck", "usb_refclkin", "auxclk"
|
||||
|
||||
This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz
|
||||
clock and the clock at index 1 is the USB 1.1 PHY 48MHz clock.
|
||||
|
||||
eHRPWM Time Base Clock (TBCLK)
|
||||
------------------------------
|
||||
Required properties:
|
||||
- compatible: shall be "ti,da830-tbclksync".
|
||||
- #clock-cells: from common clock binding; shall be set to 0.
|
||||
- clocks: phandle to the parent clock
|
||||
- clock-names: shall be "fck"
|
||||
|
||||
PLL DIV4.5 divider
|
||||
------------------
|
||||
Required properties:
|
||||
- compatible: shall be "ti,da830-div4p5ena".
|
||||
- #clock-cells: from common clock binding; shall be set to 0.
|
||||
- clocks: phandle to the parent clock
|
||||
- clock-names: shall be "pll0_pllout"
|
||||
|
||||
EMIFA clock source (ASYNC1)
|
||||
---------------------------
|
||||
Required properties:
|
||||
- compatible: shall be "ti,da850-async1-clksrc".
|
||||
- #clock-cells: from common clock binding; shall be set to 0.
|
||||
- clocks: phandles to the parent clocks corresponding to clock-names
|
||||
- clock-names: shall be "pll0_sysclk3", "div4.5"
|
||||
|
||||
ASYNC3 clock source
|
||||
-------------------
|
||||
Required properties:
|
||||
- compatible: shall be "ti,da850-async3-clksrc".
|
||||
- #clock-cells: from common clock binding; shall be set to 0.
|
||||
- clocks: phandles to the parent clocks corresponding to clock-names
|
||||
- clock-names: shall be "pll0_sysclk2", "pll1_sysclk2"
|
||||
|
||||
Examples:
|
||||
|
||||
cfgchip: syscon@1417c {
|
||||
compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
|
||||
reg = <0x1417c 0x14>;
|
||||
|
||||
usb_phy_clk: usb-phy-clocks {
|
||||
compatible = "ti,da830-usb-phy-clocks";
|
||||
#clock-cells = <1>;
|
||||
clocks = <&psc1 1>, <&usb_refclkin>, <&pll0_auxclk>;
|
||||
clock-names = "fck", "usb_refclkin", "auxclk";
|
||||
};
|
||||
ehrpwm_tbclk: ehrpwm_tbclk {
|
||||
compatible = "ti,da830-tbclksync";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&psc1 17>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
div4p5_clk: div4.5 {
|
||||
compatible = "ti,da830-div4p5ena";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&pll0_pllout>;
|
||||
clock-names = "pll0_pllout";
|
||||
};
|
||||
async1_clk: async1 {
|
||||
compatible = "ti,da850-async1-clksrc";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&pll0_sysclk 3>, <&div4p5_clk>;
|
||||
clock-names = "pll0_sysclk3", "div4.5";
|
||||
};
|
||||
async3_clk: async3 {
|
||||
compatible = "ti,da850-async3-clksrc";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>;
|
||||
clock-names = "pll0_sysclk2", "pll1_sysclk2";
|
||||
};
|
||||
};
|
||||
|
||||
Also see:
|
||||
- Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
@@ -0,0 +1,96 @@
|
||||
Binding for TI DaVinci PLL Controllers
|
||||
|
||||
The PLL provides clocks to most of the components on the SoC. In addition
|
||||
to the PLL itself, this controller also contains bypasses, gates, dividers,
|
||||
an multiplexers for various clock signals.
|
||||
|
||||
Required properties:
|
||||
- compatible: shall be one of:
|
||||
- "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
|
||||
- "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
|
||||
- reg: physical base address and size of the controller's register area.
|
||||
- clocks: phandles corresponding to the clock names
|
||||
- clock-names: names of the clock sources - depends on compatible string
|
||||
- for "ti,da850-pll0", shall be "clksrc", "extclksrc"
|
||||
- for "ti,da850-pll1", shall be "clksrc"
|
||||
|
||||
Optional properties:
|
||||
- ti,clkmode-square-wave: Indicates that the the board is supplying a square
|
||||
wave input on the OSCIN pin instead of using a crystal oscillator.
|
||||
This property is only valid when compatible = "ti,da850-pll0".
|
||||
|
||||
|
||||
Optional child nodes:
|
||||
|
||||
pllout
|
||||
Describes the main PLL clock output (before POSTDIV). The node name must
|
||||
be "pllout".
|
||||
|
||||
Required properties:
|
||||
- #clock-cells: shall be 0
|
||||
|
||||
sysclk
|
||||
Describes the PLLDIVn divider clocks that provide the SYSCLKn clock
|
||||
domains. The node name must be "sysclk". Consumers of this node should
|
||||
use "n" in "SYSCLKn" as the index parameter for the clock cell.
|
||||
|
||||
Required properties:
|
||||
- #clock-cells: shall be 1
|
||||
|
||||
auxclk
|
||||
Describes the AUXCLK output of the PLL. The node name must be "auxclk".
|
||||
This child node is only valid when compatible = "ti,da850-pll0".
|
||||
|
||||
Required properties:
|
||||
- #clock-cells: shall be 0
|
||||
|
||||
obsclk
|
||||
Describes the OBSCLK output of the PLL. The node name must be "obsclk".
|
||||
|
||||
Required properties:
|
||||
- #clock-cells: shall be 0
|
||||
|
||||
|
||||
Examples:
|
||||
|
||||
pll0: clock-controller@11000 {
|
||||
compatible = "ti,da850-pll0";
|
||||
reg = <0x11000 0x1000>;
|
||||
clocks = <&ref_clk>, <&pll1_sysclk 3>;
|
||||
clock-names = "clksrc", "extclksrc";
|
||||
ti,clkmode-square-wave;
|
||||
|
||||
pll0_pllout: pllout {
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
pll0_sysclk: sysclk {
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
pll0_auxclk: auxclk {
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
pll0_obsclk: obsclk {
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pll1: clock-controller@21a000 {
|
||||
compatible = "ti,da850-pll1";
|
||||
reg = <0x21a000 0x1000>;
|
||||
clocks = <&ref_clk>;
|
||||
clock-names = "clksrc";
|
||||
|
||||
pll0_sysclk: sysclk {
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
pll0_obsclk: obsclk {
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
Also see:
|
||||
- Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
@@ -0,0 +1,71 @@
|
||||
Binding for TI DaVinci Power Sleep Controller (PSC)
|
||||
|
||||
The PSC provides power management, clock gating and reset functionality. It is
|
||||
primarily used for clocking.
|
||||
|
||||
Required properties:
|
||||
- compatible: shall be one of:
|
||||
- "ti,da850-psc0" for PSC0 on DA850/OMAP-L138/AM18XX
|
||||
- "ti,da850-psc1" for PSC1 on DA850/OMAP-L138/AM18XX
|
||||
- reg: physical base address and size of the controller's register area
|
||||
- #clock-cells: from common clock binding; shall be set to 1
|
||||
- #power-domain-cells: from generic power domain binding; shall be set to 1.
|
||||
- clocks: phandles to clocks corresponding to the clock-names property
|
||||
- clock-names: list of parent clock names - depends on compatible value
|
||||
- for "ti,da850-psc0", shall be "pll0_sysclk1", "pll0_sysclk2",
|
||||
"pll0_sysclk4", "pll0_sysclk6", "async1"
|
||||
- for "ti,da850-psc1", shall be "pll0_sysclk2", "pll0_sysclk4", "async3"
|
||||
|
||||
Optional properties:
|
||||
- #reset-cells: from reset binding; shall be set to 1 - only applicable when
|
||||
at least one local domain provides a local reset.
|
||||
|
||||
Consumers:
|
||||
|
||||
Clock, power domain and reset consumers shall use the local power domain
|
||||
module ID (LPSC) as the index corresponding to the clock cell. Refer to
|
||||
the device-specific datasheet to find these numbers. NB: Most local
|
||||
domains only provide a clock/power domain and not a reset.
|
||||
|
||||
Examples:
|
||||
|
||||
psc0: clock-controller@10000 {
|
||||
compatible = "ti,da850-psc0";
|
||||
reg = <0x10000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>,
|
||||
<&pll0_sysclk 4>, <&pll0_sysclk 6>, <&async1_clk>;
|
||||
clock_names = "pll0_sysclk1", "pll0_sysclk2",
|
||||
"pll0_sysclk4", "pll0_sysclk6", "async1";
|
||||
};
|
||||
psc1: clock-controller@227000 {
|
||||
compatible = "ti,da850-psc1";
|
||||
reg = <0x227000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>, <&async3_clk>;
|
||||
clock_names = "pll0_sysclk2", "pll0_sysclk4", "async3";
|
||||
};
|
||||
|
||||
/* consumer */
|
||||
dsp: dsp@11800000 {
|
||||
compatible = "ti,da850-dsp";
|
||||
reg = <0x11800000 0x40000>,
|
||||
<0x11e00000 0x8000>,
|
||||
<0x11f00000 0x8000>,
|
||||
<0x01c14044 0x4>,
|
||||
<0x01c14174 0x8>;
|
||||
reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <28>;
|
||||
clocks = <&psc0 15>;
|
||||
power-domains = <&psc0 15>;
|
||||
resets = <&psc0 15>;
|
||||
};
|
||||
|
||||
Also see:
|
||||
- Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
- Documentation/devicetree/bindings/power/power_domain.txt
|
||||
- Documentation/devicetree/bindings/reset/reset.txt
|
||||
@@ -75,6 +75,9 @@ Optional properties:
|
||||
- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0,
|
||||
see [2]
|
||||
- ti,set-rate-parent : clk_set_rate is propagated to parent
|
||||
- ti,latch-bit : latch the divider value to HW, only needed if the register
|
||||
access requires this. As an example dra76x DPLL_GMAC H14 divider implements
|
||||
such behavior.
|
||||
|
||||
Examples:
|
||||
dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
|
||||
|
||||
@@ -48,6 +48,9 @@ Optional properties:
|
||||
zero
|
||||
- ti,set-rate-parent : clk_set_rate is propagated to parent clock,
|
||||
not supported by the composite-mux-clock subtype
|
||||
- ti,latch-bit : latch the mux value to HW, only needed if the register
|
||||
access requires this. As an example, dra7x DPLL_GMAC H14 muxing
|
||||
implements such behavior.
|
||||
|
||||
Examples:
|
||||
|
||||
|
||||
@@ -0,0 +1,25 @@
|
||||
Ingenic JZ47xx PWM Controller
|
||||
=============================
|
||||
|
||||
Required properties:
|
||||
- compatible: One of:
|
||||
* "ingenic,jz4740-pwm"
|
||||
* "ingenic,jz4770-pwm"
|
||||
* "ingenic,jz4780-pwm"
|
||||
- #pwm-cells: Should be 3. See pwm.txt in this directory for a description
|
||||
of the cells format.
|
||||
- clocks : phandle to the external clock.
|
||||
- clock-names : Should be "ext".
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
pwm: pwm@10002000 {
|
||||
compatible = "ingenic,jz4740-pwm";
|
||||
reg = <0x10002000 0x1000>;
|
||||
|
||||
#pwm-cells = <3>;
|
||||
|
||||
clocks = <&ext>;
|
||||
clock-names = "ext";
|
||||
};
|
||||
@@ -7,6 +7,8 @@ See ../mfd/stm32-lptimer.txt for details about the parent node.
|
||||
|
||||
Required parameters:
|
||||
- compatible: Must be "st,stm32-pwm-lp".
|
||||
- #pwm-cells: Should be set to 3. This PWM chip uses the default 3 cells
|
||||
bindings defined in pwm.txt.
|
||||
|
||||
Optional properties:
|
||||
- pinctrl-names: Set to "default".
|
||||
@@ -18,6 +20,7 @@ Example:
|
||||
...
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm-lp";
|
||||
#pwm-cells = <3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lppwm1_pins>;
|
||||
};
|
||||
|
||||
@@ -7,6 +7,8 @@ Required properties:
|
||||
- "allwinner,sun5i-a13-pwm"
|
||||
- "allwinner,sun7i-a20-pwm"
|
||||
- "allwinner,sun8i-h3-pwm"
|
||||
- "allwinner,sun50i-a64-pwm", "allwinner,sun5i-a13-pwm"
|
||||
- "allwinner,sun50i-h5-pwm", "allwinner,sun5i-a13-pwm"
|
||||
- reg: physical base address and length of the controller's registers
|
||||
- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
|
||||
the cells format.
|
||||
|
||||
@@ -2,6 +2,8 @@
|
||||
|
||||
Required Properties:
|
||||
- compatible: should be "renesas,pwm-rcar" and one of the following.
|
||||
- "renesas,pwm-r8a7743": for RZ/G1M
|
||||
- "renesas,pwm-r8a7745": for RZ/G1E
|
||||
- "renesas,pwm-r8a7778": for R-Car M1A
|
||||
- "renesas,pwm-r8a7779": for R-Car H1
|
||||
- "renesas,pwm-r8a7790": for R-Car H2
|
||||
@@ -9,6 +11,7 @@ Required Properties:
|
||||
- "renesas,pwm-r8a7794": for R-Car E2
|
||||
- "renesas,pwm-r8a7795": for R-Car H3
|
||||
- "renesas,pwm-r8a7796": for R-Car M3-W
|
||||
- "renesas,pwm-r8a77965": for R-Car M3-N
|
||||
- "renesas,pwm-r8a77995": for R-Car D3
|
||||
- reg: base address and length of the registers block for the PWM.
|
||||
- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
|
||||
@@ -17,13 +20,15 @@ Required Properties:
|
||||
- pinctrl-0: phandle, referring to a default pin configuration node.
|
||||
- pinctrl-names: Set to "default".
|
||||
|
||||
Example: R8A7790 (R-Car H2) PWM Timer node
|
||||
Example: R8A7743 (RZ/G1M) PWM Timer node
|
||||
|
||||
pwm0: pwm@e6e30000 {
|
||||
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
|
||||
compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
|
||||
reg = <0 0xe6e30000 0 0x8>;
|
||||
clocks = <&cpg CPG_MOD 523>;
|
||||
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 523>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&mstp5_clks R8A7790_CLK_PWM>;
|
||||
pinctrl-0 = <&pwm0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user