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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6 into for-davem
This commit is contained in:
@@ -7,6 +7,7 @@
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#include "bcma_private.h"
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#include <linux/bcma/bcma.h>
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#include <linux/slab.h>
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MODULE_DESCRIPTION("Broadcom's specific AMBA driver");
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MODULE_LICENSE("GPL");
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@@ -229,6 +229,7 @@ static void ar9003_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
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static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
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struct ath_tx_status *ts)
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{
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struct ar9003_txc *txc = (struct ar9003_txc *) ds;
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struct ar9003_txs *ads;
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u32 status;
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@@ -238,7 +239,11 @@ static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
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if ((status & AR_TxDone) == 0)
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return -EINPROGRESS;
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ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;
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ts->qid = MS(ads->ds_info, AR_TxQcuNum);
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if (!txc || (MS(txc->info, AR_TxQcuNum) == ts->qid))
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ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;
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else
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return -ENOENT;
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if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) ||
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(MS(ads->ds_info, AR_TxRxDesc) != 1)) {
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@@ -254,7 +259,6 @@ static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
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ts->ts_seqnum = MS(status, AR_SeqNum);
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ts->tid = MS(status, AR_TxTid);
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ts->qid = MS(ads->ds_info, AR_TxQcuNum);
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ts->desc_id = MS(ads->status1, AR_TxDescId);
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ts->ts_tstamp = ads->status4;
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ts->ts_status = 0;
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@@ -236,7 +236,7 @@ static void ar9003_paprd_get_gain_table(struct ath_hw *ah)
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memset(entry, 0, sizeof(ah->paprd_gain_table_entries));
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memset(index, 0, sizeof(ah->paprd_gain_table_index));
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for (i = 0; i < 32; i++) {
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for (i = 0; i < PAPRD_GAIN_TABLE_ENTRIES; i++) {
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entry[i] = REG_READ(ah, reg);
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index[i] = (entry[i] >> 24) & 0xff;
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reg += 4;
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@@ -246,13 +246,13 @@ static void ar9003_paprd_get_gain_table(struct ath_hw *ah)
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static unsigned int ar9003_get_desired_gain(struct ath_hw *ah, int chain,
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int target_power)
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{
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int olpc_gain_delta = 0;
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int olpc_gain_delta = 0, cl_gain_mod;
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int alpha_therm, alpha_volt;
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int therm_cal_value, volt_cal_value;
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int therm_value, volt_value;
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int thermal_gain_corr, voltage_gain_corr;
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int desired_scale, desired_gain = 0;
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u32 reg;
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u32 reg_olpc = 0, reg_cl_gain = 0;
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REG_CLR_BIT(ah, AR_PHY_PAPRD_TRAINER_STAT1,
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AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE);
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@@ -271,15 +271,29 @@ static unsigned int ar9003_get_desired_gain(struct ath_hw *ah, int chain,
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volt_value = REG_READ_FIELD(ah, AR_PHY_BB_THERM_ADC_4,
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AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE);
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if (chain == 0)
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reg = AR_PHY_TPC_11_B0;
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else if (chain == 1)
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reg = AR_PHY_TPC_11_B1;
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else
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reg = AR_PHY_TPC_11_B2;
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switch (chain) {
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case 0:
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reg_olpc = AR_PHY_TPC_11_B0;
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reg_cl_gain = AR_PHY_CL_TAB_0;
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break;
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case 1:
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reg_olpc = AR_PHY_TPC_11_B1;
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reg_cl_gain = AR_PHY_CL_TAB_1;
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break;
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case 2:
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reg_olpc = AR_PHY_TPC_11_B2;
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reg_cl_gain = AR_PHY_CL_TAB_2;
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break;
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default:
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ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
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"Invalid chainmask: %d\n", chain);
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break;
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}
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olpc_gain_delta = REG_READ_FIELD(ah, reg,
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olpc_gain_delta = REG_READ_FIELD(ah, reg_olpc,
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AR_PHY_TPC_11_OLPC_GAIN_DELTA);
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cl_gain_mod = REG_READ_FIELD(ah, reg_cl_gain,
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AR_PHY_CL_TAB_CL_GAIN_MOD);
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if (olpc_gain_delta >= 128)
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olpc_gain_delta = olpc_gain_delta - 256;
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@@ -289,7 +303,7 @@ static unsigned int ar9003_get_desired_gain(struct ath_hw *ah, int chain,
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voltage_gain_corr = (alpha_volt * (volt_value - volt_cal_value) +
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(128 / 2)) / 128;
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desired_gain = target_power - olpc_gain_delta - thermal_gain_corr -
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voltage_gain_corr + desired_scale;
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voltage_gain_corr + desired_scale + cl_gain_mod;
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return desired_gain;
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}
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@@ -727,7 +741,7 @@ int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain)
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desired_gain = ar9003_get_desired_gain(ah, chain, train_power);
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gain_index = 0;
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for (i = 0; i < 32; i++) {
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for (i = 0; i < PAPRD_GAIN_TABLE_ENTRIES; i++) {
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if (ah->paprd_gain_table_index[i] >= desired_gain)
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break;
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gain_index++;
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@@ -1121,6 +1121,9 @@
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#define AR_PHY_POWERTX_RATE8_POWERTXHT40_5 0x3F00
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#define AR_PHY_POWERTX_RATE8_POWERTXHT40_5_S 8
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#define AR_PHY_CL_TAB_CL_GAIN_MOD 0x1f
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#define AR_PHY_CL_TAB_CL_GAIN_MOD_S 0
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void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
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#endif /* AR9003_PHY_H */
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@@ -101,6 +101,11 @@ enum buffer_type {
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#define ATH_TXSTATUS_RING_SIZE 64
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#define DS2PHYS(_dd, _ds) \
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((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
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#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
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#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
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struct ath_descdma {
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void *dd_desc;
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dma_addr_t dd_desc_paddr;
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@@ -361,6 +361,7 @@ void ath_beacon_tasklet(unsigned long data)
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath_buf *bf = NULL;
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struct ieee80211_vif *vif;
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struct ath_tx_status ts;
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int slot;
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u32 bfaddr, bc = 0;
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@@ -385,7 +386,9 @@ void ath_beacon_tasklet(unsigned long data)
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ath_dbg(common, ATH_DBG_BSTUCK,
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"beacon is officially stuck\n");
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sc->sc_flags |= SC_OP_TSF_RESET;
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spin_lock(&sc->sc_pcu_lock);
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ath_reset(sc, true);
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spin_unlock(&sc->sc_pcu_lock);
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}
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return;
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@@ -465,6 +468,11 @@ void ath_beacon_tasklet(unsigned long data)
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ath9k_hw_txstart(ah, sc->beacon.beaconq);
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sc->beacon.ast_be_xmit += bc; /* XXX per-vif? */
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if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
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spin_lock_bh(&sc->sc_pcu_lock);
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ath9k_hw_txprocdesc(ah, bf->bf_desc, (void *)&ts);
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spin_unlock_bh(&sc->sc_pcu_lock);
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}
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}
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}
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@@ -49,6 +49,8 @@ static struct usb_device_id ath9k_hif_usb_ids[] = {
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.driver_info = AR9280_USB }, /* Netgear WNDA3200 */
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{ USB_DEVICE(0x083A, 0xA704),
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.driver_info = AR9280_USB }, /* SMC Networks */
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{ USB_DEVICE(0x0411, 0x017f),
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.driver_info = AR9280_USB }, /* Sony UWA-BR100 */
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{ USB_DEVICE(0x0cf3, 0x20ff),
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.driver_info = STORAGE_DEVICE },
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@@ -299,10 +299,6 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
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struct list_head *head, const char *name,
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int nbuf, int ndesc, bool is_tx)
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{
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#define DS2PHYS(_dd, _ds) \
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((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
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#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
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#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
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struct ath_common *common = ath9k_hw_common(sc->sc_ah);
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u8 *ds;
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struct ath_buf *bf;
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@@ -397,9 +393,6 @@ fail2:
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fail:
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memset(dd, 0, sizeof(*dd));
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return error;
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#undef ATH_DESC_4KB_BOUND_CHECK
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#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
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#undef DS2PHYS
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}
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void ath9k_init_crypto(struct ath_softc *sc)
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@@ -617,8 +617,11 @@ void ath_hw_check(struct work_struct *work)
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ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, "
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"busy=%d (try %d)\n", busy, sc->hw_busy_count + 1);
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if (busy >= 99) {
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if (++sc->hw_busy_count >= 3)
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if (++sc->hw_busy_count >= 3) {
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spin_lock_bh(&sc->sc_pcu_lock);
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ath_reset(sc, true);
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spin_unlock_bh(&sc->sc_pcu_lock);
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}
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} else if (busy >= 0)
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sc->hw_busy_count = 0;
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@@ -637,7 +640,9 @@ static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
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/* Rx is hung for more than 500ms. Reset it */
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ath_dbg(common, ATH_DBG_RESET,
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"Possible RX hang, resetting");
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spin_lock_bh(&sc->sc_pcu_lock);
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ath_reset(sc, true);
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spin_unlock_bh(&sc->sc_pcu_lock);
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count = 0;
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}
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} else
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@@ -674,7 +679,9 @@ void ath9k_tasklet(unsigned long data)
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if ((status & ATH9K_INT_FATAL) ||
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(status & ATH9K_INT_BB_WATCHDOG)) {
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spin_lock(&sc->sc_pcu_lock);
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ath_reset(sc, true);
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spin_unlock(&sc->sc_pcu_lock);
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return;
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}
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@@ -980,7 +987,6 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
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del_timer_sync(&common->ani.timer);
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ath9k_ps_wakeup(sc);
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spin_lock_bh(&sc->sc_pcu_lock);
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ieee80211_stop_queues(hw);
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@@ -1023,7 +1029,6 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
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}
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ieee80211_wake_queues(hw);
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spin_unlock_bh(&sc->sc_pcu_lock);
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/* Start ANI */
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if (!common->disable_ani)
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@@ -2326,9 +2331,9 @@ static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
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ath9k_ps_wakeup(sc);
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spin_lock_bh(&sc->sc_pcu_lock);
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drain_txq = ath_drain_all_txq(sc, false);
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spin_unlock_bh(&sc->sc_pcu_lock);
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if (!drain_txq)
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ath_reset(sc, false);
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spin_unlock_bh(&sc->sc_pcu_lock);
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ath9k_ps_restore(sc);
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ieee80211_wake_queues(hw);
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@@ -566,11 +566,8 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
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rcu_read_unlock();
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if (needreset) {
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||||
spin_unlock_bh(&sc->sc_pcu_lock);
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if (needreset)
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ath_reset(sc, false);
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spin_lock_bh(&sc->sc_pcu_lock);
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||||
}
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}
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static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
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@@ -2170,7 +2167,9 @@ static void ath_tx_complete_poll_work(struct work_struct *work)
|
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if (needreset) {
|
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ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
|
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"tx hung, resetting the chip\n");
|
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spin_lock_bh(&sc->sc_pcu_lock);
|
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ath_reset(sc, true);
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spin_unlock_bh(&sc->sc_pcu_lock);
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}
|
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ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
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|
||||
@@ -472,7 +472,7 @@ static struct sk_buff *carl9170_rx_copy_data(u8 *buf, int len)
|
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u8 *qc = ieee80211_get_qos_ctl(hdr);
|
||||
reserved += NET_IP_ALIGN;
|
||||
|
||||
if (*qc & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
|
||||
if (*qc & IEEE80211_QOS_CTL_A_MSDU_PRESENT)
|
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reserved += NET_IP_ALIGN;
|
||||
}
|
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|
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|
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@@ -11,6 +11,7 @@ b43-$(CONFIG_B43_PHY_N) += phy_n.o
|
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b43-$(CONFIG_B43_PHY_LP) += phy_lp.o
|
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b43-$(CONFIG_B43_PHY_LP) += tables_lpphy.o
|
||||
b43-$(CONFIG_B43_PHY_HT) += phy_ht.o
|
||||
b43-$(CONFIG_B43_PHY_HT) += tables_phy_ht.o
|
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b43-$(CONFIG_B43_PHY_HT) += radio_2059.o
|
||||
b43-y += sysfs.o
|
||||
b43-y += xmit.o
|
||||
|
||||
@@ -24,9 +24,14 @@
|
||||
|
||||
#include "b43.h"
|
||||
#include "phy_ht.h"
|
||||
#include "tables_phy_ht.h"
|
||||
#include "radio_2059.h"
|
||||
#include "main.h"
|
||||
|
||||
/**************************************************
|
||||
* Radio 2059.
|
||||
**************************************************/
|
||||
|
||||
static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
|
||||
const struct b43_phy_ht_channeltab_e_radio2059 *e)
|
||||
{
|
||||
@@ -56,7 +61,7 @@ static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
|
||||
b43_radio_write(dev, 0x98, e->radio_syn98);
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
routing = i ? 0x800 : 0x400;
|
||||
routing = i ? R2059_RXRX1 : R2059_TXRX0;
|
||||
b43_radio_write(dev, routing | 0x4a, e->radio_rxtx4a);
|
||||
b43_radio_write(dev, routing | 0x58, e->radio_rxtx58);
|
||||
b43_radio_write(dev, routing | 0x5a, e->radio_rxtx5a);
|
||||
@@ -78,11 +83,120 @@ static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
|
||||
udelay(300);
|
||||
}
|
||||
|
||||
static void b43_radio_2059_init(struct b43_wldev *dev)
|
||||
{
|
||||
const u16 routing[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1 };
|
||||
const u16 radio_values[3][2] = {
|
||||
{ 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 },
|
||||
};
|
||||
u16 i, j;
|
||||
|
||||
b43_radio_write(dev, R2059_ALL | 0x51, 0x0070);
|
||||
b43_radio_write(dev, R2059_ALL | 0x5a, 0x0003);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(routing); i++)
|
||||
b43_radio_set(dev, routing[i] | 0x146, 0x3);
|
||||
|
||||
b43_radio_set(dev, 0x2e, 0x0078);
|
||||
b43_radio_set(dev, 0xc0, 0x0080);
|
||||
msleep(2);
|
||||
b43_radio_mask(dev, 0x2e, ~0x0078);
|
||||
b43_radio_mask(dev, 0xc0, ~0x0080);
|
||||
|
||||
if (1) { /* FIXME */
|
||||
b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x1);
|
||||
udelay(10);
|
||||
b43_radio_set(dev, R2059_RXRX1 | 0x0BF, 0x1);
|
||||
b43_radio_maskset(dev, R2059_RXRX1 | 0x19B, 0x3, 0x2);
|
||||
|
||||
b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x2);
|
||||
udelay(100);
|
||||
b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x2);
|
||||
|
||||
for (i = 0; i < 10000; i++) {
|
||||
if (b43_radio_read(dev, R2059_RXRX1 | 0x145) & 1) {
|
||||
i = 0;
|
||||
break;
|
||||
}
|
||||
udelay(100);
|
||||
}
|
||||
if (i)
|
||||
b43err(dev->wl, "radio 0x945 timeout\n");
|
||||
|
||||
b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x1);
|
||||
b43_radio_set(dev, 0xa, 0x60);
|
||||
|
||||
for (i = 0; i < 3; i++) {
|
||||
b43_radio_write(dev, 0x17F, radio_values[i][0]);
|
||||
b43_radio_write(dev, 0x13D, 0x6E);
|
||||
b43_radio_write(dev, 0x13E, radio_values[i][1]);
|
||||
b43_radio_write(dev, 0x13C, 0x55);
|
||||
|
||||
for (j = 0; j < 10000; j++) {
|
||||
if (b43_radio_read(dev, 0x140) & 2) {
|
||||
j = 0;
|
||||
break;
|
||||
}
|
||||
udelay(500);
|
||||
}
|
||||
if (j)
|
||||
b43err(dev->wl, "radio 0x140 timeout\n");
|
||||
|
||||
b43_radio_write(dev, 0x13C, 0x15);
|
||||
}
|
||||
|
||||
b43_radio_mask(dev, 0x17F, ~0x1);
|
||||
}
|
||||
|
||||
b43_radio_mask(dev, 0x11, 0x0008);
|
||||
}
|
||||
|
||||
/**************************************************
|
||||
* Channel switching ops.
|
||||
**************************************************/
|
||||
|
||||
static void b43_phy_ht_channel_setup(struct b43_wldev *dev,
|
||||
const struct b43_phy_ht_channeltab_e_phy *e,
|
||||
struct ieee80211_channel *new_channel)
|
||||
{
|
||||
/* TODO */
|
||||
bool old_band_5ghz;
|
||||
u8 i;
|
||||
|
||||
old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */
|
||||
if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
|
||||
/* TODO */
|
||||
} else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1);
|
||||
b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2);
|
||||
b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3);
|
||||
b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4);
|
||||
b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5);
|
||||
b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6);
|
||||
|
||||
/* TODO: some ops on PHY regs 0x0B0 and 0xC0A */
|
||||
|
||||
/* TODO: separated function? */
|
||||
for (i = 0; i < 3; i++) {
|
||||
u16 mask;
|
||||
u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8));
|
||||
|
||||
if (0) /* FIXME */
|
||||
mask = 0x2 << (i * 4);
|
||||
else
|
||||
mask = 0;
|
||||
b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask);
|
||||
|
||||
b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16);
|
||||
b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)),
|
||||
tmp & 0xFF);
|
||||
b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)),
|
||||
tmp & 0xFF);
|
||||
}
|
||||
|
||||
b43_phy_write(dev, 0x017e, 0x3830);
|
||||
}
|
||||
|
||||
static int b43_phy_ht_set_channel(struct b43_wldev *dev,
|
||||
@@ -139,6 +253,13 @@ static void b43_phy_ht_op_prepare_structs(struct b43_wldev *dev)
|
||||
memset(phy_ht, 0, sizeof(*phy_ht));
|
||||
}
|
||||
|
||||
static int b43_phy_ht_op_init(struct b43_wldev *dev)
|
||||
{
|
||||
b43_phy_ht_tables_init(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void b43_phy_ht_op_free(struct b43_wldev *dev)
|
||||
{
|
||||
struct b43_phy *phy = &dev->phy;
|
||||
@@ -162,6 +283,11 @@ static void b43_phy_ht_op_software_rfkill(struct b43_wldev *dev,
|
||||
b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, ~0, 0x1);
|
||||
b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, ~0);
|
||||
b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, ~0, 0x2);
|
||||
|
||||
if (dev->phy.radio_ver == 0x2059)
|
||||
b43_radio_2059_init(dev);
|
||||
else
|
||||
B43_WARN_ON(1);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -255,9 +381,7 @@ const struct b43_phy_operations b43_phyops_ht = {
|
||||
.allocate = b43_phy_ht_op_allocate,
|
||||
.free = b43_phy_ht_op_free,
|
||||
.prepare_structs = b43_phy_ht_op_prepare_structs,
|
||||
/*
|
||||
.init = b43_phy_ht_op_init,
|
||||
*/
|
||||
.phy_read = b43_phy_ht_op_read,
|
||||
.phy_write = b43_phy_ht_op_write,
|
||||
.phy_maskset = b43_phy_ht_op_maskset,
|
||||
|
||||
@@ -4,9 +4,16 @@
|
||||
#include "phy_common.h"
|
||||
|
||||
|
||||
#define B43_PHY_HT_BANDCTL 0x009 /* Band control */
|
||||
#define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */
|
||||
#define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */
|
||||
#define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */
|
||||
#define B43_PHY_HT_BW1 0x1CE
|
||||
#define B43_PHY_HT_BW2 0x1CF
|
||||
#define B43_PHY_HT_BW3 0x1D0
|
||||
#define B43_PHY_HT_BW4 0x1D1
|
||||
#define B43_PHY_HT_BW5 0x1D2
|
||||
#define B43_PHY_HT_BW6 0x1D3
|
||||
|
||||
#define B43_PHY_HT_RF_CTL1 B43_PHY_EXTG(0x010)
|
||||
|
||||
@@ -20,7 +27,12 @@
|
||||
|
||||
/* Values for PHY registers used on channel switching */
|
||||
struct b43_phy_ht_channeltab_e_phy {
|
||||
/* TODO */
|
||||
u16 bw1;
|
||||
u16 bw2;
|
||||
u16 bw3;
|
||||
u16 bw4;
|
||||
u16 bw5;
|
||||
u16 bw6;
|
||||
};
|
||||
|
||||
|
||||
|
||||
@@ -23,6 +23,141 @@
|
||||
#include "b43.h"
|
||||
#include "radio_2059.h"
|
||||
|
||||
#define RADIOREGS(r00, r01, r02, r03, r04, r05, r06, r07, r08, r09, \
|
||||
r10, r11, r12, r13, r14, r15, r16, r17, r18, r19, \
|
||||
r20, r21, r22, r23, r24, r25, r26, r27, r28) \
|
||||
.radio_syn16 = r00, \
|
||||
.radio_syn17 = r01, \
|
||||
.radio_syn22 = r02, \
|
||||
.radio_syn25 = r03, \
|
||||
.radio_syn27 = r04, \
|
||||
.radio_syn28 = r05, \
|
||||
.radio_syn29 = r06, \
|
||||
.radio_syn2c = r07, \
|
||||
.radio_syn2d = r08, \
|
||||
.radio_syn37 = r09, \
|
||||
.radio_syn41 = r10, \
|
||||
.radio_syn43 = r11, \
|
||||
.radio_syn47 = r12, \
|
||||
.radio_syn4a = r13, \
|
||||
.radio_syn58 = r14, \
|
||||
.radio_syn5a = r15, \
|
||||
.radio_syn6a = r16, \
|
||||
.radio_syn6d = r17, \
|
||||
.radio_syn6e = r18, \
|
||||
.radio_syn92 = r19, \
|
||||
.radio_syn98 = r20, \
|
||||
.radio_rxtx4a = r21, \
|
||||
.radio_rxtx58 = r22, \
|
||||
.radio_rxtx5a = r23, \
|
||||
.radio_rxtx6a = r24, \
|
||||
.radio_rxtx6d = r25, \
|
||||
.radio_rxtx6e = r26, \
|
||||
.radio_rxtx92 = r27, \
|
||||
.radio_rxtx98 = r28
|
||||
|
||||
#define PHYREGS(r0, r1, r2, r3, r4, r5) \
|
||||
.phy_regs.bw1 = r0, \
|
||||
.phy_regs.bw2 = r1, \
|
||||
.phy_regs.bw3 = r2, \
|
||||
.phy_regs.bw4 = r3, \
|
||||
.phy_regs.bw5 = r4, \
|
||||
.phy_regs.bw6 = r5
|
||||
|
||||
static const struct b43_phy_ht_channeltab_e_radio2059 b43_phy_ht_channeltab_radio2059[] = {
|
||||
{ .freq = 2412,
|
||||
RADIOREGS(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c,
|
||||
0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443),
|
||||
},
|
||||
{ .freq = 2417,
|
||||
RADIOREGS(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71,
|
||||
0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441),
|
||||
},
|
||||
{ .freq = 2422,
|
||||
RADIOREGS(0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76,
|
||||
0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f),
|
||||
},
|
||||
{ .freq = 2427,
|
||||
RADIOREGS(0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b,
|
||||
0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d),
|
||||
},
|
||||
{ .freq = 2432,
|
||||
RADIOREGS(0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80,
|
||||
0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a),
|
||||
},
|
||||
{ .freq = 2437,
|
||||
RADIOREGS(0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85,
|
||||
0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438),
|
||||
},
|
||||
{ .freq = 2442,
|
||||
RADIOREGS(0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a,
|
||||
0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436),
|
||||
},
|
||||
{ .freq = 2447,
|
||||
RADIOREGS(0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f,
|
||||
0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434),
|
||||
},
|
||||
{ .freq = 2452,
|
||||
RADIOREGS(0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94,
|
||||
0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431),
|
||||
},
|
||||
{ .freq = 2457,
|
||||
RADIOREGS(0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99,
|
||||
0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f),
|
||||
},
|
||||
{ .freq = 2462,
|
||||
RADIOREGS(0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e,
|
||||
0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d),
|
||||
},
|
||||
{ .freq = 2467,
|
||||
RADIOREGS(0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3,
|
||||
0x09, 0x0f, 0x05, 0x00, 0x05, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b),
|
||||
},
|
||||
{ .freq = 2472,
|
||||
RADIOREGS(0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8,
|
||||
0x09, 0x0f, 0x05, 0x00, 0x05, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
|
||||
0x00, 0x00, 0x00, 0xf0, 0x00),
|
||||
PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429),
|
||||
},
|
||||
};
|
||||
|
||||
const struct b43_phy_ht_channeltab_e_radio2059
|
||||
*b43_phy_ht_get_channeltab_e_r2059(struct b43_wldev *dev, u16 freq)
|
||||
{
|
||||
|
||||
@@ -5,6 +5,11 @@
|
||||
|
||||
#include "phy_ht.h"
|
||||
|
||||
#define R2059_SYN 0x000
|
||||
#define R2059_TXRX0 0x400
|
||||
#define R2059_RXRX1 0x800
|
||||
#define R2059_ALL 0xC00
|
||||
|
||||
/* Values for various registers uploaded on channel switching */
|
||||
struct b43_phy_ht_channeltab_e_radio2059 {
|
||||
/* The channel frequency in MHz */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,22 @@
|
||||
#ifndef B43_TABLES_PHY_HT_H_
|
||||
#define B43_TABLES_PHY_HT_H_
|
||||
|
||||
/* The HT-PHY tables. */
|
||||
#define B43_HTTAB_TYPEMASK 0xF0000000
|
||||
#define B43_HTTAB_8BIT 0x10000000
|
||||
#define B43_HTTAB_16BIT 0x20000000
|
||||
#define B43_HTTAB_32BIT 0x30000000
|
||||
#define B43_HTTAB8(table, offset) (((table) << 10) | (offset) | B43_HTTAB_8BIT)
|
||||
#define B43_HTTAB16(table, offset) (((table) << 10) | (offset) | B43_HTTAB_16BIT)
|
||||
#define B43_HTTAB32(table, offset) (((table) << 10) | (offset) | B43_HTTAB_32BIT)
|
||||
|
||||
u32 b43_httab_read(struct b43_wldev *dev, u32 offset);
|
||||
void b43_httab_read_bulk(struct b43_wldev *dev, u32 offset,
|
||||
unsigned int nr_elements, void *_data);
|
||||
void b43_httab_write(struct b43_wldev *dev, u32 offset, u32 value);
|
||||
void b43_httab_write_bulk(struct b43_wldev *dev, u32 offset,
|
||||
unsigned int nr_elements, const void *_data);
|
||||
|
||||
void b43_phy_ht_tables_init(struct b43_wldev *dev);
|
||||
|
||||
#endif /* B43_TABLES_PHY_HT_H_ */
|
||||
@@ -484,7 +484,7 @@ static inline u16 iwl_legacy_pcie_link_ctl(struct iwl_priv *priv)
|
||||
{
|
||||
int pos;
|
||||
u16 pci_lnk_ctl;
|
||||
pos = pci_find_capability(priv->pci_dev, PCI_CAP_ID_EXP);
|
||||
pos = pci_pcie_cap(priv->pci_dev);
|
||||
pci_read_config_word(priv->pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
|
||||
return pci_lnk_ctl;
|
||||
}
|
||||
|
||||
@@ -34,6 +34,7 @@
|
||||
#include <net/mac80211.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <asm/unaligned.h>
|
||||
#include <linux/stringify.h>
|
||||
|
||||
#include "iwl-eeprom.h"
|
||||
#include "iwl-dev.h"
|
||||
@@ -53,10 +54,10 @@
|
||||
#define IWL100_UCODE_API_MIN 5
|
||||
|
||||
#define IWL1000_FW_PRE "iwlwifi-1000-"
|
||||
#define IWL1000_MODULE_FIRMWARE(api) IWL1000_FW_PRE #api ".ucode"
|
||||
#define IWL1000_MODULE_FIRMWARE(api) IWL1000_FW_PRE __stringify(api) ".ucode"
|
||||
|
||||
#define IWL100_FW_PRE "iwlwifi-100-"
|
||||
#define IWL100_MODULE_FIRMWARE(api) IWL100_FW_PRE #api ".ucode"
|
||||
#define IWL100_MODULE_FIRMWARE(api) IWL100_FW_PRE __stringify(api) ".ucode"
|
||||
|
||||
|
||||
/*
|
||||
|
||||
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Reference in New Issue
Block a user