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ath5k: Port to new bitrate/channel API

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Author: Nick Kossifidis <mickflemm@gmail.com>

Tested on 5211, 5213+5112, 5213A+2112A and it wors fine.

Also i figured out a way to process rate vallue found
on status descriptors, it's still buggy but we are getting
closer (i think it improved stability a little).

Changes to hw.c, initvals.c, phy.c
Changes-licensed-under: ISC

Changes to ath5k.h, base.c, base.h
Changes-licensed-under: 3-Clause-BSD

Acked-by: Jiri Slaby <jirislaby@gmail.com>
Signed-off-by: Nick Kossifidis <mickflemm@gmail.com>
Signed-off-by: Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Luis R. Rodriguez
2008-02-03 21:51:04 -05:00
committed by John W. Linville
parent 406f2388cc
commit d8ee398d18
8 changed files with 330 additions and 373 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/net/wireless/Kconfig
-1
View File
@@ -735,7 +735,6 @@ config P54_PCI
config ATH5K
tristate "Atheros 5xxx wireless cards support"
depends on PCI && MAC80211 && WLAN_80211 && EXPERIMENTAL
depends on BROKEN
---help---
This module adds support for wireless adapters based on
Atheros 5xxx chipset.
drivers/net/wireless/ath5k/Makefile
+1 -1
View File
@@ -1,2 +1,2 @@
ath5k-objs = base.o hw.o regdom.o initvals.o phy.o debug.o
ath5k-objs = base.o hw.o initvals.o phy.o debug.o
obj-$(CONFIG_ATH5K) += ath5k.o
drivers/net/wireless/ath5k/ath5k.h
+46 -54
View File
@@ -30,7 +30,6 @@
#include <net/mac80211.h>
#include "hw.h"
#include "regdom.h"
/* PCI IDs */
#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */
@@ -251,18 +250,20 @@ struct ath5k_srev_name {
*/
#define MODULATION_TURBO 0x00000080
enum ath5k_vendor_mode {
MODE_ATHEROS_TURBO = NUM_IEEE80211_MODES+1,
MODE_ATHEROS_TURBOG
enum ath5k_driver_mode {
AR5K_MODE_11A = 0,
AR5K_MODE_11A_TURBO = 1,
AR5K_MODE_11B = 2,
AR5K_MODE_11G = 3,
AR5K_MODE_11G_TURBO = 4,
AR5K_MODE_XR = 0,
AR5K_MODE_MAX = 5
};
/* Number of supported mac80211 enum ieee80211_phymode modes by this driver */
#define NUM_DRIVER_MODES 3
/* adding this flag to rate_code enables short preamble, see ar5212_reg.h */
#define AR5K_SET_SHORT_PREAMBLE 0x04
#define HAS_SHPREAMBLE(_ix) (rt->rates[_ix].modulation == IEEE80211_RATE_CCK_2)
#define HAS_SHPREAMBLE(_ix) (rt->rates[_ix].modulation == IEEE80211_RATE_SHORT_PREAMBLE)
#define SHPREAMBLE_FLAG(_ix) (HAS_SHPREAMBLE(_ix) ? AR5K_SET_SHORT_PREAMBLE : 0)
/****************\
@@ -560,8 +561,8 @@ struct ath5k_desc {
* Used internaly in OpenHAL (ar5211.c/ar5212.c
* for reset_tx_queue). Also see struct struct ieee80211_channel.
*/
#define IS_CHAN_XR(_c) ((_c.val & CHANNEL_XR) != 0)
#define IS_CHAN_B(_c) ((_c.val & CHANNEL_B) != 0)
#define IS_CHAN_XR(_c) ((_c.hw_value & CHANNEL_XR) != 0)
#define IS_CHAN_B(_c) ((_c.hw_value & CHANNEL_B) != 0)
/*
* The following structure will be used to map 2GHz channels to
@@ -584,7 +585,7 @@ struct ath5k_athchan_2ghz {
/**
* struct ath5k_rate - rate structure
* @valid: is this a valid rate for the current mode
* @valid: is this a valid rate for rate control (remove)
* @modulation: respective mac80211 modulation
* @rate_kbps: rate in kbit/s
* @rate_code: hardware rate value, used in &struct ath5k_desc, on RX on
@@ -643,47 +644,48 @@ struct ath5k_rate_table {
/*
* Rate tables...
* TODO: CLEAN THIS !!!
*/
#define AR5K_RATES_11A { 8, { \
255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \
7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \
255, 255, 255, 255, 255, 255, 255, 255 }, { \
{ 1, IEEE80211_RATE_OFDM, 6000, 11, 140, 0 }, \
{ 1, IEEE80211_RATE_OFDM, 9000, 15, 18, 0 }, \
{ 1, IEEE80211_RATE_OFDM, 12000, 10, 152, 2 }, \
{ 1, IEEE80211_RATE_OFDM, 18000, 14, 36, 2 }, \
{ 1, IEEE80211_RATE_OFDM, 24000, 9, 176, 4 }, \
{ 1, IEEE80211_RATE_OFDM, 36000, 13, 72, 4 }, \
{ 1, IEEE80211_RATE_OFDM, 48000, 8, 96, 4 }, \
{ 1, IEEE80211_RATE_OFDM, 54000, 12, 108, 4 } } \
{ 1, 0, 6000, 11, 140, 0 }, \
{ 1, 0, 9000, 15, 18, 0 }, \
{ 1, 0, 12000, 10, 152, 2 }, \
{ 1, 0, 18000, 14, 36, 2 }, \
{ 1, 0, 24000, 9, 176, 4 }, \
{ 1, 0, 36000, 13, 72, 4 }, \
{ 1, 0, 48000, 8, 96, 4 }, \
{ 1, 0, 54000, 12, 108, 4 } } \
}
#define AR5K_RATES_11B { 4, { \
255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \
255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \
3, 2, 1, 0, 255, 255, 255, 255 }, { \
{ 1, IEEE80211_RATE_CCK, 1000, 27, 130, 0 }, \
{ 1, IEEE80211_RATE_CCK_2, 2000, 26, 132, 1 }, \
{ 1, IEEE80211_RATE_CCK_2, 5500, 25, 139, 1 }, \
{ 1, IEEE80211_RATE_CCK_2, 11000, 24, 150, 1 } } \
{ 1, 0, 1000, 27, 130, 0 }, \
{ 1, IEEE80211_RATE_SHORT_PREAMBLE, 2000, 26, 132, 1 }, \
{ 1, IEEE80211_RATE_SHORT_PREAMBLE, 5500, 25, 139, 1 }, \
{ 1, IEEE80211_RATE_SHORT_PREAMBLE, 11000, 24, 150, 1 } } \
}
#define AR5K_RATES_11G { 12, { \
255, 255, 255, 255, 255, 255, 255, 255, 10, 8, 6, 4, \
11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \
3, 2, 1, 0, 255, 255, 255, 255 }, { \
{ 1, IEEE80211_RATE_CCK, 1000, 27, 2, 0 }, \
{ 1, IEEE80211_RATE_CCK_2, 2000, 26, 4, 1 }, \
{ 1, IEEE80211_RATE_CCK_2, 5500, 25, 11, 1 }, \
{ 1, IEEE80211_RATE_CCK_2, 11000, 24, 22, 1 }, \
{ 0, IEEE80211_RATE_OFDM, 6000, 11, 12, 4 }, \
{ 0, IEEE80211_RATE_OFDM, 9000, 15, 18, 4 }, \
{ 1, IEEE80211_RATE_OFDM, 12000, 10, 24, 6 }, \
{ 1, IEEE80211_RATE_OFDM, 18000, 14, 36, 6 }, \
{ 1, IEEE80211_RATE_OFDM, 24000, 9, 48, 8 }, \
{ 1, IEEE80211_RATE_OFDM, 36000, 13, 72, 8 }, \
{ 1, IEEE80211_RATE_OFDM, 48000, 8, 96, 8 }, \
{ 1, IEEE80211_RATE_OFDM, 54000, 12, 108, 8 } } \
{ 1, 0, 1000, 27, 2, 0 }, \
{ 1, IEEE80211_RATE_SHORT_PREAMBLE, 2000, 26, 4, 1 }, \
{ 1, IEEE80211_RATE_SHORT_PREAMBLE, 5500, 25, 11, 1 }, \
{ 1, IEEE80211_RATE_SHORT_PREAMBLE, 11000, 24, 22, 1 }, \
{ 0, 0, 6000, 11, 12, 4 }, \
{ 0, 0, 9000, 15, 18, 4 }, \
{ 1, 0, 12000, 10, 24, 6 }, \
{ 1, 0, 18000, 14, 36, 6 }, \
{ 1, 0, 24000, 9, 48, 8 }, \
{ 1, 0, 36000, 13, 72, 8 }, \
{ 1, 0, 48000, 8, 96, 8 }, \
{ 1, 0, 54000, 12, 108, 8 } } \
}
#define AR5K_RATES_TURBO { 8, { \
@@ -708,14 +710,14 @@ struct ath5k_rate_table {
{ 1, MODULATION_XR, 1000, 2, 139, 1 }, \
{ 1, MODULATION_XR, 2000, 6, 150, 2 }, \
{ 1, MODULATION_XR, 3000, 1, 150, 3 }, \
{ 1, IEEE80211_RATE_OFDM, 6000, 11, 140, 4 }, \
{ 1, IEEE80211_RATE_OFDM, 9000, 15, 18, 4 }, \
{ 1, IEEE80211_RATE_OFDM, 12000, 10, 152, 6 }, \
{ 1, IEEE80211_RATE_OFDM, 18000, 14, 36, 6 }, \
{ 1, IEEE80211_RATE_OFDM, 24000, 9, 176, 8 }, \
{ 1, IEEE80211_RATE_OFDM, 36000, 13, 72, 8 }, \
{ 1, IEEE80211_RATE_OFDM, 48000, 8, 96, 8 }, \
{ 1, IEEE80211_RATE_OFDM, 54000, 12, 108, 8 } } \
{ 1, 0, 6000, 11, 140, 4 }, \
{ 1, 0, 9000, 15, 18, 4 }, \
{ 1, 0, 12000, 10, 152, 6 }, \
{ 1, 0, 18000, 14, 36, 6 }, \
{ 1, 0, 24000, 9, 176, 8 }, \
{ 1, 0, 36000, 13, 72, 8 }, \
{ 1, 0, 48000, 8, 96, 8 }, \
{ 1, 0, 54000, 12, 108, 8 } } \
}
/*
@@ -895,7 +897,7 @@ struct ath5k_capabilities {
* Supported PHY modes
* (ie. CHANNEL_A, CHANNEL_B, ...)
*/
DECLARE_BITMAP(cap_mode, NUM_DRIVER_MODES);
DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);
/*
* Frequency range (without regulation restrictions)
@@ -907,14 +909,6 @@ struct ath5k_capabilities {
u16 range_5ghz_max;
} cap_range;
/*
* Active regulation domain settings
*/
struct {
enum ath5k_regdom reg_current;
enum ath5k_regdom reg_hw;
} cap_regdomain;
/*
* Values stored in the EEPROM (some of them...)
*/
@@ -1129,8 +1123,6 @@ extern int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level);
/* Regulatory Domain/Channels Setup */
extern u16 ath5k_get_regdomain(struct ath5k_hw *ah);
/* Misc functions */
extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result);
drivers/net/wireless/ath5k/base.c
+192 -156
View File
File diff suppressed because it is too large Load Diff
drivers/net/wireless/ath5k/base.h
+11 -3
View File
@@ -83,7 +83,7 @@ struct ath5k_txq {
#if CHAN_DEBUG
#define ATH_CHAN_MAX (26+26+26+200+200)
#else
#define ATH_CHAN_MAX (14+14+14+252+20) /* XXX what's the max? */
#define ATH_CHAN_MAX (14+14+14+252+20)
#endif
/* Software Carrier, keeps track of the driver state
@@ -95,12 +95,19 @@ struct ath5k_softc {
struct ieee80211_tx_queue_stats tx_stats;
struct ieee80211_low_level_stats ll_stats;
struct ieee80211_hw *hw; /* IEEE 802.11 common */
struct ieee80211_hw_mode modes[NUM_DRIVER_MODES];
struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
struct ieee80211_channel channels[ATH_CHAN_MAX];
struct ieee80211_rate rates[AR5K_MAX_RATES * NUM_DRIVER_MODES];
struct ieee80211_rate rates[AR5K_MAX_RATES * IEEE80211_NUM_BANDS];
enum ieee80211_if_types opmode;
struct ath5k_hw *ah; /* Atheros HW */
struct ieee80211_supported_band *curband;
u8 a_rates;
u8 b_rates;
u8 g_rates;
u8 xr_rates;
#if ATH5K_DEBUG
struct ath5k_dbg_info debug; /* debug info */
#endif
@@ -169,6 +176,7 @@ struct ath5k_softc {
unsigned int nexttbtt; /* next beacon time in TU */
struct timer_list calib_tim; /* calibration timer */
int power_level; /* Requested tx power in dbm */
};
#define ath5k_hw_hasbssidmask(_ah) \
drivers/net/wireless/ath5k/hw.c
+46 -124
View File
@@ -140,9 +140,6 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
* HW information
*/
/* Get reg domain from eeprom */
ath5k_get_regdomain(ah);
ah->ah_op_mode = IEEE80211_IF_TYPE_STA;
ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
ah->ah_turbo = false;
@@ -405,15 +402,15 @@ const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath5k_hw *ah,
/* Get rate tables */
switch (mode) {
case MODE_IEEE80211A:
case AR5K_MODE_11A:
return &ath5k_rt_11a;
case MODE_ATHEROS_TURBO:
case AR5K_MODE_11A_TURBO:
return &ath5k_rt_turbo;
case MODE_IEEE80211B:
case AR5K_MODE_11B:
return &ath5k_rt_11b;
case MODE_IEEE80211G:
case AR5K_MODE_11G:
return &ath5k_rt_11g;
case MODE_ATHEROS_TURBOG:
case AR5K_MODE_11G_TURBO:
return &ath5k_rt_xr;
}
@@ -457,15 +454,15 @@ static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
ds_coef_exp, ds_coef_man, clock;
if (!(ah->ah_version == AR5K_AR5212) ||
!(channel->val & CHANNEL_OFDM))
!(channel->hw_value & CHANNEL_OFDM))
BUG();
/* Seems there are two PLLs, one for baseband sampling and one
* for tuning. Tuning basebands are 40 MHz or 80MHz when in
* turbo. */
clock = channel->val & CHANNEL_TURBO ? 80 : 40;
clock = channel->hw_value & CHANNEL_TURBO ? 80 : 40;
coef_scaled = ((5 * (clock << 24)) / 2) /
channel->freq;
channel->center_freq;
for (coef_exp = 31; coef_exp > 0; coef_exp--)
if ((coef_scaled >> coef_exp) & 0x1)
@@ -492,8 +489,7 @@ static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
* ath5k_hw_write_rate_duration - set rate duration during hw resets
*
* @ah: the &struct ath5k_hw
* @driver_mode: one of enum ieee80211_phymode or our one of our own
* vendor modes
* @mode: one of enum ath5k_driver_mode
*
* Write the rate duration table for the current mode upon hw reset. This
* is a helper for ath5k_hw_reset(). It seems all this is doing is setting
@@ -504,19 +500,20 @@ static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
*
*/
static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah,
unsigned int driver_mode)
unsigned int mode)
{
struct ath5k_softc *sc = ah->ah_sc;
const struct ath5k_rate_table *rt;
struct ieee80211_rate srate = {};
unsigned int i;
/* Get rate table for the current operating mode */
rt = ath5k_hw_get_rate_table(ah,
driver_mode);
rt = ath5k_hw_get_rate_table(ah, mode);
/* Write rate duration table */
for (i = 0; i < rt->rate_count; i++) {
const struct ath5k_rate *rate, *control_rate;
u32 reg;
u16 tx_time;
@@ -526,6 +523,8 @@ static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah,
/* Set ACK timeout */
reg = AR5K_RATE_DUR(rate->rate_code);
srate.bitrate = control_rate->rate_kbps/100;
/* An ACK frame consists of 10 bytes. If you add the FCS,
* which ieee80211_generic_frame_duration() adds,
* its 14 bytes. Note we use the control rate and not the
@@ -533,7 +532,7 @@ static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah,
* ieee80211_duration() for a brief description of
* what rate we should choose to TX ACKs. */
tx_time = ieee80211_generic_frame_duration(sc->hw,
sc->vif, 10, control_rate->rate_kbps/100);
sc->vif, 10, &srate);
ath5k_hw_reg_write(ah, tx_time, reg);
@@ -567,7 +566,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
{
struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
u32 data, s_seq, s_ant, s_led[3];
unsigned int i, mode, freq, ee_mode, ant[2], driver_mode = -1;
unsigned int i, mode, freq, ee_mode, ant[2];
int ret;
ATH5K_TRACE(ah->ah_sc);
@@ -602,7 +601,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
/*Wakeup the device*/
ret = ath5k_hw_nic_wakeup(ah, channel->val, false);
ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false);
if (ret)
return ret;
@@ -624,37 +623,32 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
return -EINVAL;
}
switch (channel->val & CHANNEL_MODES) {
switch (channel->hw_value & CHANNEL_MODES) {
case CHANNEL_A:
mode = AR5K_INI_VAL_11A;
mode = AR5K_MODE_11A;
freq = AR5K_INI_RFGAIN_5GHZ;
ee_mode = AR5K_EEPROM_MODE_11A;
driver_mode = MODE_IEEE80211A;
break;
case CHANNEL_G:
mode = AR5K_INI_VAL_11G;
mode = AR5K_MODE_11G;
freq = AR5K_INI_RFGAIN_2GHZ;
ee_mode = AR5K_EEPROM_MODE_11G;
driver_mode = MODE_IEEE80211G;
break;
case CHANNEL_B:
mode = AR5K_INI_VAL_11B;
mode = AR5K_MODE_11B;
freq = AR5K_INI_RFGAIN_2GHZ;
ee_mode = AR5K_EEPROM_MODE_11B;
driver_mode = MODE_IEEE80211B;
break;
case CHANNEL_T:
mode = AR5K_INI_VAL_11A_TURBO;
mode = AR5K_MODE_11A_TURBO;
freq = AR5K_INI_RFGAIN_5GHZ;
ee_mode = AR5K_EEPROM_MODE_11A;
driver_mode = MODE_ATHEROS_TURBO;
break;
/*Is this ok on 5211 too ?*/
case CHANNEL_TG:
mode = AR5K_INI_VAL_11G_TURBO;
mode = AR5K_MODE_11G_TURBO;
freq = AR5K_INI_RFGAIN_2GHZ;
ee_mode = AR5K_EEPROM_MODE_11G;
driver_mode = MODE_ATHEROS_TURBOG;
break;
case CHANNEL_XR:
if (ah->ah_version == AR5K_AR5211) {
@@ -662,14 +656,13 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
"XR mode not available on 5211");
return -EINVAL;
}
mode = AR5K_INI_VAL_XR;
mode = AR5K_MODE_XR;
freq = AR5K_INI_RFGAIN_5GHZ;
ee_mode = AR5K_EEPROM_MODE_11A;
driver_mode = MODE_IEEE80211A;
break;
default:
ATH5K_ERR(ah->ah_sc,
"invalid channel: %d\n", channel->freq);
"invalid channel: %d\n", channel->center_freq);
return -EINVAL;
}
@@ -702,7 +695,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
if (ah->ah_version > AR5K_AR5211){ /* found on 5213+ */
ath5k_hw_reg_write(ah, 0x0002a002, AR5K_PHY(11));
if (channel->val == CHANNEL_G)
if (channel->hw_value == CHANNEL_G)
ath5k_hw_reg_write(ah, 0x00f80d80, AR5K_PHY(83)); /* 0x00fc0ec0 */
else
ath5k_hw_reg_write(ah, 0x00000000, AR5K_PHY(83));
@@ -720,7 +713,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
AR5K_SREV_RAD_5112A) {
ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
AR5K_PHY_CCKTXCTL);
if (channel->val & CHANNEL_5GHZ)
if (channel->hw_value & CHANNEL_5GHZ)
data = 0xffb81020;
else
data = 0xffb80d20;
@@ -740,7 +733,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
* mac80211 are integrated */
if (ah->ah_version == AR5K_AR5212 &&
ah->ah_sc->vif != NULL)
ath5k_hw_write_rate_duration(ah, driver_mode);
ath5k_hw_write_rate_duration(ah, mode);
/*
* Write RF registers
@@ -756,7 +749,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
/* Write OFDM timings on 5212*/
if (ah->ah_version == AR5K_AR5212 &&
channel->val & CHANNEL_OFDM) {
channel->hw_value & CHANNEL_OFDM) {
ret = ath5k_hw_write_ofdm_timings(ah, channel);
if (ret)
return ret;
@@ -765,7 +758,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
/*Enable/disable 802.11b mode on 5111
(enable 2111 frequency converter + CCK)*/
if (ah->ah_radio == AR5K_RF5111) {
if (driver_mode == MODE_IEEE80211B)
if (mode == AR5K_MODE_11B)
AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
AR5K_TXCFG_B_MODE);
else
@@ -903,7 +896,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
if (ah->ah_version != AR5K_AR5210) {
data = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
AR5K_PHY_RX_DELAY_M;
data = (channel->val & CHANNEL_CCK) ?
data = (channel->hw_value & CHANNEL_CCK) ?
((data << 2) / 22) : (data / 10);
udelay(100 + data);
@@ -920,11 +913,11 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
AR5K_PHY_AGCCTL_CAL, 0, false)) {
ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
channel->freq);
channel->center_freq);
return -EAGAIN;
}
ret = ath5k_hw_noise_floor_calibration(ah, channel->freq);
ret = ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
if (ret)
return ret;
@@ -932,7 +925,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
/* A and G modes can use QAM modulation which requires enabling
* I and Q calibration. Don't bother in B mode. */
if (!(driver_mode == MODE_IEEE80211B)) {
if (!(mode == AR5K_MODE_11B)) {
ah->ah_calibration = true;
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
@@ -1590,9 +1583,10 @@ static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
/*
* Write to eeprom - currently disabled, use at your own risk
*/
#if 0
static int ath5k_hw_eeprom_write(struct ath5k_hw *ah, u32 offset, u16 data)
{
#if 0
u32 status, timeout;
ATH5K_TRACE(ah->ah_sc);
@@ -1634,10 +1628,11 @@ static int ath5k_hw_eeprom_write(struct ath5k_hw *ah, u32 offset, u16 data)
}
udelay(15);
}
#endif
ATH5K_ERR(ah->ah_sc, "EEPROM Write is disabled!");
return -EIO;
}
#endif
/*
* Translate binary channel representation in EEPROM to frequency
@@ -2042,50 +2037,6 @@ static int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
return 0;
}
/*
* Read/Write regulatory domain
*/
static bool ath5k_eeprom_regulation_domain(struct ath5k_hw *ah, bool write,
enum ath5k_regdom *regdomain)
{
u16 ee_regdomain;
/* Read current value */
if (write != true) {
ee_regdomain = ah->ah_capabilities.cap_eeprom.ee_regdomain;
*regdomain = ath5k_regdom_to_ieee(ee_regdomain);
return true;
}
ee_regdomain = ath5k_regdom_from_ieee(*regdomain);
/* Try to write a new value */
if (ah->ah_capabilities.cap_eeprom.ee_protect &
AR5K_EEPROM_PROTECT_WR_128_191)
return false;
if (ath5k_hw_eeprom_write(ah, AR5K_EEPROM_REG_DOMAIN, ee_regdomain)!=0)
return false;
ah->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain;
return true;
}
/*
* Use the above to write a new regulatory domain
*/
int ath5k_hw_set_regdomain(struct ath5k_hw *ah, u16 regdomain)
{
enum ath5k_regdom ieee_regdomain;
ieee_regdomain = ath5k_regdom_to_ieee(regdomain);
if (ath5k_eeprom_regulation_domain(ah, true, &ieee_regdomain) == true)
return 0;
return -EIO;
}
/*
* Fill the capabilities struct
*/
@@ -2108,8 +2059,8 @@ static int ath5k_hw_get_capabilities(struct ath5k_hw *ah)
ah->ah_capabilities.cap_range.range_2ghz_max = 0;
/* Set supported modes */
__set_bit(MODE_IEEE80211A, ah->ah_capabilities.cap_mode);
__set_bit(MODE_ATHEROS_TURBO, ah->ah_capabilities.cap_mode);
__set_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode);
__set_bit(AR5K_MODE_11A_TURBO, ah->ah_capabilities.cap_mode);
} else {
/*
* XXX The tranceiver supports frequencies from 4920 to 6100GHz
@@ -2131,12 +2082,12 @@ static int ath5k_hw_get_capabilities(struct ath5k_hw *ah)
ah->ah_capabilities.cap_range.range_5ghz_max = 6100;
/* Set supported modes */
__set_bit(MODE_IEEE80211A,
__set_bit(AR5K_MODE_11A,
ah->ah_capabilities.cap_mode);
__set_bit(MODE_ATHEROS_TURBO,
__set_bit(AR5K_MODE_11A_TURBO,
ah->ah_capabilities.cap_mode);
if (ah->ah_version == AR5K_AR5212)
__set_bit(MODE_ATHEROS_TURBOG,
__set_bit(AR5K_MODE_11G_TURBO,
ah->ah_capabilities.cap_mode);
}
@@ -2148,11 +2099,11 @@ static int ath5k_hw_get_capabilities(struct ath5k_hw *ah)
ah->ah_capabilities.cap_range.range_2ghz_max = 2732;
if (AR5K_EEPROM_HDR_11B(ee_header))
__set_bit(MODE_IEEE80211B,
__set_bit(AR5K_MODE_11B,
ah->ah_capabilities.cap_mode);
if (AR5K_EEPROM_HDR_11G(ee_header))
__set_bit(MODE_IEEE80211G,
__set_bit(AR5K_MODE_11G,
ah->ah_capabilities.cap_mode);
}
}
@@ -4248,35 +4199,6 @@ void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
}
/*********************************\
Regulatory Domain/Channels Setup
\*********************************/
u16 ath5k_get_regdomain(struct ath5k_hw *ah)
{
u16 regdomain;
enum ath5k_regdom ieee_regdomain;
#ifdef COUNTRYCODE
u16 code;
#endif
ath5k_eeprom_regulation_domain(ah, false, &ieee_regdomain);
ah->ah_capabilities.cap_regdomain.reg_hw = ieee_regdomain;
#ifdef COUNTRYCODE
/*
* Get the regulation domain by country code. This will ignore
* the settings found in the EEPROM.
*/
code = ieee80211_name2countrycode(COUNTRYCODE);
ieee_regdomain = ieee80211_countrycode2regdomain(code);
#endif
regdomain = ath5k_regdom_from_ieee(ieee_regdomain);
ah->ah_capabilities.cap_regdomain.reg_current = regdomain;
return regdomain;
}
/****************\
drivers/net/wireless/ath5k/initvals.c
+1 -1
View File
@@ -1317,7 +1317,7 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
/* For AR5211 */
} else if (ah->ah_version == AR5K_AR5211) {
if(mode > 2){ /* AR5K_INI_VAL_11B */
if(mode > 2){ /* AR5K_MODE_11B */
ATH5K_ERR(ah->ah_sc,"unsupported channel mode: %d\n", mode);
return -EINVAL;
}
drivers/net/wireless/ath5k/phy.c
+33 -33
View File
@@ -1018,7 +1018,7 @@ static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah,
int obdb = -1, bank = -1;
u32 ee_mode;
AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX);
AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
rf = ah->ah_rf_banks;
@@ -1038,8 +1038,8 @@ static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah,
}
/* Modify bank 0 */
if (channel->val & CHANNEL_2GHZ) {
if (channel->val & CHANNEL_CCK)
if (channel->hw_value & CHANNEL_2GHZ) {
if (channel->hw_value & CHANNEL_CCK)
ee_mode = AR5K_EEPROM_MODE_11B;
else
ee_mode = AR5K_EEPROM_MODE_11G;
@@ -1058,10 +1058,10 @@ static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah,
} else {
/* For 11a, Turbo and XR */
ee_mode = AR5K_EEPROM_MODE_11A;
obdb = channel->freq >= 5725 ? 3 :
(channel->freq >= 5500 ? 2 :
(channel->freq >= 5260 ? 1 :
(channel->freq > 4000 ? 0 : -1)));
obdb = channel->center_freq >= 5725 ? 3 :
(channel->center_freq >= 5500 ? 2 :
(channel->center_freq >= 5260 ? 1 :
(channel->center_freq > 4000 ? 0 : -1)));
if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
ee->ee_pwd_84, 1, 51, 3, true))
@@ -1119,12 +1119,12 @@ static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah,
int obdb = -1, bank = -1;
u32 ee_mode;
AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX);
AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
rf = ah->ah_rf_banks;
if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_2112A
&& !test_bit(MODE_IEEE80211A, ah->ah_capabilities.cap_mode)){
&& !test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)){
rf_ini = rfregs_2112a;
rf_size = ARRAY_SIZE(rfregs_5112a);
if (mode < 2) {
@@ -1156,8 +1156,8 @@ static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah,
}
/* Modify bank 6 */
if (channel->val & CHANNEL_2GHZ) {
if (channel->val & CHANNEL_OFDM)
if (channel->hw_value & CHANNEL_2GHZ) {
if (channel->hw_value & CHANNEL_OFDM)
ee_mode = AR5K_EEPROM_MODE_11G;
else
ee_mode = AR5K_EEPROM_MODE_11B;
@@ -1173,10 +1173,10 @@ static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah,
} else {
/* For 11a, Turbo and XR */
ee_mode = AR5K_EEPROM_MODE_11A;
obdb = channel->freq >= 5725 ? 3 :
(channel->freq >= 5500 ? 2 :
(channel->freq >= 5260 ? 1 :
(channel->freq > 4000 ? 0 : -1)));
obdb = channel->center_freq >= 5725 ? 3 :
(channel->center_freq >= 5500 ? 2 :
(channel->center_freq >= 5260 ? 1 :
(channel->center_freq > 4000 ? 0 : -1)));
if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
ee->ee_ob[ee_mode][obdb], 3, 279, 0, true))
@@ -1219,7 +1219,7 @@ static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
unsigned int rf_size, i;
int bank = -1;
AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX);
AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
rf = ah->ah_rf_banks;
@@ -1445,7 +1445,7 @@ static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
* newer chipsets like the AR5212A who have a completely
* different RF/PHY part.
*/
athchan = (ath5k_hw_bitswap((channel->chan - 24) / 2, 5) << 1) |
athchan = (ath5k_hw_bitswap((ieee80211_frequency_to_channel(channel->center_freq) - 24) / 2, 5) << 1) |
(1 << 6) | 0x1;
return athchan;
@@ -1506,7 +1506,7 @@ static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
struct ieee80211_channel *channel)
{
struct ath5k_athchan_2ghz ath5k_channel_2ghz;
unsigned int ath5k_channel = channel->chan;
unsigned int ath5k_channel = ieee80211_frequency_to_channel(channel->center_freq);
u32 data0, data1, clock;
int ret;
@@ -1515,9 +1515,9 @@ static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
*/
data0 = data1 = 0;
if (channel->val & CHANNEL_2GHZ) {
if (channel->hw_value & CHANNEL_2GHZ) {
/* Map 2GHz channel to 5GHz Atheros channel ID */
ret = ath5k_hw_rf5111_chan2athchan(channel->chan,
ret = ath5k_hw_rf5111_chan2athchan(ieee80211_frequency_to_channel(channel->center_freq),
&ath5k_channel_2ghz);
if (ret)
return ret;
@@ -1555,7 +1555,7 @@ static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
u16 c;
data = data0 = data1 = data2 = 0;
c = channel->freq;
c = channel->center_freq;
/*
* Set the channel on the RF5112 or newer
@@ -1604,13 +1604,13 @@ int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
* Check bounds supported by the PHY
* (don't care about regulation restrictions at this point)
*/
if ((channel->freq < ah->ah_capabilities.cap_range.range_2ghz_min ||
channel->freq > ah->ah_capabilities.cap_range.range_2ghz_max) &&
(channel->freq < ah->ah_capabilities.cap_range.range_5ghz_min ||
channel->freq > ah->ah_capabilities.cap_range.range_5ghz_max)) {
if ((channel->center_freq < ah->ah_capabilities.cap_range.range_2ghz_min ||
channel->center_freq > ah->ah_capabilities.cap_range.range_2ghz_max) &&
(channel->center_freq < ah->ah_capabilities.cap_range.range_5ghz_min ||
channel->center_freq > ah->ah_capabilities.cap_range.range_5ghz_max)) {
ATH5K_ERR(ah->ah_sc,
"channel out of supported range (%u MHz)\n",
channel->freq);
channel->center_freq);
return -EINVAL;
}
@@ -1632,9 +1632,9 @@ int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
if (ret)
return ret;
ah->ah_current_channel.freq = channel->freq;
ah->ah_current_channel.val = channel->val;
ah->ah_turbo = channel->val == CHANNEL_T ? true : false;
ah->ah_current_channel.center_freq = channel->center_freq;
ah->ah_current_channel.hw_value = channel->hw_value;
ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false;
return 0;
}
@@ -1797,11 +1797,11 @@ static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
if (ret) {
ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
channel->freq);
channel->center_freq);
return ret;
}
ret = ath5k_hw_noise_floor_calibration(ah, channel->freq);
ret = ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
if (ret)
return ret;
@@ -1848,10 +1848,10 @@ static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah,
((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S));
done:
ath5k_hw_noise_floor_calibration(ah, channel->freq);
ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
/* Request RF gain */
if (channel->val & CHANNEL_5GHZ) {
if (channel->hw_value & CHANNEL_5GHZ) {
ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_max,
AR5K_PHY_PAPD_PROBE_TXPOWER) |
AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);