apfs/linux-apfs
0
0
Fork 0
mirror of https://github.com/linux-apfs/linux-apfs.git synced 2026-05-01 15:00:59 -07:00
Code Issues Packages Projects Releases Wiki Activity

Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

Browse Source 
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (266 commits)
  sh: Tie sparseirq in to Kconfig.
  sh: Wire up sys_rt_tgsigqueueinfo.
  sh: Fix sys_pwritev() syscall table entry for sh32.
  sh: Fix sh4a llsc-based cmpxchg()
  sh: sh7724: Add JPU support
  sh: sh7724: INTC setting update
  sh: sh7722 clock framework rewrite
  sh: sh7366 clock framework rewrite
  sh: sh7343 clock framework rewrite
  sh: sh7724 clock framework rewrite V3
  sh: sh7723 clock framework rewrite V2
  sh: add enable()/disable()/set_rate() to div6 code
  sh: add AP325RXA mode pin configuration
  sh: add Migo-R mode pin configuration
  sh: sh7722 mode pin definitions
  sh: sh7724 mode pin comments
  sh: sh7723 mode pin V2
  sh: rework mode pin code
  sh: clock div6 helper code
  sh: clock div4 frequency table offset fix
  ...
This commit is contained in:
Linus Torvalds
2009-06-11 10:08:33 -07:00
parent 6cd8e300b4 54ff328b46
commit d3d07d941f
275 changed files with 18227 additions and 7296 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/sh/Kconfig
+85 -43
View File
@@ -15,6 +15,7 @@ config SUPERH
select HAVE_IOREMAP_PROT if MMU
select HAVE_ARCH_TRACEHOOK
select HAVE_DMA_API_DEBUG
select RTC_LIB
help
The SuperH is a RISC processor targeted for use in embedded systems
and consumer electronics; it was also used in the Sega Dreamcast
@@ -74,14 +75,18 @@ config GENERIC_IOMAP
bool
config GENERIC_TIME
def_bool n
def_bool y
config GENERIC_CLOCKEVENTS
def_bool n
def_bool y
config GENERIC_CLOCKEVENTS_BROADCAST
bool
config GENERIC_CMOS_UPDATE
def_bool y
depends on SH_SH03 || SH_DREAMCAST
config GENERIC_LOCKBREAK
def_bool y
depends on SMP && PREEMPT
@@ -112,6 +117,12 @@ config SYS_SUPPORTS_PCI
config SYS_SUPPORTS_CMT
bool
config SYS_SUPPORTS_MTU2
bool
config SYS_SUPPORTS_TMU
bool
config STACKTRACE_SUPPORT
def_bool y
@@ -157,13 +168,14 @@ config CPU_SH3
bool
select CPU_HAS_INTEVT
select CPU_HAS_SR_RB
select SYS_SUPPORTS_TMU
config CPU_SH4
bool
select CPU_HAS_INTEVT
select CPU_HAS_SR_RB
select CPU_HAS_PTEA if !CPU_SH4A || CPU_SHX2
select CPU_HAS_FPU if !CPU_SH4AL_DSP
select SYS_SUPPORTS_TMU
config CPU_SH4A
bool
@@ -177,6 +189,7 @@ config CPU_SH4AL_DSP
config CPU_SH5
bool
select CPU_HAS_FPU
select SYS_SUPPORTS_TMU
config CPU_SHX2
bool
@@ -210,27 +223,32 @@ config CPU_SUBTYPE_SH7201
bool "Support SH7201 processor"
select CPU_SH2A
select CPU_HAS_FPU
select SYS_SUPPORTS_MTU2
config CPU_SUBTYPE_SH7203
bool "Support SH7203 processor"
select CPU_SH2A
select CPU_HAS_FPU
select SYS_SUPPORTS_CMT
select SYS_SUPPORTS_MTU2
config CPU_SUBTYPE_SH7206
bool "Support SH7206 processor"
select CPU_SH2A
select SYS_SUPPORTS_CMT
select SYS_SUPPORTS_MTU2
config CPU_SUBTYPE_SH7263
bool "Support SH7263 processor"
select CPU_SH2A
select CPU_HAS_FPU
select SYS_SUPPORTS_CMT
select SYS_SUPPORTS_MTU2
config CPU_SUBTYPE_MXG
bool "Support MX-G processor"
select CPU_SH2A
select SYS_SUPPORTS_MTU2
help
Select MX-G if running on an R8A03022BG part.
@@ -283,6 +301,7 @@ config CPU_SUBTYPE_SH7720
bool "Support SH7720 processor"
select CPU_SH3
select CPU_HAS_DSP
select SYS_SUPPORTS_CMT
help
Select SH7720 if you have a SH3-DSP SH7720 CPU.
@@ -290,6 +309,7 @@ config CPU_SUBTYPE_SH7721
bool "Support SH7721 processor"
select CPU_SH3
select CPU_HAS_DSP
select SYS_SUPPORTS_CMT
help
Select SH7721 if you have a SH3-DSP SH7721 CPU.
@@ -347,6 +367,16 @@ config CPU_SUBTYPE_SH7723
help
Select SH7723 if you have an SH-MobileR2 CPU.
config CPU_SUBTYPE_SH7724
bool "Support SH7724 processor"
select CPU_SH4A
select CPU_SHX2
select ARCH_SHMOBILE
select ARCH_SPARSEMEM_ENABLE
select SYS_SUPPORTS_CMT
help
Select SH7724 if you have an SH-MobileR2R CPU.
config CPU_SUBTYPE_SH7763
bool "Support SH7763 processor"
select CPU_SH4A
@@ -442,48 +472,26 @@ source "arch/sh/boards/Kconfig"
menu "Timer and clock configuration"
config SH_TMU
bool "TMU timer support"
depends on CPU_SH3 || CPU_SH4
default y
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
help
This enables the use of the TMU as the system timer.
config SH_CMT
bool "CMT timer support"
depends on SYS_SUPPORTS_CMT && CPU_SH2
config SH_TIMER_TMU
bool "TMU timer driver"
depends on SYS_SUPPORTS_TMU
default y
help
This enables the use of the CMT as the system timer.
This enables the build of the TMU timer driver.
#
# Support for the new-style CMT driver. This will replace SH_CMT
# once its other dependencies are merged.
#
config SH_TIMER_CMT
bool "CMT clockevents driver"
depends on SYS_SUPPORTS_CMT && !SH_CMT
select GENERIC_CLOCKEVENTS
config SH_MTU2
bool "MTU2 timer support"
depends on CPU_SH2A
bool "CMT timer driver"
depends on SYS_SUPPORTS_CMT
default y
help
This enables the use of the MTU2 as the system timer.
This enables build of the CMT timer driver.
config SH_TIMER_IRQ
int
default "28" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 || \
CPU_SUBTYPE_SH7763
default "86" if CPU_SUBTYPE_SH7619
default "140" if CPU_SUBTYPE_SH7206
default "142" if CPU_SUBTYPE_SH7203 && SH_CMT
default "153" if CPU_SUBTYPE_SH7203 && SH_MTU2
default "238" if CPU_SUBTYPE_MXG
default "16"
config SH_TIMER_MTU2
bool "MTU2 timer driver"
depends on SYS_SUPPORTS_MTU2
default y
help
This enables build of the MTU2 timer driver.
config SH_PCLK_FREQ
int "Peripheral clock frequency (in Hz)"
@@ -494,7 +502,7 @@ config SH_PCLK_FREQ
CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7705 || \
CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206 || \
CPU_SUBTYPE_SH7263 || CPU_SUBTYPE_MXG || \
CPU_SUBTYPE_SH7786
CPU_SUBTYPE_SH7786 || CPU_SUBTYPE_SH7724
default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
default "66000000" if CPU_SUBTYPE_SH4_202
default "50000000"
@@ -503,6 +511,13 @@ config SH_PCLK_FREQ
This is necessary for determining the reference clock value on
platforms lacking an RTC.
config SH_CLK_CPG
def_bool y
config SH_CLK_CPG_LEGACY
depends on SH_CLK_CPG
def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE
config SH_CLK_MD
int "CPU Mode Pin Setting"
depends on CPU_SH2
@@ -663,27 +678,54 @@ config GUSA_RB
LLSC, this should be more efficient than the other alternative of
disabling interrupts around the atomic sequence.
config SPARSE_IRQ
bool "Support sparse irq numbering"
depends on EXPERIMENTAL
help
This enables support for sparse irqs. This is useful in general
as most CPUs have a fairly sparse array of IRQ vectors, which
the irq_desc then maps directly on to. Systems with a high
number of off-chip IRQs will want to treat this as
experimental until they have been independently verified.
If you don't know what to do here, say N.
endmenu
menu "Boot options"
config ZERO_PAGE_OFFSET
hex "Zero page offset"
default "0x00004000" if SH_SH03
default "0x00010000" if PAGE_SIZE_64KB
hex
default "0x00010000" if PAGE_SIZE_64KB || SH_RTS7751R2D || \
SH_7751_SOLUTION_ENGINE
default "0x00004000" if PAGE_SIZE_16KB || SH_SH03
default "0x00002000" if PAGE_SIZE_8KB
default "0x00001000"
help
This sets the default offset of zero page.
config BOOT_LINK_OFFSET
hex "Link address offset for booting"
hex
default "0x00210000" if SH_SHMIN
default "0x00400000" if SH_CAYMAN
default "0x00810000" if SH_7780_SOLUTION_ENGINE
default "0x009e0000" if SH_TITAN
default "0x01800000" if SH_SDK7780
default "0x02000000" if SH_EDOSK7760
default "0x00800000"
help
This option allows you to set the link address offset of the zImage.
This can be useful if you are on a board which has a small amount of
memory.
config ENTRY_OFFSET
hex
default "0x00001000" if PAGE_SIZE_4KB
default "0x00002000" if PAGE_SIZE_8KB
default "0x00004000" if PAGE_SIZE_16KB
default "0x00010000" if PAGE_SIZE_64KB
default "0x00000000"
config UBC_WAKEUP
bool "Wakeup UBC on startup"
depends on CPU_SH4 && !CPU_SH4A
arch/sh/Kconfig.cpu
-8
View File
@@ -76,11 +76,6 @@ config SPECULATIVE_EXECUTION
If unsure, say N.
config SH64_USER_MISALIGNED_FIXUP
def_bool y
prompt "Fixup misaligned loads/stores occurring in user mode"
depends on SUPERH64
config SH64_ID2815_WORKAROUND
bool "Include workaround for SH5-101 cut2 silicon defect ID2815"
depends on CPU_SUBTYPE_SH5_101
@@ -101,9 +96,6 @@ config CPU_HAS_SR_RB
See <file:Documentation/sh/register-banks.txt> for further
information on SR.RB and register banking in the kernel in general.
config CPU_HAS_PTEA
bool
config CPU_HAS_PTEAEX
bool
arch/sh/Kconfig.debug
+2 -21
View File
@@ -38,10 +38,10 @@ config EARLY_SCIF_CONSOLE_PORT
default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763 || \
CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366 || \
CPU_SUBTYPE_SH7343
default "0xffe80000" if CPU_SH4
default "0xffea0000" if CPU_SUBTYPE_SH7785
default "0xfffe8000" if CPU_SUBTYPE_SH7203
default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263
default "0xffe80000" if CPU_SH4
default "0x00000000"
config EARLY_PRINTK
@@ -92,7 +92,7 @@ config 4KSTACKS
config IRQSTACKS
bool "Use separate kernel stacks when processing interrupts"
depends on DEBUG_KERNEL && SUPERH32
depends on DEBUG_KERNEL && SUPERH32 && BROKEN
help
If you say Y here the kernel will use separate kernel stacks
for handling hard and soft interrupts. This can help avoid
@@ -122,27 +122,8 @@ config SH_NO_BSS_INIT
For all other cases, say N. If this option seems perplexing, or
you aren't sure, say N.
config MORE_COMPILE_OPTIONS
bool "Add any additional compile options"
help
If you want to add additional CFLAGS to the kernel build, enable this
option and then enter what you would like to add in the next question.
Note however that -g is already appended with the selection of KGDB.
config COMPILE_OPTIONS
string "Additional compile arguments"
depends on MORE_COMPILE_OPTIONS
config SH64_SR_WATCH
bool "Debug: set SR.WATCH to enable hardware watchpoints and trace"
depends on SUPERH64
config POOR_MANS_STRACE
bool "Debug: enable rudimentary strace facility"
depends on SUPERH64
help
This option allows system calls to be traced to the console. It also
aids in detecting kernel stack underflow. It is useful for debugging
early-userland problems (e.g. init incurring fatal exceptions.)
endmenu
arch/sh/Makefile
+26 -47
View File
@@ -70,9 +70,6 @@ cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += -ml
cflags-y += $(call cc-option,-mno-fdpic)
cflags-y += $(isaflags-y) -ffreestanding
cflags-$(CONFIG_MORE_COMPILE_OPTIONS) += \
$(shell echo $(CONFIG_COMPILE_OPTIONS) | sed -e 's/"//g')
OBJCOPYFLAGS := -O binary -R .note -R .note.gnu.build-id -R .comment \
-R .stab -R .stabstr -S
@@ -85,7 +82,6 @@ defaultimage-$(CONFIG_SH_7206_SOLUTION_ENGINE) := vmlinux
defaultimage-$(CONFIG_SH_7619_SOLUTION_ENGINE) := vmlinux
# Set some sensible Kbuild defaults
KBUILD_DEFCONFIG := shx3_defconfig
KBUILD_IMAGE := $(defaultimage-y)
#
@@ -93,26 +89,38 @@ KBUILD_IMAGE := $(defaultimage-y)
# error messages during linking.
#
ifdef CONFIG_SUPERH32
UTS_MACHINE := sh
LDFLAGS_vmlinux += -e _stext
UTS_MACHINE := sh
BITS := 32
LDFLAGS_vmlinux += -e _stext
KBUILD_DEFCONFIG := shx3_defconfig
else
UTS_MACHINE := sh64
LDFLAGS_vmlinux += --defsym phys_stext=_stext-$(CONFIG_PAGE_OFFSET) \
--defsym phys_stext_shmedia=phys_stext+1 \
-e phys_stext_shmedia
UTS_MACHINE := sh64
BITS := 64
LDFLAGS_vmlinux += --defsym phys_stext=_stext-$(CONFIG_PAGE_OFFSET) \
--defsym phys_stext_shmedia=phys_stext+1 \
-e phys_stext_shmedia
KBUILD_DEFCONFIG := cayman_defconfig
endif
ifneq ($(SUBARCH),$(ARCH))
ifeq ($(CROSS_COMPILE),)
CROSS_COMPILE := $(call cc-cross-prefix, $(UTS_MACHINE)-linux- $(UTS_MACHINE)-linux-gnu- $(UTS_MACHINE)-unknown-linux-gnu-)
endif
endif
ifdef CONFIG_CPU_LITTLE_ENDIAN
LDFLAGS_vmlinux += --defsym 'jiffies=jiffies_64'
ld-bfd := elf32-$(UTS_MACHINE)-linux
LDFLAGS_vmlinux += --defsym 'jiffies=jiffies_64' --oformat $(ld-bfd)
LDFLAGS += -EL
else
LDFLAGS_vmlinux += --defsym 'jiffies=jiffies_64+4'
ld-bfd := elf32-$(UTS_MACHINE)big-linux
LDFLAGS_vmlinux += --defsym 'jiffies=jiffies_64+4' --oformat $(ld-bfd)
LDFLAGS += -EB
endif
head-y := arch/sh/kernel/init_task.o
head-$(CONFIG_SUPERH32) += arch/sh/kernel/head_32.o
head-$(CONFIG_SUPERH64) += arch/sh/kernel/head_64.o
export ld-bfd BITS
head-y := arch/sh/kernel/init_task.o arch/sh/kernel/head_$(BITS).o
core-y += arch/sh/kernel/ arch/sh/mm/ arch/sh/boards/
core-$(CONFIG_SH_FPU_EMU) += arch/sh/math-emu/
@@ -193,10 +201,11 @@ zImage uImage uImage.srec vmlinux.srec: vmlinux
compressed: zImage
archprepare: maketools arch/sh/lib64/syscalltab.h
archprepare: maketools
archclean:
$(Q)$(MAKE) $(clean)=$(boot)
$(Q)$(MAKE) $(clean)=arch/sh/kernel/vsyscall
define archhelp
@echo '* zImage - Compressed kernel image'
@@ -205,34 +214,4 @@ define archhelp
@echo ' uImage.srec - Create an S-record for U-Boot'
endef
define filechk_gen-syscalltab
(set -e; \
echo "/*"; \
echo " * DO NOT MODIFY."; \
echo " *"; \
echo " * This file was generated by arch/sh/Makefile"; \
echo " * Any changes will be reverted at build time."; \
echo " */"; \
echo ""; \
echo "#ifndef __SYSCALLTAB_H"; \
echo "#define __SYSCALLTAB_H"; \
echo ""; \
echo "#include <linux/kernel.h>"; \
echo ""; \
echo "struct syscall_info {"; \
echo " const char *name;"; \
echo "} syscall_info_table[] = {"; \
sed -e '/^.*\.long /!d;s// { "/;s/\(\([^/]*\)\/\)\{1\}.*/\2/; \
s/[ \t]*$$//g;s/$$/" },/;s/\("\)sys_/\1/g'; \
echo "};"; \
echo ""; \
echo "#define NUM_SYSCALL_INFO_ENTRIES ARRAY_SIZE(syscall_info_table)";\
echo ""; \
echo "#endif /* __SYSCALLTAB_H */" )
endef
arch/sh/lib64/syscalltab.h: arch/sh/kernel/syscalls_64.S
$(call filechk,gen-syscalltab)
CLEAN_FILES += arch/sh/lib64/syscalltab.h \
include/asm-sh/machtypes.h
CLEAN_FILES += include/asm-sh/machtypes.h
arch/sh/boards/Kconfig
+12 -3
View File
@@ -46,6 +46,15 @@ config SH_7722_SOLUTION_ENGINE
Select 7722 SolutionEngine if configuring for a Hitachi SH772
evaluation board.
config SH_7724_SOLUTION_ENGINE
bool "SolutionEngine7724"
select SOLUTION_ENGINE
depends on CPU_SUBTYPE_SH7724
select ARCH_REQUIRE_GPIOLIB
help
Select 7724 SolutionEngine if configuring for a Hitachi SH7724
evaluation board.
config SH_7751_SOLUTION_ENGINE
bool "SolutionEngine7751"
select SOLUTION_ENGINE
@@ -121,7 +130,7 @@ config SH_RTS7751R2D
bool "RTS7751R2D"
depends on CPU_SUBTYPE_SH7751R
select SYS_SUPPORTS_PCI
select IO_TRAPPED
select IO_TRAPPED if MMU
help
Select RTS7751R2D if configuring for a Renesas Technology
Sales SH-Graphics board.
@@ -145,13 +154,13 @@ config SH_HIGHLANDER
bool "Highlander"
depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785
select SYS_SUPPORTS_PCI
select IO_TRAPPED
select IO_TRAPPED if MMU
config SH_SH7785LCR
bool "SH7785LCR"
depends on CPU_SUBTYPE_SH7785
select SYS_SUPPORTS_PCI
select IO_TRAPPED
select IO_TRAPPED if MMU
config SH_SH7785LCR_29BIT_PHYSMAPS
bool "SH7785LCR 29bit physmaps"
arch/sh/boards/board-ap325rxa.c
+12
View File
@@ -535,6 +535,18 @@ static int __init ap325rxa_devices_setup(void)
}
device_initcall(ap325rxa_devices_setup);
/* Return the board specific boot mode pin configuration */
static int ap325rxa_mode_pins(void)
{
/* MD0=0, MD1=0, MD2=0: Clock Mode 0
* MD3=0: 16-bit Area0 Bus Width
* MD5=1: Little Endian
* TSTMD=1, MD8=1: Test Mode Disabled
*/
return MODE_PIN5 | MODE_PIN8;
}
static struct sh_machine_vector mv_ap325rxa __initmv = {
.mv_name = "AP-325RXA",
.mv_mode_pins = ap325rxa_mode_pins,
};
arch/sh/boards/board-sh7785lcr.c
+42 -2
View File
@@ -2,12 +2,12 @@
* Renesas Technology Corp. R0P7785LC0011RL Support.
*
* Copyright (C) 2008 Yoshihiro Shimoda
* Copyright (C) 2009 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/sm501.h>
@@ -19,8 +19,12 @@
#include <linux/i2c-pca-platform.h>
#include <linux/i2c-algo-pca.h>
#include <linux/irq.h>
#include <asm/heartbeat.h>
#include <linux/clk.h>
#include <linux/errno.h>
#include <mach/sh7785lcr.h>
#include <asm/heartbeat.h>
#include <asm/clock.h>
#include <cpu/sh7785.h>
/*
* NOTE: This board has 2 physical memory maps.
@@ -273,6 +277,20 @@ void __init init_sh7785lcr_IRQ(void)
plat_irq_setup_pins(IRQ_MODE_IRQ3210);
}
static int sh7785lcr_clk_init(void)
{
struct clk *clk;
int ret;
clk = clk_get(NULL, "extal");
if (!clk || IS_ERR(clk))
return PTR_ERR(clk);
ret = clk_set_rate(clk, 33333333);
clk_put(clk);
return ret;
}
static void sh7785lcr_power_off(void)
{
unsigned char *p;
@@ -303,12 +321,34 @@ static void __init sh7785lcr_setup(char **cmdline_p)
writel(0x000307c2, sm501_reg);
}
/* Return the board specific boot mode pin configuration */
static int sh7785lcr_mode_pins(void)
{
int value = 0;
/* These are the factory default settings of S1 and S2.
* If you change these dip switches then you will need to
* adjust the values below as well.
*/
value |= MODE_PIN4; /* Clock Mode 16 */
value |= MODE_PIN5; /* 32-bit Area0 bus width */
value |= MODE_PIN6; /* 32-bit Area0 bus width */
value |= MODE_PIN7; /* Area 0 SRAM interface [fixed] */
value |= MODE_PIN8; /* Little Endian */
value |= MODE_PIN9; /* Master Mode */
value |= MODE_PIN14; /* No PLL step-up */
return value;
}
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_sh7785lcr __initmv = {
.mv_name = "SH7785LCR",
.mv_setup = sh7785lcr_setup,
.mv_clk_init = sh7785lcr_clk_init,
.mv_init_irq = init_sh7785lcr_IRQ,
.mv_mode_pins = sh7785lcr_mode_pins,
};
arch/sh/boards/mach-cayman/Makefile
+1 -1
View File
@@ -1,4 +1,4 @@
#
# Makefile for the Hitachi Cayman specific parts of the kernel
#
obj-y := setup.o irq.o
obj-y := setup.o irq.o panic.o
arch/sh/boards/mach-cayman/irq.c
+1 -16
View File
@@ -142,26 +142,11 @@ int cayman_irq_demux(int evt)
return irq;
}
#if defined(CONFIG_PROC_FS) && defined(CONFIG_SYSCTL)
int cayman_irq_describe(char* p, int irq)
{
if (irq < NR_INTC_IRQS) {
return intc_irq_describe(p, irq);
} else if (irq < NR_INTC_IRQS + 8) {
return sprintf(p, "(SMSC %d)", irq - NR_INTC_IRQS);
} else if ((irq >= NR_INTC_IRQS + 24) && (irq < NR_INTC_IRQS + 32)) {
return sprintf(p, "(PCI2 %d)", irq - (NR_INTC_IRQS + 24));
}
return 0;
}
#endif
void init_cayman_irq(void)
{
int i;
epld_virt = onchip_remap(EPLD_BASE, 1024, "EPLD");
epld_virt = (unsigned long)ioremap_nocache(EPLD_BASE, 1024);
if (!epld_virt) {
printk(KERN_ERR "Cayman IRQ: Unable to remap EPLD\n");
return;
arch/sh/boards/mach-cayman/panic.c
+49
View File
@@ -0,0 +1,49 @@
/*
* Copyright (C) 2003 Richard Curnow, SuperH UK Limited
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/kernel.h>
#include <linux/io.h>
#include <cpu/registers.h>
/* THIS IS A PHYSICAL ADDRESS */
#define HDSP2534_ADDR (0x04002100)
static void poor_mans_delay(void)
{
int i;
for (i = 0; i < 2500000; i++)
cpu_relax();
}
static void show_value(unsigned long x)
{
int i;
unsigned nibble;
for (i = 0; i < 8; i++) {
nibble = ((x >> (i * 4)) & 0xf);
__raw_writeb(nibble + ((nibble > 9) ? 55 : 48),
HDSP2534_ADDR + 0xe0 + ((7 - i) << 2));
}
}
void
panic_handler(unsigned long panicPC, unsigned long panicSSR,
unsigned long panicEXPEVT)
{
while (1) {
/* This piece of code displays the PC on the LED display */
show_value(panicPC);
poor_mans_delay();
show_value(panicSSR);
poor_mans_delay();
show_value(panicEXPEVT);
poor_mans_delay();
}
}
arch/sh/boards/mach-cayman/setup.c
+1 -1
View File
@@ -102,7 +102,7 @@ static int __init smsc_superio_setup(void)
{
unsigned char devid, devrev;
smsc_superio_virt = onchip_remap(SMSC_SUPERIO_BASE, 1024, "SMSC SuperIO");
smsc_superio_virt = (unsigned long)ioremap_nocache(SMSC_SUPERIO_BASE, 1024);
if (!smsc_superio_virt) {
panic("Unable to remap SMSC SuperIO\n");
}
arch/sh/boards/mach-dreamcast/setup.c
-6
View File
@@ -30,7 +30,6 @@
extern struct irq_chip systemasic_int;
extern void aica_time_init(void);
extern int gapspci_init(void);
extern int systemasic_irq_demux(int);
static void __init dreamcast_setup(char **cmdline_p)
@@ -51,11 +50,6 @@ static void __init dreamcast_setup(char **cmdline_p)
handle_level_irq);
board_time_init = aica_time_init;
#ifdef CONFIG_PCI
if (gapspci_init() < 0)
printk(KERN_WARNING "GAPSPCI was not detected.\n");
#endif
}
static struct sh_machine_vector mv_dreamcast __initmv = {
arch/sh/boards/mach-migor/setup.c
+19
View File
@@ -584,3 +584,22 @@ static int __init migor_devices_setup(void)
return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
}
__initcall(migor_devices_setup);
/* Return the board specific boot mode pin configuration */
static int migor_mode_pins(void)
{
/* MD0=1, MD1=1, MD2=0: Clock Mode 3
* MD3=0: 16-bit Area0 Bus Width
* MD5=1: Little Endian
* TSTMD=1, MD8=0: Test Mode Disabled
*/
return MODE_PIN0 | MODE_PIN1 | MODE_PIN5;
}
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_migor __initmv = {
.mv_name = "Migo-R",
.mv_mode_pins = migor_mode_pins,
};
arch/sh/boards/mach-r2d/setup.c
+50
View File
@@ -10,6 +10,9 @@
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/ata_platform.h>
#include <linux/sm501.h>
#include <linux/sm501-regs.h>
@@ -181,6 +184,50 @@ static struct platform_device sm501_device = {
.resource = sm501_resources,
};
static struct mtd_partition r2d_partitions[] = {
{
.name = "U-Boot",
.offset = 0x00000000,
.size = 0x00040000,
.mask_flags = MTD_WRITEABLE,
}, {
.name = "Environment",
.offset = MTDPART_OFS_NXTBLK,
.size = 0x00040000,
.mask_flags = MTD_WRITEABLE,
}, {
.name = "Kernel",
.offset = MTDPART_OFS_NXTBLK,
.size = 0x001c0000,
}, {
.name = "Flash_FS",
.offset = MTDPART_OFS_NXTBLK,
.size = MTDPART_SIZ_FULL,
}
};
static struct physmap_flash_data flash_data = {
.width = 2,
.nr_parts = ARRAY_SIZE(r2d_partitions),
.parts = r2d_partitions,
};
static struct resource flash_resource = {
.start = 0x00000000,
.end = 0x02000000,
.flags = IORESOURCE_MEM,
};
static struct platform_device flash_device = {
.name = "physmap-flash",
.id = -1,
.resource = &flash_resource,
.num_resources = 1,
.dev = {
.platform_data = &flash_data,
},
};
static struct platform_device *rts7751r2d_devices[] __initdata = {
&sm501_device,
&heartbeat_device,
@@ -203,6 +250,9 @@ static int __init rts7751r2d_devices_setup(void)
if (register_trapped_io(&cf_trapped_io) == 0)
platform_device_register(&cf_ide_device);
if (mach_is_r2d_plus())
platform_device_register(&flash_device);
spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus));
return platform_add_devices(rts7751r2d_devices,
arch/sh/boards/mach-se/7724/Makefile
+10
View File
@@ -0,0 +1,10 @@
#
# Makefile for the HITACHI UL SolutionEngine 7724 specific parts of the kernel
#
# This file is subject to the terms and conditions of the GNU General Public
# License. See the file "COPYING" in the main directory of this archive
# for more details.
#
#
obj-y := setup.o irq.o
arch/sh/boards/mach-se/7724/irq.c
+139
View File
@@ -0,0 +1,139 @@
/*
* linux/arch/sh/boards/se/7724/irq.c
*
* Copyright (C) 2009 Renesas Solutions Corp.
*
* Kuninori Morimoto <morimoto.kuninori@renesas.com>
*
* Based on linux/arch/sh/boards/se/7722/irq.c
* Copyright (C) 2007 Nobuhiro Iwamatsu
*
* Hitachi UL SolutionEngine 7724 Support.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <mach-se/mach/se7724.h>
struct fpga_irq {
unsigned long sraddr;
unsigned long mraddr;
unsigned short mask;
unsigned int base;
};
static unsigned int fpga2irq(unsigned int irq)
{
if (irq >= IRQ0_BASE &&
irq <= IRQ0_END)
return IRQ0_IRQ;
else if (irq >= IRQ1_BASE &&
irq <= IRQ1_END)
return IRQ1_IRQ;
else
return IRQ2_IRQ;
}
static struct fpga_irq get_fpga_irq(unsigned int irq)
{
struct fpga_irq set;
switch (irq) {
case IRQ0_IRQ:
set.sraddr = IRQ0_SR;
set.mraddr = IRQ0_MR;
set.mask = IRQ0_MASK;
set.base = IRQ0_BASE;
break;
case IRQ1_IRQ:
set.sraddr = IRQ1_SR;
set.mraddr = IRQ1_MR;
set.mask = IRQ1_MASK;
set.base = IRQ1_BASE;
break;
default:
set.sraddr = IRQ2_SR;
set.mraddr = IRQ2_MR;
set.mask = IRQ2_MASK;
set.base = IRQ2_BASE;
break;
}
return set;
}
static void disable_se7724_irq(unsigned int irq)
{
struct fpga_irq set = get_fpga_irq(fpga2irq(irq));
unsigned int bit = irq - set.base;
ctrl_outw(ctrl_inw(set.mraddr) | 0x0001 << bit, set.mraddr);
}
static void enable_se7724_irq(unsigned int irq)
{
struct fpga_irq set = get_fpga_irq(fpga2irq(irq));
unsigned int bit = irq - set.base;
ctrl_outw(ctrl_inw(set.mraddr) & ~(0x0001 << bit), set.mraddr);
}
static struct irq_chip se7724_irq_chip __read_mostly = {
.name = "SE7724-FPGA",
.mask = disable_se7724_irq,
.unmask = enable_se7724_irq,
.mask_ack = disable_se7724_irq,
};
static void se7724_irq_demux(unsigned int irq, struct irq_desc *desc)
{
struct fpga_irq set = get_fpga_irq(irq);
unsigned short intv = ctrl_inw(set.sraddr);
struct irq_desc *ext_desc;
unsigned int ext_irq = set.base;
intv &= set.mask;
while (intv) {
if (intv & 0x0001) {
ext_desc = irq_desc + ext_irq;
handle_level_irq(ext_irq, ext_desc);
}
intv >>= 1;
ext_irq++;
}
}
/*
* Initialize IRQ setting
*/
void __init init_se7724_IRQ(void)
{
int i;
ctrl_outw(0xffff, IRQ0_MR); /* mask all */
ctrl_outw(0xffff, IRQ1_MR); /* mask all */
ctrl_outw(0xffff, IRQ2_MR); /* mask all */
ctrl_outw(0x0000, IRQ0_SR); /* clear irq */
ctrl_outw(0x0000, IRQ1_SR); /* clear irq */
ctrl_outw(0x0000, IRQ2_SR); /* clear irq */
ctrl_outw(0x002a, IRQ_MODE); /* set irq type */
for (i = 0; i < SE7724_FPGA_IRQ_NR; i++)
set_irq_chip_and_handler_name(SE7724_FPGA_IRQ_BASE + i,
&se7724_irq_chip,
handle_level_irq, "level");
set_irq_chained_handler(IRQ0_IRQ, se7724_irq_demux);
set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
set_irq_chained_handler(IRQ1_IRQ, se7724_irq_demux);
set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
set_irq_chained_handler(IRQ2_IRQ, se7724_irq_demux);
set_irq_type(IRQ2_IRQ, IRQ_TYPE_LEVEL_LOW);
}
arch/sh/boards/mach-se/7724/setup.c
+448
View File
@@ -0,0 +1,448 @@
/*
* linux/arch/sh/boards/se/7724/setup.c
*
* Copyright (C) 2009 Renesas Solutions Corp.
*
* Kuninori Morimoto <morimoto.kuninori@renesas.com>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/delay.h>
#include <linux/smc91x.h>
#include <linux/gpio.h>
#include <linux/input.h>
#include <video/sh_mobile_lcdc.h>
#include <media/sh_mobile_ceu.h>
#include <asm/io.h>
#include <asm/heartbeat.h>
#include <asm/sh_keysc.h>
#include <cpu/sh7724.h>
#include <mach-se/mach/se7724.h>
/*
* SWx 1234 5678
* ------------------------------------
* SW31 : 1001 1100 : default
* SW32 : 0111 1111 : use on board flash
*
* SW41 : abxx xxxx -> a = 0 : Analog monitor
* 1 : Digital monitor
* b = 0 : VGA
* 1 : SVGA
*/
/* Heartbeat */
static struct heartbeat_data heartbeat_data = {
.regsize = 16,
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = &heartbeat_data,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
};
/* LAN91C111 */
static struct smc91x_platdata smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
};
static struct resource smc91x_eth_resources[] = {
[0] = {
.name = "SMC91C111" ,
.start = 0x1a300300,
.end = 0x1a30030f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ0_SMC,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
},
};
static struct platform_device smc91x_eth_device = {
.name = "smc91x",
.num_resources = ARRAY_SIZE(smc91x_eth_resources),
.resource = smc91x_eth_resources,
.dev = {
.platform_data = &smc91x_info,
},
};
/* MTD */
static struct mtd_partition nor_flash_partitions[] = {
{
.name = "uboot",
.offset = 0,
.size = (1 * 1024 * 1024),
.mask_flags = MTD_WRITEABLE, /* Read-only */
}, {
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = (2 * 1024 * 1024),
}, {
.name = "free-area",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static struct physmap_flash_data nor_flash_data = {
.width = 2,
.parts = nor_flash_partitions,
.nr_parts = ARRAY_SIZE(nor_flash_partitions),
};
static struct resource nor_flash_resources[] = {
[0] = {
.name = "NOR Flash",
.start = 0x00000000,
.end = 0x01ffffff,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device nor_flash_device = {
.name = "physmap-flash",
.resource = nor_flash_resources,
.num_resources = ARRAY_SIZE(nor_flash_resources),
.dev = {
.platform_data = &nor_flash_data,
},
};
/* LCDC */
static struct sh_mobile_lcdc_info lcdc_info = {
.clock_source = LCDC_CLK_EXTERNAL,
.ch[0] = {
.chan = LCDC_CHAN_MAINLCD,
.bpp = 16,
.clock_divider = 1,
.lcd_cfg = {
.name = "LB070WV1",
.sync = 0, /* hsync and vsync are active low */
},
.lcd_size_cfg = { /* 7.0 inch */
.width = 152,
.height = 91,
},
.board_cfg = {
},
}
};
static struct resource lcdc_resources[] = {
[0] = {
.name = "LCDC",
.start = 0xfe940000,
.end = 0xfe941fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 106,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device lcdc_device = {
.name = "sh_mobile_lcdc_fb",
.num_resources = ARRAY_SIZE(lcdc_resources),
.resource = lcdc_resources,
.dev = {
.platform_data = &lcdc_info,
},
};
/* CEU0 */
static struct sh_mobile_ceu_info sh_mobile_ceu0_info = {
.flags = SH_CEU_FLAG_USE_8BIT_BUS,
};
static struct resource ceu0_resources[] = {
[0] = {
.name = "CEU0",
.start = 0xfe910000,
.end = 0xfe91009f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 52,
.flags = IORESOURCE_IRQ,
},
[2] = {
/* place holder for contiguous memory */
},
};
static struct platform_device ceu0_device = {
.name = "sh_mobile_ceu",
.id = 0, /* "ceu0" clock */
.num_resources = ARRAY_SIZE(ceu0_resources),
.resource = ceu0_resources,
.dev = {
.platform_data = &sh_mobile_ceu0_info,
},
};
/* CEU1 */
static struct sh_mobile_ceu_info sh_mobile_ceu1_info = {
.flags = SH_CEU_FLAG_USE_8BIT_BUS,
};
static struct resource ceu1_resources[] = {
[0] = {
.name = "CEU1",
.start = 0xfe914000,
.end = 0xfe91409f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 63,
.flags = IORESOURCE_IRQ,
},
[2] = {
/* place holder for contiguous memory */
},
};
static struct platform_device ceu1_device = {
.name = "sh_mobile_ceu",
.id = 1, /* "ceu1" clock */
.num_resources = ARRAY_SIZE(ceu1_resources),
.resource = ceu1_resources,
.dev = {
.platform_data = &sh_mobile_ceu1_info,
},
};
/* KEYSC */
static struct sh_keysc_info keysc_info = {
.mode = SH_KEYSC_MODE_1,
.scan_timing = 10,
.delay = 50,
.keycodes = {
KEY_1, KEY_2, KEY_3, KEY_4, KEY_5,
KEY_6, KEY_7, KEY_8, KEY_9, KEY_A,
KEY_B, KEY_C, KEY_D, KEY_E, KEY_F,
KEY_G, KEY_H, KEY_I, KEY_K, KEY_L,
KEY_M, KEY_N, KEY_O, KEY_P, KEY_Q,
KEY_R, KEY_S, KEY_T, KEY_U, KEY_V,
},
};
static struct resource keysc_resources[] = {
[0] = {
.start = 0x1a204000,
.end = 0x1a20400f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ0_KEY,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device keysc_device = {
.name = "sh_keysc",
.id = 0, /* "keysc0" clock */
.num_resources = ARRAY_SIZE(keysc_resources),
.resource = keysc_resources,
.dev = {
.platform_data = &keysc_info,
},
};
static struct platform_device *ms7724se_devices[] __initdata = {
&heartbeat_device,
&smc91x_eth_device,
&lcdc_device,
&nor_flash_device,
&ceu0_device,
&ceu1_device,
&keysc_device,
};
#define SW4140 0xBA201000
#define FPGA_OUT 0xBA200400
#define PORT_HIZA 0xA4050158
#define SW41_A 0x0100
#define SW41_B 0x0200
#define SW41_C 0x0400
#define SW41_D 0x0800
#define SW41_E 0x1000
#define SW41_F 0x2000
#define SW41_G 0x4000
#define SW41_H 0x8000
static int __init devices_setup(void)
{
u16 sw = ctrl_inw(SW4140); /* select camera, monitor */
/* Reset Release */
ctrl_outw(ctrl_inw(FPGA_OUT) &
~((1 << 1) | /* LAN */
(1 << 6) | /* VIDEO DAC */
(1 << 12)), /* USB0 */
FPGA_OUT);
/* enable IRQ 0,1,2 */
gpio_request(GPIO_FN_INTC_IRQ0, NULL);
gpio_request(GPIO_FN_INTC_IRQ1, NULL);
gpio_request(GPIO_FN_INTC_IRQ2, NULL);
/* enable SCIFA3 */
gpio_request(GPIO_FN_SCIF3_I_SCK, NULL);
gpio_request(GPIO_FN_SCIF3_I_RXD, NULL);
gpio_request(GPIO_FN_SCIF3_I_TXD, NULL);
gpio_request(GPIO_FN_SCIF3_I_CTS, NULL);
gpio_request(GPIO_FN_SCIF3_I_RTS, NULL);
/* enable LCDC */
gpio_request(GPIO_FN_LCDD23, NULL);
gpio_request(GPIO_FN_LCDD22, NULL);
gpio_request(GPIO_FN_LCDD21, NULL);
gpio_request(GPIO_FN_LCDD20, NULL);
gpio_request(GPIO_FN_LCDD19, NULL);
gpio_request(GPIO_FN_LCDD18, NULL);
gpio_request(GPIO_FN_LCDD17, NULL);
gpio_request(GPIO_FN_LCDD16, NULL);
gpio_request(GPIO_FN_LCDD15, NULL);
gpio_request(GPIO_FN_LCDD14, NULL);
gpio_request(GPIO_FN_LCDD13, NULL);
gpio_request(GPIO_FN_LCDD12, NULL);
gpio_request(GPIO_FN_LCDD11, NULL);
gpio_request(GPIO_FN_LCDD10, NULL);
gpio_request(GPIO_FN_LCDD9, NULL);
gpio_request(GPIO_FN_LCDD8, NULL);
gpio_request(GPIO_FN_LCDD7, NULL);
gpio_request(GPIO_FN_LCDD6, NULL);
gpio_request(GPIO_FN_LCDD5, NULL);
gpio_request(GPIO_FN_LCDD4, NULL);
gpio_request(GPIO_FN_LCDD3, NULL);
gpio_request(GPIO_FN_LCDD2, NULL);
gpio_request(GPIO_FN_LCDD1, NULL);
gpio_request(GPIO_FN_LCDD0, NULL);
gpio_request(GPIO_FN_LCDDISP, NULL);
gpio_request(GPIO_FN_LCDHSYN, NULL);
gpio_request(GPIO_FN_LCDDCK, NULL);
gpio_request(GPIO_FN_LCDVSYN, NULL);
gpio_request(GPIO_FN_LCDDON, NULL);
gpio_request(GPIO_FN_LCDVEPWC, NULL);
gpio_request(GPIO_FN_LCDVCPWC, NULL);
gpio_request(GPIO_FN_LCDRD, NULL);
gpio_request(GPIO_FN_LCDLCLK, NULL);
ctrl_outw((ctrl_inw(PORT_HIZA) & ~0x0001), PORT_HIZA);
/* enable CEU0 */
gpio_request(GPIO_FN_VIO0_D15, NULL);
gpio_request(GPIO_FN_VIO0_D14, NULL);
gpio_request(GPIO_FN_VIO0_D13, NULL);
gpio_request(GPIO_FN_VIO0_D12, NULL);
gpio_request(GPIO_FN_VIO0_D11, NULL);
gpio_request(GPIO_FN_VIO0_D10, NULL);
gpio_request(GPIO_FN_VIO0_D9, NULL);
gpio_request(GPIO_FN_VIO0_D8, NULL);
gpio_request(GPIO_FN_VIO0_D7, NULL);
gpio_request(GPIO_FN_VIO0_D6, NULL);
gpio_request(GPIO_FN_VIO0_D5, NULL);
gpio_request(GPIO_FN_VIO0_D4, NULL);
gpio_request(GPIO_FN_VIO0_D3, NULL);
gpio_request(GPIO_FN_VIO0_D2, NULL);
gpio_request(GPIO_FN_VIO0_D1, NULL);
gpio_request(GPIO_FN_VIO0_D0, NULL);
gpio_request(GPIO_FN_VIO0_VD, NULL);
gpio_request(GPIO_FN_VIO0_CLK, NULL);
gpio_request(GPIO_FN_VIO0_FLD, NULL);
gpio_request(GPIO_FN_VIO0_HD, NULL);
platform_resource_setup_memory(&ceu0_device, "ceu", 4 << 20);
/* enable CEU1 */
gpio_request(GPIO_FN_VIO1_D7, NULL);
gpio_request(GPIO_FN_VIO1_D6, NULL);
gpio_request(GPIO_FN_VIO1_D5, NULL);
gpio_request(GPIO_FN_VIO1_D4, NULL);
gpio_request(GPIO_FN_VIO1_D3, NULL);
gpio_request(GPIO_FN_VIO1_D2, NULL);
gpio_request(GPIO_FN_VIO1_D1, NULL);
gpio_request(GPIO_FN_VIO1_D0, NULL);
gpio_request(GPIO_FN_VIO1_FLD, NULL);
gpio_request(GPIO_FN_VIO1_HD, NULL);
gpio_request(GPIO_FN_VIO1_VD, NULL);
gpio_request(GPIO_FN_VIO1_CLK, NULL);
platform_resource_setup_memory(&ceu1_device, "ceu", 4 << 20);
/* KEYSC */
gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
gpio_request(GPIO_FN_KEYIN4, NULL);
gpio_request(GPIO_FN_KEYIN3, NULL);
gpio_request(GPIO_FN_KEYIN2, NULL);
gpio_request(GPIO_FN_KEYIN1, NULL);
gpio_request(GPIO_FN_KEYIN0, NULL);
gpio_request(GPIO_FN_KEYOUT3, NULL);
gpio_request(GPIO_FN_KEYOUT2, NULL);
gpio_request(GPIO_FN_KEYOUT1, NULL);
gpio_request(GPIO_FN_KEYOUT0, NULL);
if (sw & SW41_B) {
/* SVGA */
lcdc_info.ch[0].lcd_cfg.xres = 800;
lcdc_info.ch[0].lcd_cfg.yres = 600;
lcdc_info.ch[0].lcd_cfg.left_margin = 142;
lcdc_info.ch[0].lcd_cfg.right_margin = 52;
lcdc_info.ch[0].lcd_cfg.hsync_len = 96;
lcdc_info.ch[0].lcd_cfg.upper_margin = 24;
lcdc_info.ch[0].lcd_cfg.lower_margin = 2;
lcdc_info.ch[0].lcd_cfg.vsync_len = 2;
} else {
/* VGA */
lcdc_info.ch[0].lcd_cfg.xres = 640;
lcdc_info.ch[0].lcd_cfg.yres = 480;
lcdc_info.ch[0].lcd_cfg.left_margin = 105;
lcdc_info.ch[0].lcd_cfg.right_margin = 50;
lcdc_info.ch[0].lcd_cfg.hsync_len = 96;
lcdc_info.ch[0].lcd_cfg.upper_margin = 33;
lcdc_info.ch[0].lcd_cfg.lower_margin = 10;
lcdc_info.ch[0].lcd_cfg.vsync_len = 2;
}
if (sw & SW41_A) {
/* Digital monitor */
lcdc_info.ch[0].interface_type = RGB18;
lcdc_info.ch[0].flags = 0;
} else {
/* Analog monitor */
lcdc_info.ch[0].interface_type = RGB24;
lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
}
return platform_add_devices(ms7724se_devices,
ARRAY_SIZE(ms7724se_devices));
}
device_initcall(devices_setup);
static struct sh_machine_vector mv_ms7724se __initmv = {
.mv_name = "ms7724se",
.mv_init_irq = init_se7724_IRQ,
.mv_nr_irqs = SE7724_FPGA_IRQ_BASE + SE7724_FPGA_IRQ_NR,
};
arch/sh/boards/mach-se/7751/Makefile
-2
View File
@@ -3,5 +3,3 @@
#
obj-y := setup.o io.o irq.o
obj-$(CONFIG_PCI) += pci.o
arch/sh/boards/mach-se/7751/io.c
-16
View File
@@ -34,8 +34,6 @@ unsigned char sh7751se_inb(unsigned long port)
{
if (PXSEG(port))
return *(volatile unsigned char *)port;
else if (is_pci_ioaddr(port))
return *(volatile unsigned char *)pci_ioaddr(port);
else
return (*port2adr(port)) & 0xff;
}
@@ -46,8 +44,6 @@ unsigned char sh7751se_inb_p(unsigned long port)
if (PXSEG(port))
v = *(volatile unsigned char *)port;
else if (is_pci_ioaddr(port))
v = *(volatile unsigned char *)pci_ioaddr(port);
else
v = (*port2adr(port)) & 0xff;
ctrl_delay();
@@ -58,8 +54,6 @@ unsigned short sh7751se_inw(unsigned long port)
{
if (PXSEG(port))
return *(volatile unsigned short *)port;
else if (is_pci_ioaddr(port))
return *(volatile unsigned short *)pci_ioaddr(port);
else if (port >= 0x2000)
return *port2adr(port);
else
@@ -71,8 +65,6 @@ unsigned int sh7751se_inl(unsigned long port)
{
if (PXSEG(port))
return *(volatile unsigned long *)port;
else if (is_pci_ioaddr(port))
return *(volatile unsigned int *)pci_ioaddr(port);
else if (port >= 0x2000)
return *port2adr(port);
else
@@ -85,8 +77,6 @@ void sh7751se_outb(unsigned char value, unsigned long port)
if (PXSEG(port))
*(volatile unsigned char *)port = value;
else if (is_pci_ioaddr(port))
*((unsigned char*)pci_ioaddr(port)) = value;
else
*(port2adr(port)) = value;
}
@@ -95,8 +85,6 @@ void sh7751se_outb_p(unsigned char value, unsigned long port)
{
if (PXSEG(port))
*(volatile unsigned char *)port = value;
else if (is_pci_ioaddr(port))
*((unsigned char*)pci_ioaddr(port)) = value;
else
*(port2adr(port)) = value;
ctrl_delay();
@@ -106,8 +94,6 @@ void sh7751se_outw(unsigned short value, unsigned long port)
{
if (PXSEG(port))
*(volatile unsigned short *)port = value;
else if (is_pci_ioaddr(port))
*((unsigned short *)pci_ioaddr(port)) = value;
else if (port >= 0x2000)
*port2adr(port) = value;
else
@@ -118,8 +104,6 @@ void sh7751se_outl(unsigned int value, unsigned long port)
{
if (PXSEG(port))
*(volatile unsigned long *)port = value;
else if (is_pci_ioaddr(port))
*((unsigned long*)pci_ioaddr(port)) = value;
else
maybebadio(port);
}
arch/sh/boards/mach-se/7751/pci.c
-147
View File
@@ -1,147 +0,0 @@
/*
* linux/arch/sh/boards/se/7751/pci.c
*
* Author: Ian DaSilva (idasilva@mvista.com)
*
* Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* PCI initialization for the Hitachi SH7751 Solution Engine board (MS7751SE01)
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <asm/io.h>
#include "../../../drivers/pci/pci-sh7751.h"
#define PCIMCR_MRSET_OFF 0xBFFFFFFF
#define PCIMCR_RFSH_OFF 0xFFFFFFFB
/*
* Only long word accesses of the PCIC's internal local registers and the
* configuration registers from the CPU is supported.
*/
#define PCIC_WRITE(x,v) writel((v), PCI_REG(x))
#define PCIC_READ(x) readl(PCI_REG(x))
/*
* Description: This function sets up and initializes the pcic, sets
* up the BARS, maps the DRAM into the address space etc, etc.
*/
int __init pcibios_init_platform(void)
{
unsigned long bcr1, wcr1, wcr2, wcr3, mcr;
unsigned short bcr2;
/*
* Initialize the slave bus controller on the pcic. The values used
* here should not be hardcoded, but they should be taken from the bsc
* on the processor, to make this function as generic as possible.
* (i.e. Another sbc may usr different SDRAM timing settings -- in order
* for the pcic to work, its settings need to be exactly the same.)
*/
bcr1 = (*(volatile unsigned long*)(SH7751_BCR1));
bcr2 = (*(volatile unsigned short*)(SH7751_BCR2));
wcr1 = (*(volatile unsigned long*)(SH7751_WCR1));
wcr2 = (*(volatile unsigned long*)(SH7751_WCR2));
wcr3 = (*(volatile unsigned long*)(SH7751_WCR3));
mcr = (*(volatile unsigned long*)(SH7751_MCR));
bcr1 = bcr1 | 0x00080000; /* Enable Bit 19, BREQEN */
(*(volatile unsigned long*)(SH7751_BCR1)) = bcr1;
bcr1 = bcr1 | 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
PCIC_WRITE(SH7751_PCIBCR1, bcr1); /* PCIC BCR1 */
PCIC_WRITE(SH7751_PCIBCR2, bcr2); /* PCIC BCR2 */
PCIC_WRITE(SH7751_PCIWCR1, wcr1); /* PCIC WCR1 */
PCIC_WRITE(SH7751_PCIWCR2, wcr2); /* PCIC WCR2 */
PCIC_WRITE(SH7751_PCIWCR3, wcr3); /* PCIC WCR3 */
mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
PCIC_WRITE(SH7751_PCIMCR, mcr); /* PCIC MCR */
/* Enable all interrupts, so we know what to fix */
PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff);
PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f);
/* Set up standard PCI config registers */
PCIC_WRITE(SH7751_PCICONF1, 0xF39000C7); /* Bus Master, Mem & I/O access */
PCIC_WRITE(SH7751_PCICONF2, 0x00000000); /* PCI Class code & Revision ID */
PCIC_WRITE(SH7751_PCICONF4, 0xab000001); /* PCI I/O address (local regs) */
PCIC_WRITE(SH7751_PCICONF5, 0x0c000000); /* PCI MEM address (local RAM) */
PCIC_WRITE(SH7751_PCICONF6, 0xd0000000); /* PCI MEM address (unused) */
PCIC_WRITE(SH7751_PCICONF11, 0x35051054); /* PCI Subsystem ID & Vendor ID */
PCIC_WRITE(SH7751_PCILSR0, 0x03f00000); /* MEM (full 64M exposed) */
PCIC_WRITE(SH7751_PCILSR1, 0x00000000); /* MEM (unused) */
PCIC_WRITE(SH7751_PCILAR0, 0x0c000000); /* MEM (direct map from PCI) */
PCIC_WRITE(SH7751_PCILAR1, 0x00000000); /* MEM (unused) */
/* Now turn it on... */
PCIC_WRITE(SH7751_PCICR, 0xa5000001);
/*
* Set PCIMBR and PCIIOBR here, assuming a single window
* (16M MEM, 256K IO) is enough. If a larger space is
* needed, the readx/writex and inx/outx functions will
* have to do more (e.g. setting registers for each call).
*/
/*
* Set the MBR so PCI address is one-to-one with window,
* meaning all calls go straight through... use BUG_ON to
* catch erroneous assumption.
*/
BUG_ON(PCIBIOS_MIN_MEM != SH7751_PCI_MEMORY_BASE);
PCIC_WRITE(SH7751_PCIMBR, PCIBIOS_MIN_MEM);
/* Set IOBR for window containing area specified in pci.h */
PCIC_WRITE(SH7751_PCIIOBR, (PCIBIOS_MIN_IO & SH7751_PCIIOBR_MASK));
/* All done, may as well say so... */
printk("SH7751 PCI: Finished initialization of the PCI controller\n");
return 1;
}
int __init pcibios_map_platform_irq(u8 slot, u8 pin)
{
switch (slot) {
case 0: return 13;
case 1: return 13; /* AMD Ethernet controller */
case 2: return -1;
case 3: return -1;
case 4: return -1;
default:
printk("PCI: Bad IRQ mapping request for slot %d\n", slot);
return -1;
}
}
static struct resource sh7751_io_resource = {
.name = "SH7751 IO",
.start = SH7751_PCI_IO_BASE,
.end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
.flags = IORESOURCE_IO
};
static struct resource sh7751_mem_resource = {
.name = "SH7751 mem",
.start = SH7751_PCI_MEMORY_BASE,
.end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM
};
extern struct pci_ops sh7751_pci_ops;
struct pci_channel board_pci_channels[] = {
{ &sh7751_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
{ NULL, NULL, NULL, 0, 0 },
};

Some files were not shown because too many files have changed in this diff Show More