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[media] Driver for Toshiba TC358743 HDMI to CSI-2 bridge
The driver is tested on our hardware and all the implemented features works as expected. Missing features: - CEC support - HDCP repeater support - IR support Signed-off-by: Mats Randgaard <matrandg@cisco.com> [hans.verkuil@cisco.com: updated copyright year to 2015] [hans.verkuil@cisco.com: update confusing confctl_mutex comment] Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
This commit is contained in:
committed by
Mauro Carvalho Chehab
parent
bde2b96d6d
commit
d32d98642d
@@ -10319,6 +10319,13 @@ F: drivers/char/toshiba.c
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F: include/linux/toshiba.h
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F: include/uapi/linux/toshiba.h
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TOSHIBA TC358743 DRIVER
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M: Mats Randgaard <matrandg@cisco.com>
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L: linux-media@vger.kernel.org
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S: Maintained
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F: drivers/media/i2c/tc358743*
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F: include/media/tc358743.h
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TMIO MMC DRIVER
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M: Ian Molton <ian@mnementh.co.uk>
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L: linux-mmc@vger.kernel.org
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@@ -287,6 +287,15 @@ config VIDEO_SAA711X
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To compile this driver as a module, choose M here: the
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module will be called saa7115.
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config VIDEO_TC358743
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tristate "Toshiba TC358743 decoder"
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depends on VIDEO_V4L2 && I2C
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---help---
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Support for the Toshiba TC358743 HDMI to MIPI CSI-2 bridge.
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To compile this driver as a module, choose M here: the
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module will be called tc358743.
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config VIDEO_TVP514X
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tristate "Texas Instruments TVP514x video decoder"
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depends on VIDEO_V4L2 && I2C
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@@ -78,3 +78,4 @@ obj-$(CONFIG_VIDEO_AK881X) += ak881x.o
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obj-$(CONFIG_VIDEO_IR_I2C) += ir-kbd-i2c.o
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obj-$(CONFIG_VIDEO_ML86V7667) += ml86v7667.o
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obj-$(CONFIG_VIDEO_OV2659) += ov2659.o
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obj-$(CONFIG_VIDEO_TC358743) += tc358743.o
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,131 @@
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/*
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* tc358743 - Toshiba HDMI to CSI-2 bridge
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*
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* Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights
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* reserved.
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*
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* This program is free software; you may redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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/*
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* References (c = chapter, p = page):
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* REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
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* REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
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*/
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#ifndef _TC358743_
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#define _TC358743_
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enum tc358743_ddc5v_delays {
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DDC5V_DELAY_0_MS,
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DDC5V_DELAY_50_MS,
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DDC5V_DELAY_100_MS,
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DDC5V_DELAY_200_MS,
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};
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enum tc358743_hdmi_detection_delay {
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HDMI_MODE_DELAY_0_MS,
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HDMI_MODE_DELAY_25_MS,
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HDMI_MODE_DELAY_50_MS,
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HDMI_MODE_DELAY_100_MS,
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};
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struct tc358743_platform_data {
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/* System clock connected to REFCLK (pin H5) */
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u32 refclk_hz; /* 26 MHz, 27 MHz or 42 MHz */
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/* DDC +5V debounce delay to avoid spurious interrupts when the cable
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* is connected.
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* Sets DDC5V_MODE in register DDC_CTL.
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* Default: DDC5V_DELAY_0_MS
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*/
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enum tc358743_ddc5v_delays ddc5v_delay;
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bool enable_hdcp;
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/*
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* The FIFO size is 512x32, so Toshiba recommend to set the default FIFO
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* level to somewhere in the middle (e.g. 300), so it can cover speed
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* mismatches in input and output ports.
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*/
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u16 fifo_level;
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/* Bps pr lane is (refclk_hz / pll_prd) * pll_fbd */
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u16 pll_prd;
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u16 pll_fbd;
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/* CSI
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* Calculate CSI parameters with REF_02 for the highest resolution your
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* CSI interface can handle. The driver will adjust the number of CSI
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* lanes in use according to the pixel clock.
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*
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* The values in brackets are calculated with REF_02 when the number of
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* bps pr lane is 823.5 MHz, and can serve as a starting point.
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*/
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u32 lineinitcnt; /* (0x00001770) */
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u32 lptxtimecnt; /* (0x00000005) */
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u32 tclk_headercnt; /* (0x00001d04) */
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u32 tclk_trailcnt; /* (0x00000000) */
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u32 ths_headercnt; /* (0x00000505) */
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u32 twakeup; /* (0x00004650) */
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u32 tclk_postcnt; /* (0x00000000) */
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u32 ths_trailcnt; /* (0x00000004) */
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u32 hstxvregcnt; /* (0x00000005) */
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/* DVI->HDMI detection delay to avoid unnecessary switching between DVI
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* and HDMI mode.
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* Sets HDMI_DET_V in register HDMI_DET.
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* Default: HDMI_MODE_DELAY_0_MS
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*/
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enum tc358743_hdmi_detection_delay hdmi_detection_delay;
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/* Reset PHY automatically when TMDS clock goes from DC to AC.
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* Sets PHY_AUTO_RST2 in register PHY_CTL2.
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* Default: false
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*/
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bool hdmi_phy_auto_reset_tmds_detected;
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/* Reset PHY automatically when TMDS clock passes 21 MHz.
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* Sets PHY_AUTO_RST3 in register PHY_CTL2.
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* Default: false
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*/
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bool hdmi_phy_auto_reset_tmds_in_range;
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/* Reset PHY automatically when TMDS clock is detected.
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* Sets PHY_AUTO_RST4 in register PHY_CTL2.
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* Default: false
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*/
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bool hdmi_phy_auto_reset_tmds_valid;
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/* Reset HDMI PHY automatically when hsync period is out of range.
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* Sets H_PI_RST in register HV_RST.
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* Default: false
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*/
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bool hdmi_phy_auto_reset_hsync_out_of_range;
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/* Reset HDMI PHY automatically when vsync period is out of range.
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* Sets V_PI_RST in register HV_RST.
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* Default: false
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*/
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bool hdmi_phy_auto_reset_vsync_out_of_range;
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};
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/* custom controls */
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/* Audio sample rate in Hz */
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#define TC358743_CID_AUDIO_SAMPLING_RATE (V4L2_CID_USER_TC358743_BASE + 0)
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/* Audio present status */
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#define TC358743_CID_AUDIO_PRESENT (V4L2_CID_USER_TC358743_BASE + 1)
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#endif
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@@ -174,6 +174,10 @@ enum v4l2_colorfx {
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* We reserve 16 controls for this driver. */
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#define V4L2_CID_USER_ADV7180_BASE (V4L2_CID_USER_BASE + 0x1070)
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/* The base for the tc358743 driver controls.
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* We reserve 16 controls for this driver. */
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#define V4L2_CID_USER_TC358743_BASE (V4L2_CID_USER_BASE + 0x1080)
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/* MPEG-class control IDs */
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/* The MPEG controls are applicable to all codec controls
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* and the 'MPEG' part of the define is historical */
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