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Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC updates from Olof Johansson: "This contains the bulk of new SoC development for this merge window. Two new platforms have been added, the sunxi platforms (Allwinner A1x SoCs) by Maxime Ripard, and a generic Broadcom platform for a new series of ARMv7 platforms from them, where the hope is that we can keep the platform code generic enough to have them all share one mach directory. The new Broadcom platform is contributed by Christian Daudt. Highbank has grown support for Calxeda's next generation of hardware, ECX-2000. clps711x has seen a lot of cleanup from Alexander Shiyan, and he's also taken on maintainership of the platform. Beyond this there has been a bunch of work from a number of people on converting more platforms to IRQ domains, pinctrl conversion, cleanup and general feature enablement across most of the active platforms." Fix up trivial conflicts as per Olof. * tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (174 commits) mfd: vexpress-sysreg: Remove LEDs code irqchip: irq-sunxi: Add terminating entry for sunxi_irq_dt_ids clocksource: sunxi_timer: Add terminating entry for sunxi_timer_dt_ids irq: versatile: delete dangling variable ARM: sunxi: add missing include for mdelay() ARM: EXYNOS: Avoid early use of of_machine_is_compatible() ARM: dts: add node for PL330 MDMA1 controller for exynos4 ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412 ARM: EXYNOS: add UART3 to DEBUG_LL ports ARM: S3C24XX: Add clkdev entry for camif-upll clock ARM: SAMSUNG: Add s3c24xx/s3c64xx CAMIF GPIO setup helpers ARM: sunxi: Add missing sun4i.dtsi file pinctrl: samsung: Do not initialise statics to 0 ARM i.MX6: remove gate_mask from pllv3 ARM i.MX6: Fix ethernet PLL clocks ARM i.MX6: rename PLLs according to datasheet ARM i.MX6: Add pwm support ARM i.MX51: Add pwm support ARM i.MX53: Add pwm support ARM: mx5: Replace clk_register_clkdev with clock DT lookup ...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,19 @@
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ARM Allwinner SoCs
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||||
==================
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This document lists all the ARM Allwinner SoCs that are currently
|
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supported in mainline by the Linux kernel. This document will also
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provide links to documentation and or datasheet for these SoCs.
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SunXi family
|
||||
------------
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Flavors:
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Allwinner A10 (sun4i)
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Datasheet : http://dl.linux-sunxi.org/A10/A10%20Datasheet%20-%20v1.21%20%282012-04-06%29.pdf
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Allwinner A13 (sun5i)
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Datasheet : http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf
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Core: Cortex A8
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Linux kernel mach directory: arch/arm/mach-sunxi
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@@ -0,0 +1,9 @@
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Broadcom BCM11351 device tree bindings
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-------------------------------------------
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Boards with the bcm281xx SoC family (which includes bcm11130, bcm11140,
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bcm11351, bcm28145, bcm28155 SoCs) shall have the following properties:
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Required root node property:
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compatible = "bcm,bcm11351";
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@@ -1,8 +1,15 @@
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Calxeda Highbank Platforms Device Tree Bindings
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Calxeda Platforms Device Tree Bindings
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-----------------------------------------------
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Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following
|
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properties.
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Boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC shall have the
|
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following properties.
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|
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Required root node properties:
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- compatible = "calxeda,highbank";
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Boards with Calxeda Cortex-A15 based ECX-2000 SOC shall have the following
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properties.
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Required root node properties:
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- compatible = "calxeda,ecx-2000";
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@@ -0,0 +1,50 @@
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ARM Versatile Express system registers
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--------------------------------------
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|
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This is a system control registers block, providing multiple low level
|
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platform functions like board detection and identification, software
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interrupt generation, MMC and NOR Flash control etc.
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|
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Required node properties:
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- compatible value : = "arm,vexpress,sysreg";
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- reg : physical base address and the size of the registers window
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- gpio-controller : specifies that the node is a GPIO controller
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- #gpio-cells : size of the GPIO specifier, should be 2:
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- first cell is the pseudo-GPIO line number:
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0 - MMC CARDIN
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1 - MMC WPROT
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2 - NOR FLASH WPn
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- second cell can take standard GPIO flags (currently ignored).
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Example:
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v2m_sysreg: sysreg@10000000 {
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compatible = "arm,vexpress-sysreg";
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reg = <0x10000000 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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This block also can also act a bridge to the platform's configuration
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bus via "system control" interface, addressing devices with site number,
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position in the board stack, config controller, function and device
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numbers - see motherboard's TRM for more details.
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|
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The node describing a config device must refer to the sysreg node via
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"arm,vexpress,config-bridge" phandle (can be also defined in the node's
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parent) and relies on the board topology properties - see main vexpress
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node documentation for more details. It must must also define the
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following property:
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- arm,vexpress-sysreg,func : must contain two cells:
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- first cell defines function number (eg. 1 for clock generator,
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2 for voltage regulators etc.)
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- device number (eg. osc 0, osc 1 etc.)
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|
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Example:
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mcc {
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arm,vexpress,config-bridge = <&v2m_sysreg>;
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osc@0 {
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 0>;
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};
|
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};
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@@ -11,6 +11,10 @@ the motherboard file using a /include/ directive. As the motherboard
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can be initialized in one of two different configurations ("memory
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maps"), care must be taken to include the correct one.
|
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|
||||
|
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Root node
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---------
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|
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Required properties in the root node:
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- compatible value:
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compatible = "arm,vexpress,<model>", "arm,vexpress";
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@@ -45,6 +49,10 @@ Optional properties in the root node:
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- Coretile Express A9x4 (V2P-CA9) HBI-0225:
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arm,hbi = <0x225>;
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|
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CPU nodes
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---------
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||||
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Top-level standard "cpus" node is required. It must contain a node
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with device_type = "cpu" property for every available core, eg.:
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|
||||
@@ -59,6 +67,52 @@ with device_type = "cpu" property for every available core, eg.:
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};
|
||||
};
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||||
|
||||
|
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Configuration infrastructure
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||||
----------------------------
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||||
|
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The platform has an elaborated configuration system, consisting of
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microcontrollers residing on the mother- and daughterboards known
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as Motherboard/Daughterboard Configuration Controller (MCC and DCC).
|
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The controllers are responsible for the platform initialization
|
||||
(reset generation, flash programming, FPGA bitfiles loading etc.)
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but also control clock generators, voltage regulators, gather
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environmental data like temperature, power consumption etc. Even
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the video output switch (FPGA) is controlled that way.
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|
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Nodes describing devices controlled by this infrastructure should
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point at the bridge device node:
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- bridge phandle:
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arm,vexpress,config-bridge = <phandle>;
|
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This property can be also defined in a parent node (eg. for a DCC)
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and is effective for all children.
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|
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|
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Platform topology
|
||||
-----------------
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||||
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As Versatile Express can be configured in number of physically
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different setups, the device tree should describe platform topology.
|
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Root node and main motherboard node must define the following
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property, describing physical location of the children nodes:
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- site number:
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arm,vexpress,site = <number>;
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where 0 means motherboard, 1 or 2 are daugtherboard sites,
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0xf means "master" site (site containing main CPU tile)
|
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- when daughterboards are stacked on one site, their position
|
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in the stack be be described with:
|
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arm,vexpress,position = <number>;
|
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- when describing tiles consisting more than one DCC, its number
|
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can be described with:
|
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arm,vexpress,dcc = <number>;
|
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|
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Any of the numbers above defaults to zero if not defined in
|
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the node or any of its parent.
|
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|
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|
||||
Motherboard
|
||||
-----------
|
||||
|
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The motherboard description file provides a single "motherboard" node
|
||||
using 2 address cells corresponding to the Static Memory Bus used
|
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between the motherboard and the tile. The first cell defines the Chip
|
||||
@@ -87,22 +141,30 @@ can be used to obtain required phandle in the tile's "aliases" node:
|
||||
- SP804 timers:
|
||||
v2m_timer01 and v2m_timer23
|
||||
|
||||
Current Linux implementation requires a "arm,v2m_timer" alias
|
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pointing at one of the motherboard's SP804 timers, if it is to be
|
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used as the system timer. This alias should be defined in the
|
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motherboard files.
|
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The tile description should define a "smb" node, describing the
|
||||
Static Memory Bus between the tile and motherboard. It must define
|
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the following properties:
|
||||
- "simple-bus" compatible value (to ensure creation of the children)
|
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compatible = "simple-bus";
|
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- mapping of the SMB CS/offset addresses into main address space:
|
||||
#address-cells = <2>;
|
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#size-cells = <1>;
|
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ranges = <...>;
|
||||
- interrupts mapping:
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
interrupt-map = <...>;
|
||||
|
||||
The tile description must define "ranges", "interrupt-map-mask" and
|
||||
"interrupt-map" properties to translate the motherboard's address
|
||||
and interrupt space into one used by the tile's processor.
|
||||
|
||||
Abbreviated example:
|
||||
Example of a VE tile description (simplified)
|
||||
---------------------------------------------
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "V2P-CA5s";
|
||||
arm,hbi = <0x225>;
|
||||
arm,vexpress,site = <0xf>;
|
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compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress";
|
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interrupt-parent = <&gic>;
|
||||
#address-cells = <1>;
|
||||
@@ -134,13 +196,29 @@ Abbreviated example:
|
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<0x2c000100 0x100>;
|
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};
|
||||
|
||||
motherboard {
|
||||
dcc {
|
||||
compatible = "simple-bus";
|
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arm,vexpress,config-bridge = <&v2m_sysreg>;
|
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|
||||
osc@0 {
|
||||
compatible = "arm,vexpress-osc";
|
||||
};
|
||||
};
|
||||
|
||||
smb {
|
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compatible = "simple-bus";
|
||||
|
||||
#address-cells = <2>;
|
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#size-cells = <1>;
|
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/* CS0 is visible at 0x08000000 */
|
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ranges = <0 0 0x08000000 0x04000000>;
|
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|
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#interrupt-cells = <1>;
|
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interrupt-map-mask = <0 0 63>;
|
||||
/* Active high IRQ 0 is connected to GIC's SPI0 */
|
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interrupt-map = <0 0 0 &gic 0 0 4>;
|
||||
|
||||
/include/ "vexpress-v2m-rs1.dtsi"
|
||||
};
|
||||
};
|
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|
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/include/ "vexpress-v2m-rs1.dtsi"
|
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|
||||
@@ -0,0 +1,191 @@
|
||||
* Clock bindings for Freescale i.MX5
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,<soc>-ccm" , where <soc> can be imx51 or imx53
|
||||
- reg: Address and length of the register set
|
||||
- interrupts: Should contain CCM interrupt
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX5
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
---------------------------
|
||||
dummy 0
|
||||
ckil 1
|
||||
osc 2
|
||||
ckih1 3
|
||||
ckih2 4
|
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ahb 5
|
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ipg 6
|
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axi_a 7
|
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axi_b 8
|
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uart_pred 9
|
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uart_root 10
|
||||
esdhc_a_pred 11
|
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esdhc_b_pred 12
|
||||
esdhc_c_s 13
|
||||
esdhc_d_s 14
|
||||
emi_sel 15
|
||||
emi_slow_podf 16
|
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nfc_podf 17
|
||||
ecspi_pred 18
|
||||
ecspi_podf 19
|
||||
usboh3_pred 20
|
||||
usboh3_podf 21
|
||||
usb_phy_pred 22
|
||||
usb_phy_podf 23
|
||||
cpu_podf 24
|
||||
di_pred 25
|
||||
tve_di 26
|
||||
tve_s 27
|
||||
uart1_ipg_gate 28
|
||||
uart1_per_gate 29
|
||||
uart2_ipg_gate 30
|
||||
uart2_per_gate 31
|
||||
uart3_ipg_gate 32
|
||||
uart3_per_gate 33
|
||||
i2c1_gate 34
|
||||
i2c2_gate 35
|
||||
gpt_ipg_gate 36
|
||||
pwm1_ipg_gate 37
|
||||
pwm1_hf_gate 38
|
||||
pwm2_ipg_gate 39
|
||||
pwm2_hf_gate 40
|
||||
gpt_hf_gate 41
|
||||
fec_gate 42
|
||||
usboh3_per_gate 43
|
||||
esdhc1_ipg_gate 44
|
||||
esdhc2_ipg_gate 45
|
||||
esdhc3_ipg_gate 46
|
||||
esdhc4_ipg_gate 47
|
||||
ssi1_ipg_gate 48
|
||||
ssi2_ipg_gate 49
|
||||
ssi3_ipg_gate 50
|
||||
ecspi1_ipg_gate 51
|
||||
ecspi1_per_gate 52
|
||||
ecspi2_ipg_gate 53
|
||||
ecspi2_per_gate 54
|
||||
cspi_ipg_gate 55
|
||||
sdma_gate 56
|
||||
emi_slow_gate 57
|
||||
ipu_s 58
|
||||
ipu_gate 59
|
||||
nfc_gate 60
|
||||
ipu_di1_gate 61
|
||||
vpu_s 62
|
||||
vpu_gate 63
|
||||
vpu_reference_gate 64
|
||||
uart4_ipg_gate 65
|
||||
uart4_per_gate 66
|
||||
uart5_ipg_gate 67
|
||||
uart5_per_gate 68
|
||||
tve_gate 69
|
||||
tve_pred 70
|
||||
esdhc1_per_gate 71
|
||||
esdhc2_per_gate 72
|
||||
esdhc3_per_gate 73
|
||||
esdhc4_per_gate 74
|
||||
usb_phy_gate 75
|
||||
hsi2c_gate 76
|
||||
mipi_hsc1_gate 77
|
||||
mipi_hsc2_gate 78
|
||||
mipi_esc_gate 79
|
||||
mipi_hsp_gate 80
|
||||
ldb_di1_div_3_5 81
|
||||
ldb_di1_div 82
|
||||
ldb_di0_div_3_5 83
|
||||
ldb_di0_div 84
|
||||
ldb_di1_gate 85
|
||||
can2_serial_gate 86
|
||||
can2_ipg_gate 87
|
||||
i2c3_gate 88
|
||||
lp_apm 89
|
||||
periph_apm 90
|
||||
main_bus 91
|
||||
ahb_max 92
|
||||
aips_tz1 93
|
||||
aips_tz2 94
|
||||
tmax1 95
|
||||
tmax2 96
|
||||
tmax3 97
|
||||
spba 98
|
||||
uart_sel 99
|
||||
esdhc_a_sel 100
|
||||
esdhc_b_sel 101
|
||||
esdhc_a_podf 102
|
||||
esdhc_b_podf 103
|
||||
ecspi_sel 104
|
||||
usboh3_sel 105
|
||||
usb_phy_sel 106
|
||||
iim_gate 107
|
||||
usboh3_gate 108
|
||||
emi_fast_gate 109
|
||||
ipu_di0_gate 110
|
||||
gpc_dvfs 111
|
||||
pll1_sw 112
|
||||
pll2_sw 113
|
||||
pll3_sw 114
|
||||
ipu_di0_sel 115
|
||||
ipu_di1_sel 116
|
||||
tve_ext_sel 117
|
||||
mx51_mipi 118
|
||||
pll4_sw 119
|
||||
ldb_di1_sel 120
|
||||
di_pll4_podf 121
|
||||
ldb_di0_sel 122
|
||||
ldb_di0_gate 123
|
||||
usb_phy1_gate 124
|
||||
usb_phy2_gate 125
|
||||
per_lp_apm 126
|
||||
per_pred1 127
|
||||
per_pred2 128
|
||||
per_podf 129
|
||||
per_root 130
|
||||
ssi_apm 131
|
||||
ssi1_root_sel 132
|
||||
ssi2_root_sel 133
|
||||
ssi3_root_sel 134
|
||||
ssi_ext1_sel 135
|
||||
ssi_ext2_sel 136
|
||||
ssi_ext1_com_sel 137
|
||||
ssi_ext2_com_sel 138
|
||||
ssi1_root_pred 139
|
||||
ssi1_root_podf 140
|
||||
ssi2_root_pred 141
|
||||
ssi2_root_podf 142
|
||||
ssi_ext1_pred 143
|
||||
ssi_ext1_podf 144
|
||||
ssi_ext2_pred 145
|
||||
ssi_ext2_podf 146
|
||||
ssi1_root_gate 147
|
||||
ssi2_root_gate 148
|
||||
ssi3_root_gate 149
|
||||
ssi_ext1_gate 150
|
||||
ssi_ext2_gate 151
|
||||
epit1_ipg_gate 152
|
||||
epit1_hf_gate 153
|
||||
epit2_ipg_gate 154
|
||||
epit2_hf_gate 155
|
||||
can_sel 156
|
||||
can1_serial_gate 157
|
||||
can1_ipg_gate 158
|
||||
|
||||
Examples (for mx53):
|
||||
|
||||
clks: ccm@53fd4000{
|
||||
compatible = "fsl,imx53-ccm";
|
||||
reg = <0x53fd4000 0x4000>;
|
||||
interrupts = <0 71 0x04 0 72 0x04>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
can1: can@53fc8000 {
|
||||
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
|
||||
reg = <0x53fc8000 0x4000>;
|
||||
interrupts = <82>;
|
||||
clocks = <&clks 158>, <&clks 157>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -187,9 +187,9 @@ clocks and IDs.
|
||||
pll3_usb_otg 172
|
||||
pll4_audio 173
|
||||
pll5_video 174
|
||||
pll6_mlb 175
|
||||
pll8_mlb 175
|
||||
pll7_usb_host 176
|
||||
pll8_enet 177
|
||||
pll6_enet 177
|
||||
ssi1_ipg 178
|
||||
ssi2_ipg 179
|
||||
ssi3_ipg 180
|
||||
@@ -198,6 +198,11 @@ clocks and IDs.
|
||||
usbphy2 183
|
||||
ldb_di0_div_3_5 184
|
||||
ldb_di1_div_3_5 185
|
||||
sata_ref 186
|
||||
sata_ref_100m 187
|
||||
pcie_ref 188
|
||||
pcie_ref_125m 189
|
||||
enet_ref 190
|
||||
|
||||
Examples:
|
||||
|
||||
|
||||
@@ -0,0 +1,104 @@
|
||||
Allwinner Sunxi Interrupt Controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "allwinner,sunxi-ic"
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt source. The value shall be 1.
|
||||
|
||||
The interrupt sources are as follows:
|
||||
|
||||
0: ENMI
|
||||
1: UART0
|
||||
2: UART1
|
||||
3: UART2
|
||||
4: UART3
|
||||
5: IR0
|
||||
6: IR1
|
||||
7: I2C0
|
||||
8: I2C1
|
||||
9: I2C2
|
||||
10: SPI0
|
||||
11: SPI1
|
||||
12: SPI2
|
||||
13: SPDIF
|
||||
14: AC97
|
||||
15: TS
|
||||
16: I2S
|
||||
17: UART4
|
||||
18: UART5
|
||||
19: UART6
|
||||
20: UART7
|
||||
21: KEYPAD
|
||||
22: TIMER0
|
||||
23: TIMER1
|
||||
24: TIMER2
|
||||
25: TIMER3
|
||||
26: CAN
|
||||
27: DMA
|
||||
28: PIO
|
||||
29: TOUCH_PANEL
|
||||
30: AUDIO_CODEC
|
||||
31: LRADC
|
||||
32: SDMC0
|
||||
33: SDMC1
|
||||
34: SDMC2
|
||||
35: SDMC3
|
||||
36: MEMSTICK
|
||||
37: NAND
|
||||
38: USB0
|
||||
39: USB1
|
||||
40: USB2
|
||||
41: SCR
|
||||
42: CSI0
|
||||
43: CSI1
|
||||
44: LCDCTRL0
|
||||
45: LCDCTRL1
|
||||
46: MP
|
||||
47: DEFEBE0
|
||||
48: DEFEBE1
|
||||
49: PMU
|
||||
50: SPI3
|
||||
51: TZASC
|
||||
52: PATA
|
||||
53: VE
|
||||
54: SS
|
||||
55: EMAC
|
||||
56: SATA
|
||||
57: GPS
|
||||
58: HDMI
|
||||
59: TVE
|
||||
60: ACE
|
||||
61: TVD
|
||||
62: PS2_0
|
||||
63: PS2_1
|
||||
64: USB3
|
||||
65: USB4
|
||||
66: PLE_PFM
|
||||
67: TIMER4
|
||||
68: TIMER5
|
||||
69: GPU_GP
|
||||
70: GPU_GPMMU
|
||||
71: GPU_PP0
|
||||
72: GPU_PPMMU0
|
||||
73: GPU_PMU
|
||||
74: GPU_RSV0
|
||||
75: GPU_RSV1
|
||||
76: GPU_RSV2
|
||||
77: GPU_RSV3
|
||||
78: GPU_RSV4
|
||||
79: GPU_RSV5
|
||||
80: GPU_RSV6
|
||||
82: SYNC_TIMER0
|
||||
83: SYNC_TIMER1
|
||||
|
||||
Example:
|
||||
|
||||
intc: interrupt-controller {
|
||||
compatible = "allwinner,sunxi-ic";
|
||||
reg = <0x01c20400 0x400>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
@@ -8,13 +8,20 @@ on-chip controllers onto these pads.
|
||||
Required Properties:
|
||||
- compatible: should be one of the following.
|
||||
- "samsung,pinctrl-exynos4210": for Exynos4210 compatible pin-controller.
|
||||
- "samsung,pinctrl-exynos4x12": for Exynos4x12 compatible pin-controller.
|
||||
- "samsung,pinctrl-exynos5250": for Exynos5250 compatible pin-controller.
|
||||
|
||||
- reg: Base address of the pin controller hardware module and length of
|
||||
the address space it occupies.
|
||||
|
||||
- interrupts: interrupt specifier for the controller. The format and value of
|
||||
the interrupt specifier depends on the interrupt parent for the controller.
|
||||
- Pin banks as child nodes: Pin banks of the controller are represented by child
|
||||
nodes of the controller node. Bank name is taken from name of the node. Each
|
||||
bank node must contain following properties:
|
||||
|
||||
- gpio-controller: identifies the node as a gpio controller and pin bank.
|
||||
- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
|
||||
binding is used, the amount of cells must be specified as 2. See generic
|
||||
GPIO binding documentation for description of particular cells.
|
||||
|
||||
- Pin mux/config groups as child nodes: The pin mux (selecting pin function
|
||||
mode) and pin config (pull up/down, driver strength) settings are represented
|
||||
@@ -72,16 +79,24 @@ used as system wakeup events.
|
||||
A. External GPIO Interrupts: For supporting external gpio interrupts, the
|
||||
following properties should be specified in the pin-controller device node.
|
||||
|
||||
- interrupt-controller: identifies the controller node as interrupt-parent.
|
||||
- #interrupt-cells: the value of this property should be 2.
|
||||
- First Cell: represents the external gpio interrupt number local to the
|
||||
external gpio interrupt space of the controller.
|
||||
- Second Cell: flags to identify the type of the interrupt
|
||||
- 1 = rising edge triggered
|
||||
- 2 = falling edge triggered
|
||||
- 3 = rising and falling edge triggered
|
||||
- 4 = high level triggered
|
||||
- 8 = low level triggered
|
||||
- interrupt-parent: phandle of the interrupt parent to which the external
|
||||
GPIO interrupts are forwarded to.
|
||||
- interrupts: interrupt specifier for the controller. The format and value of
|
||||
the interrupt specifier depends on the interrupt parent for the controller.
|
||||
|
||||
In addition, following properties must be present in node of every bank
|
||||
of pins supporting GPIO interrupts:
|
||||
|
||||
- interrupt-controller: identifies the controller node as interrupt-parent.
|
||||
- #interrupt-cells: the value of this property should be 2.
|
||||
- First Cell: represents the external gpio interrupt number local to the
|
||||
external gpio interrupt space of the controller.
|
||||
- Second Cell: flags to identify the type of the interrupt
|
||||
- 1 = rising edge triggered
|
||||
- 2 = falling edge triggered
|
||||
- 3 = rising and falling edge triggered
|
||||
- 4 = high level triggered
|
||||
- 8 = low level triggered
|
||||
|
||||
B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
|
||||
child node representing the external wakeup interrupt controller should be
|
||||
@@ -94,6 +109,11 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
|
||||
found on Samsung Exynos4210 SoC.
|
||||
- interrupt-parent: phandle of the interrupt parent to which the external
|
||||
wakeup interrupts are forwarded to.
|
||||
- interrupts: interrupt used by multiplexed wakeup interrupts.
|
||||
|
||||
In addition, following properties must be present in node of every bank
|
||||
of pins supporting wake-up interrupts:
|
||||
|
||||
- interrupt-controller: identifies the node as interrupt-parent.
|
||||
- #interrupt-cells: the value of this property should be 2
|
||||
- First Cell: represents the external wakeup interrupt number local to
|
||||
@@ -105,11 +125,63 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
|
||||
- 4 = high level triggered
|
||||
- 8 = low level triggered
|
||||
|
||||
Node of every bank of pins supporting direct wake-up interrupts (without
|
||||
multiplexing) must contain following properties:
|
||||
|
||||
- interrupt-parent: phandle of the interrupt parent to which the external
|
||||
wakeup interrupts are forwarded to.
|
||||
- interrupts: interrupts of the interrupt parent which are used for external
|
||||
wakeup interrupts from pins of the bank, must contain interrupts for all
|
||||
pins of the bank.
|
||||
|
||||
Aliases:
|
||||
|
||||
All the pin controller nodes should be represented in the aliases node using
|
||||
the following format 'pinctrl{n}' where n is a unique number for the alias.
|
||||
|
||||
Example: A pin-controller node with pin banks:
|
||||
|
||||
pinctrl_0: pinctrl@11400000 {
|
||||
compatible = "samsung,pinctrl-exynos4210";
|
||||
reg = <0x11400000 0x1000>;
|
||||
interrupts = <0 47 0>;
|
||||
|
||||
/* ... */
|
||||
|
||||
/* Pin bank without external interrupts */
|
||||
gpy0: gpy0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
/* ... */
|
||||
|
||||
/* Pin bank with external GPIO or muxed wake-up interrupts */
|
||||
gpj0: gpj0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
/* ... */
|
||||
|
||||
/* Pin bank with external direct wake-up interrupts */
|
||||
gpx0: gpx0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
|
||||
<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
/* ... */
|
||||
};
|
||||
|
||||
Example 1: A pin-controller node with pin groups.
|
||||
|
||||
pinctrl_0: pinctrl@11400000 {
|
||||
@@ -117,6 +189,8 @@ Example 1: A pin-controller node with pin groups.
|
||||
reg = <0x11400000 0x1000>;
|
||||
interrupts = <0 47 0>;
|
||||
|
||||
/* ... */
|
||||
|
||||
uart0_data: uart0-data {
|
||||
samsung,pins = "gpa0-0", "gpa0-1";
|
||||
samsung,pin-function = <2>;
|
||||
@@ -158,20 +232,14 @@ Example 2: A pin-controller node with external wakeup interrupt controller node.
|
||||
pinctrl_1: pinctrl@11000000 {
|
||||
compatible = "samsung,pinctrl-exynos4210";
|
||||
reg = <0x11000000 0x1000>;
|
||||
interrupts = <0 46 0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0 46 0>
|
||||
|
||||
wakup_eint: wakeup-interrupt-controller {
|
||||
/* ... */
|
||||
|
||||
wakeup-interrupt-controller {
|
||||
compatible = "samsung,exynos4210-wakeup-eint";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
|
||||
<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
|
||||
<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
|
||||
<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
|
||||
<0 32 0>;
|
||||
interrupts = <0 32 0>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -190,7 +258,8 @@ Example 4: Set up the default pin state for uart controller.
|
||||
|
||||
static int s3c24xx_serial_probe(struct platform_device *pdev) {
|
||||
struct pinctrl *pinctrl;
|
||||
...
|
||||
...
|
||||
|
||||
/* ... */
|
||||
|
||||
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
|
||||
}
|
||||
|
||||
@@ -0,0 +1,17 @@
|
||||
Allwinner A1X SoCs Timer Controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "allwinner,sunxi-timer"
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
- interrupts : The interrupt of the first timer
|
||||
- clocks: phandle to the source clock (usually a 24 MHz fixed clock)
|
||||
|
||||
Example:
|
||||
|
||||
timer {
|
||||
compatible = "allwinner,sunxi-timer";
|
||||
reg = <0x01c20c00 0x400>;
|
||||
interrupts = <22>;
|
||||
clocks = <&osc>;
|
||||
};
|
||||
@@ -0,0 +1,13 @@
|
||||
BCM2835 Watchdog timer
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "brcm,bcm2835-pm-wdt"
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
|
||||
Example:
|
||||
|
||||
watchdog {
|
||||
compatible = "brcm,bcm2835-pm-wdt";
|
||||
reg = <0x7e100000 0x28>;
|
||||
};
|
||||
@@ -0,0 +1,13 @@
|
||||
Allwinner sunXi Watchdog timer
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "allwinner,sunxi-wdt"
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
|
||||
Example:
|
||||
|
||||
wdt: watchdog@01c20c90 {
|
||||
compatible = "allwinner,sunxi-wdt";
|
||||
reg = <0x01c20c90 0x10>;
|
||||
};
|
||||
+12
@@ -685,6 +685,12 @@ M: Lennert Buytenhek <kernel@wantstofly.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
|
||||
ARM/Allwinner A1X SoC support
|
||||
M: Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/mach-sunxi/
|
||||
|
||||
ARM/ATMEL AT91RM9200 AND AT91SAM ARM ARCHITECTURES
|
||||
M: Andrew Victor <linux@maxim.org.za>
|
||||
M: Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
@@ -707,6 +713,12 @@ S: Maintained
|
||||
F: arch/arm/mach-cns3xxx/
|
||||
T: git git://git.infradead.org/users/cbou/linux-cns3xxx.git
|
||||
|
||||
ARM/CIRRUS LOGIC CLPS711X ARM ARCHITECTURE
|
||||
M: Alexander Shiyan <shc_work@mail.ru>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Odd Fixes
|
||||
F: arch/arm/mach-clps711x/
|
||||
|
||||
ARM/CIRRUS LOGIC EP93XX ARM ARCHITECTURE
|
||||
M: Hartley Sweeten <hsweeten@visionengravers.com>
|
||||
M: Ryan Mallon <rmallon@gmail.com>
|
||||
|
||||
+14
-3
@@ -286,8 +286,8 @@ config ARCH_INTEGRATOR
|
||||
select MULTI_IRQ_HANDLER
|
||||
select NEED_MACH_MEMORY_H
|
||||
select PLAT_VERSATILE
|
||||
select PLAT_VERSATILE_FPGA_IRQ
|
||||
select SPARSE_IRQ
|
||||
select VERSATILE_FPGA_IRQ
|
||||
help
|
||||
Support for ARM's Integrator platform.
|
||||
|
||||
@@ -320,7 +320,7 @@ config ARCH_VERSATILE
|
||||
select PLAT_VERSATILE
|
||||
select PLAT_VERSATILE_CLCD
|
||||
select PLAT_VERSATILE_CLOCK
|
||||
select PLAT_VERSATILE_FPGA_IRQ
|
||||
select VERSATILE_FPGA_IRQ
|
||||
help
|
||||
This enables support for ARM Ltd Versatile board.
|
||||
|
||||
@@ -340,7 +340,7 @@ config ARCH_AT91
|
||||
|
||||
config ARCH_BCM2835
|
||||
bool "Broadcom BCM2835 family"
|
||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARM_AMBA
|
||||
select ARM_ERRATA_411920
|
||||
select ARM_TIMER_SP804
|
||||
@@ -348,7 +348,10 @@ config ARCH_BCM2835
|
||||
select COMMON_CLK
|
||||
select CPU_V6
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select GENERIC_GPIO
|
||||
select MULTI_IRQ_HANDLER
|
||||
select PINCTRL
|
||||
select PINCTRL_BCM2835
|
||||
select SPARSE_IRQ
|
||||
select USE_OF
|
||||
help
|
||||
@@ -370,10 +373,14 @@ config ARCH_CLPS711X
|
||||
bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
select AUTO_ZRELADDR
|
||||
select CLKDEV_LOOKUP
|
||||
select COMMON_CLK
|
||||
select CPU_ARM720T
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select MULTI_IRQ_HANDLER
|
||||
select NEED_MACH_MEMORY_H
|
||||
select SPARSE_IRQ
|
||||
help
|
||||
Support for Cirrus Logic 711x/721x/731x based boards.
|
||||
|
||||
@@ -1015,6 +1022,8 @@ source "arch/arm/mach-mvebu/Kconfig"
|
||||
|
||||
source "arch/arm/mach-at91/Kconfig"
|
||||
|
||||
source "arch/arm/mach-bcm/Kconfig"
|
||||
|
||||
source "arch/arm/mach-clps711x/Kconfig"
|
||||
|
||||
source "arch/arm/mach-cns3xxx/Kconfig"
|
||||
@@ -1106,6 +1115,8 @@ source "arch/arm/mach-exynos/Kconfig"
|
||||
|
||||
source "arch/arm/mach-shmobile/Kconfig"
|
||||
|
||||
source "arch/arm/mach-sunxi/Kconfig"
|
||||
|
||||
source "arch/arm/mach-prima2/Kconfig"
|
||||
|
||||
source "arch/arm/mach-tegra/Kconfig"
|
||||
|
||||
@@ -338,6 +338,17 @@ choice
|
||||
The uncompressor code port configuration is now handled
|
||||
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
||||
|
||||
config DEBUG_S3C_UART3
|
||||
depends on PLAT_SAMSUNG && ARCH_EXYNOS
|
||||
bool "Use S3C UART 3 for low-level debug"
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to UART 3. The port must have been initialised
|
||||
by the boot-loader before use.
|
||||
|
||||
The uncompressor code port configuration is now handled
|
||||
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
||||
|
||||
config DEBUG_SOCFPGA_UART
|
||||
depends on ARCH_SOCFPGA
|
||||
bool "Use SOCFPGA UART for low-level debug"
|
||||
@@ -345,6 +356,20 @@ choice
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on SOCFPGA based platforms.
|
||||
|
||||
config DEBUG_SUNXI_UART0
|
||||
bool "Kernel low-level debugging messages via sunXi UART0"
|
||||
depends on ARCH_SUNXI
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on Allwinner A1X based platforms on the UART0.
|
||||
|
||||
config DEBUG_SUNXI_UART1
|
||||
bool "Kernel low-level debugging messages via sunXi UART1"
|
||||
depends on ARCH_SUNXI
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on Allwinner A1X based platforms on the UART1.
|
||||
|
||||
config DEBUG_VEXPRESS_UART0_DETECT
|
||||
bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
|
||||
depends on ARCH_VEXPRESS && CPU_CP15_MMU
|
||||
@@ -424,6 +449,7 @@ config DEBUG_LL_INCLUDE
|
||||
default "debug/mvebu.S" if DEBUG_MVEBU_UART
|
||||
default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
|
||||
default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
|
||||
default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
|
||||
default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
|
||||
DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
|
||||
default "mach/debug-macro.S"
|
||||
|
||||
@@ -138,6 +138,7 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
|
||||
# Machine directory name. This list is sorted alphanumerically
|
||||
# by CONFIG_* macro name.
|
||||
machine-$(CONFIG_ARCH_AT91) += at91
|
||||
machine-$(CONFIG_ARCH_BCM) += bcm
|
||||
machine-$(CONFIG_ARCH_BCM2835) += bcm2835
|
||||
machine-$(CONFIG_ARCH_CLPS711X) += clps711x
|
||||
machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
|
||||
@@ -194,6 +195,7 @@ machine-$(CONFIG_ARCH_SPEAR13XX) += spear13xx
|
||||
machine-$(CONFIG_ARCH_SPEAR3XX) += spear3xx
|
||||
machine-$(CONFIG_MACH_SPEAR600) += spear6xx
|
||||
machine-$(CONFIG_ARCH_ZYNQ) += zynq
|
||||
machine-$(CONFIG_ARCH_SUNXI) += sunxi
|
||||
|
||||
# Platform directory name. This list is sorted alphanumerically
|
||||
# by CONFIG_* macro name.
|
||||
|
||||
@@ -45,11 +45,6 @@ ifeq ($(CONFIG_ARCH_SHARK),y)
|
||||
OBJS += head-shark.o ofw-shark.o
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_P720T),y)
|
||||
# Borrow this code from SA1100
|
||||
OBJS += head-sa1100.o
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_SA1100),y)
|
||||
OBJS += head-sa1100.o
|
||||
endif
|
||||
|
||||
@@ -33,14 +33,17 @@ dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
|
||||
dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb
|
||||
dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
|
||||
dove-cubox.dtb \
|
||||
dove-dove-db.dtb
|
||||
dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
|
||||
exynos4210-smdkv310.dtb \
|
||||
exynos4210-trats.dtb \
|
||||
exynos5250-smdk5250.dtb
|
||||
dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb
|
||||
exynos5250-smdk5250.dtb \
|
||||
exynos5440-ssdk5440.dtb
|
||||
dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
|
||||
ecx-2000.dtb
|
||||
dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
|
||||
integratorcp.dtb
|
||||
dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
|
||||
@@ -102,6 +105,8 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
|
||||
spear310-evb.dtb \
|
||||
spear320-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_SUNXI) += sun4i-cubieboard.dtb \
|
||||
sun5i-olinuxino.dtb
|
||||
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
|
||||
tegra20-medcom-wide.dtb \
|
||||
tegra20-paz00.dtb \
|
||||
|
||||
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "bcm11351.dtsi"
|
||||
|
||||
/ {
|
||||
model = "BCM11351 BRT board";
|
||||
compatible = "bcm,bcm11351-brt", "bcm,bcm11351";
|
||||
|
||||
memory {
|
||||
reg = <0x80000000 0x40000000>; /* 1 GB */
|
||||
};
|
||||
|
||||
uart@3e000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
};
|
||||
@@ -0,0 +1,50 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
model = "BCM11351 SoC";
|
||||
compatible = "bcm,bcm11351";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200n8";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@3ff00100 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x3ff01000 0x1000>,
|
||||
<0x3ff00100 0x100>;
|
||||
};
|
||||
|
||||
uart@3e000000 {
|
||||
compatible = "bcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
|
||||
status = "disabled";
|
||||
reg = <0x3e000000 0x1000>;
|
||||
clock-frequency = <13000000>;
|
||||
interrupts = <0x0 67 0x4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
L2: l2-cache {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x3ff20000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user