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Staging: sep: Upstream revision 3 of the security processor kernel driver
Upstream revision 3 of the security processor kernel driver; now located in drivers/staging This revision adds an initial TODO file This driver no longer requires to have the firmware compiled in it with the CONFIG_EXTRA_FIRMWARE configuration option. Furthermore, we now have the right to distribute the firmware binaries. This is the Linux kernel driver for the Security Processor, which is a hardware device the provides cryptographic, secure storage, and key management services. Please be aware that this patch does not contain any encryption algorithm. It only transports data to and from user space applications to the security processor. Signed-off-by: Mark Allyn <mark.a.allyn@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Mark Allyn
committed by
Greg Kroah-Hartman
Greg Kroah-Hartman
parent
249c033c29
commit
cd1bb431d8
@@ -135,5 +135,7 @@ source "drivers/staging/hv/Kconfig"
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source "drivers/staging/vme/Kconfig"
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source "drivers/staging/sep/Kconfig"
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endif # !STAGING_EXCLUDE_BUILD
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endif # STAGING
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@@ -49,3 +49,4 @@ obj-$(CONFIG_USB_CPC) += cpc-usb/
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obj-$(CONFIG_FB_UDL) += udlfb/
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obj-$(CONFIG_HYPERV) += hv/
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obj-$(CONFIG_VME_BUS) += vme/
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obj-$(CONFIG_DX_SEP) += sep/
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@@ -0,0 +1,9 @@
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config DX_SEP
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tristate "Discretix SEP driver"
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depends on MRST
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default y
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help
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Discretix SEP driver
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If unsure say M. The compiled module will be
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called sep_driver.ko
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@@ -0,0 +1,3 @@
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EXTRA_CFLAGS += -DLITTLE__ENDIAN -DDX_CC5_SEP_PLAT -DCRYS_NO_EXT_IF_MODE_SUPPORT
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obj-$(CONFIG_DX_SEP) := sep_driver.o
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sep_driver-objs := sep_main_mod.o sep_ext_with_pci_driver.o
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@@ -0,0 +1,8 @@
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Todo's so far (from Alan Cox)
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- Fix firmware loading
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- Get firmware into firmware git tree
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- Review and tidy each algorithm function
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- Check whether it can be plugged into any of the kernel crypto API
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interfaces
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- Do something about the magic shared memory interface and replace it
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with something saner (in Linux terms)
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,305 @@
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/*
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*
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* sep_driver_config.h - Security Processor Driver configuration
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*
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* Copyright(c) 2009 Intel Corporation. All rights reserved.
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* Copyright(c) 2009 Discretix. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* CONTACTS:
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*
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* Mark Allyn mark.a.allyn@intel.com
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*
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* CHANGES:
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*
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* 2009.06.26 Initial publish
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*
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*/
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#ifndef __SEP_DRIVER_CONFIG_H__
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#define __SEP_DRIVER_CONFIG_H__
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/*--------------------------------------
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DRIVER CONFIGURATION FLAGS
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-------------------------------------*/
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/* if flag is on , then the driver is running in polling and
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not interrupt mode */
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#define SEP_DRIVER_POLLING_MODE 1
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/* flag which defines if the shared area address should be
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reconfiged (send to SEP anew) during init of the driver */
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#define SEP_DRIVER_RECONFIG_MESSAGE_AREA 0
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/* the mode for running on the ARM1172 Evaluation platform (flag is 1) */
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#define SEP_DRIVER_ARM_DEBUG_MODE 0
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/*-------------------------------------------
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INTERNAL DATA CONFIGURATION
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-------------------------------------------*/
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/* flag for the input array */
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#define SEP_DRIVER_IN_FLAG 0
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/* flag for output array */
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#define SEP_DRIVER_OUT_FLAG 1
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/* maximum number of entries in one LLI tables */
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#define SEP_DRIVER_ENTRIES_PER_TABLE_IN_SEP 8
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/*--------------------------------------------------------
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SHARED AREA memory total size is 36K
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it is divided is following:
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SHARED_MESSAGE_AREA 8K }
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}
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STATIC_POOL_AREA 4K } MAPPED AREA ( 24 K)
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}
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DATA_POOL_AREA 12K }
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SYNCHRONIC_DMA_TABLES_AREA 5K
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FLOW_DMA_TABLES_AREA 4K
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SYSTEM_MEMORY_AREA 3k
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SYSTEM_MEMORY total size is 3k
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it is divided as following:
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TIME_MEMORY_AREA 8B
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-----------------------------------------------------------*/
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/*
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the maximum length of the message - the rest of the message shared
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area will be dedicated to the dma lli tables
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*/
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#define SEP_DRIVER_MAX_MESSAGE_SIZE_IN_BYTES (8 * 1024)
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/* the size of the message shared area in pages */
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#define SEP_DRIVER_MESSAGE_SHARED_AREA_SIZE_IN_BYTES (8 * 1024)
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/* the size of the data pool static area in pages */
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#define SEP_DRIVER_STATIC_AREA_SIZE_IN_BYTES (4 * 1024)
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/* the size of the data pool shared area size in pages */
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#define SEP_DRIVER_DATA_POOL_SHARED_AREA_SIZE_IN_BYTES (12 * 1024)
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/* the size of the message shared area in pages */
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#define SEP_DRIVER_SYNCHRONIC_DMA_TABLES_AREA_SIZE_IN_BYTES (1024 * 5)
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/* the size of the data pool shared area size in pages */
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#define SEP_DRIVER_FLOW_DMA_TABLES_AREA_SIZE_IN_BYTES (1024 * 4)
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/* system data (time, caller id etc') pool */
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#define SEP_DRIVER_SYSTEM_DATA_MEMORY_SIZE_IN_BYTES 100
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/* area size that is mapped - we map the MESSAGE AREA, STATIC POOL and
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DATA POOL areas. area must be module 4k */
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#define SEP_DRIVER_MMMAP_AREA_SIZE (1024 * 24)
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/*-----------------------------------------------
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offsets of the areas starting from the shared area start address
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*/
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/* message area offset */
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#define SEP_DRIVER_MESSAGE_AREA_OFFSET_IN_BYTES 0
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/* static pool area offset */
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#define SEP_DRIVER_STATIC_AREA_OFFSET_IN_BYTES \
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(SEP_DRIVER_MESSAGE_SHARED_AREA_SIZE_IN_BYTES)
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/* data pool area offset */
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#define SEP_DRIVER_DATA_POOL_AREA_OFFSET_IN_BYTES \
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(SEP_DRIVER_STATIC_AREA_OFFSET_IN_BYTES + \
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SEP_DRIVER_STATIC_AREA_SIZE_IN_BYTES)
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/* synhronic dma tables area offset */
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#define SEP_DRIVER_SYNCHRONIC_DMA_TABLES_AREA_OFFSET_IN_BYTES \
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(SEP_DRIVER_DATA_POOL_AREA_OFFSET_IN_BYTES + \
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SEP_DRIVER_DATA_POOL_SHARED_AREA_SIZE_IN_BYTES)
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/* sep driver flow dma tables area offset */
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#define SEP_DRIVER_FLOW_DMA_TABLES_AREA_OFFSET_IN_BYTES \
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(SEP_DRIVER_SYNCHRONIC_DMA_TABLES_AREA_OFFSET_IN_BYTES + \
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SEP_DRIVER_SYNCHRONIC_DMA_TABLES_AREA_SIZE_IN_BYTES)
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/* system memory offset in bytes */
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#define SEP_DRIVER_SYSTEM_DATA_MEMORY_OFFSET_IN_BYTES \
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(SEP_DRIVER_FLOW_DMA_TABLES_AREA_OFFSET_IN_BYTES + \
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SEP_DRIVER_FLOW_DMA_TABLES_AREA_SIZE_IN_BYTES)
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/* offset of the time area */
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#define SEP_DRIVER_SYSTEM_TIME_MEMORY_OFFSET_IN_BYTES \
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(SEP_DRIVER_SYSTEM_DATA_MEMORY_OFFSET_IN_BYTES)
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/* start physical address of the SEP registers memory in HOST */
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#define SEP_IO_MEM_REGION_START_ADDRESS 0x80000000
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/* size of the SEP registers memory region in HOST (for now 100 registers) */
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#define SEP_IO_MEM_REGION_SIZE (2 * 0x100000)
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/* define the number of IRQ for SEP interrupts */
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#define SEP_DIRVER_IRQ_NUM 1
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/* maximum number of add buffers */
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#define SEP_MAX_NUM_ADD_BUFFERS 100
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/* number of flows */
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#define SEP_DRIVER_NUM_FLOWS 4
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/* maximum number of entries in flow table */
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#define SEP_DRIVER_MAX_FLOW_NUM_ENTRIES_IN_TABLE 25
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/* offset of the num entries in the block length entry of the LLI */
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#define SEP_NUM_ENTRIES_OFFSET_IN_BITS 24
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/* offset of the interrupt flag in the block length entry of the LLI */
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#define SEP_INT_FLAG_OFFSET_IN_BITS 31
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/* mask for extracting data size from LLI */
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#define SEP_TABLE_DATA_SIZE_MASK 0xFFFFFF
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/* mask for entries after being shifted left */
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#define SEP_NUM_ENTRIES_MASK 0x7F
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/* default flow id */
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#define SEP_FREE_FLOW_ID 0xFFFFFFFF
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/* temp flow id used during cretiong of new flow until receiving
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real flow id from sep */
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#define SEP_TEMP_FLOW_ID (SEP_DRIVER_NUM_FLOWS + 1)
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/* maximum add buffers message length in bytes */
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#define SEP_MAX_ADD_MESSAGE_LENGTH_IN_BYTES (7 * 4)
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/* maximum number of concurrent virtual buffers */
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#define SEP_MAX_VIRT_BUFFERS_CONCURRENT 100
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/* the token that defines the start of time address */
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#define SEP_TIME_VAL_TOKEN 0x12345678
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/* DEBUG LEVEL MASKS */
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#define SEP_DEBUG_LEVEL_BASIC 0x1
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#define SEP_DEBUG_LEVEL_REGISTERS 0x2
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#define SEP_DEBUG_LEVEL_EXTENDED 0x4
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/* FUNCTIONAL MACROS */
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/* debug macro without paramaters */
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#define DEBUG_PRINT_0(DEBUG_LEVEL , info) \
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do { \
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if (DEBUG_LEVEL & sepDebug) \
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printk(KERN_WARNING info); \
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} while (0)
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/* debug macro with 1 paramater */
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#define DEBUG_PRINT_1(DEBUG_LEVEL , info , param1) \
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do { \
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if (DEBUG_LEVEL & sepDebug) \
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printk(KERN_WARNING info, param1); \
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} while (0)
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/* debug macro with 2 paramaters */
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#define DEBUG_PRINT_2(DEBUG_LEVEL, info, param1, param2) \
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do { \
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if (DEBUG_LEVEL & sepDebug) \
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printk(KERN_WARNING info , param1, param2); \
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} while (0)
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/* debug macro with 3 paramaters */
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#define DEBUG_PRINT_3(DEBUG_LEVEL, info, param1, param2, param3) \
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do { \
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if (DEBUG_LEVEL & sepDebug) \
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printk(KERN_WARNING info , param1, param2 , param3); \
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} while (0)
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/* debug macro with 4 paramaters */
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#define DEBUG_PRINT_4(DEBUG_LEVEL, info, param1, param2, param3, param4) \
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do { \
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if (DEBUG_LEVEL & sepDebug) \
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printk(KERN_WARNING info, param1, param2, param3, param4); \
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} while (0)
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#if 0
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/* write register macro with option for debug print */
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#define SEP_WRITE_REGISTER(address, value) \
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do { \
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if (sepDebug & SEP_DEBUG_LEVEL_REGISTERS) \
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printk(KERN_WARNING "Write Register: address %lu value %lu\n", \
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(unsigned long)(address), (unsigned long)(value)); \
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writel((value), (void *)(address)); \
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} while (0)
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/* read register macro with option for debug print */
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#define SEP_READ_REGISTER(address , value) \
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do { \
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(value) = readl((void *)(address)); \
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if (sepDebug & SEP_DEBUG_LEVEL_REGISTERS) \
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printk(KERN_WARNING "Read Register: address %lu value %lu\n", \
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(address), (value)); \
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} while (0)
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#else
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#if 1
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#define SEP_WRITE_REGISTER(address, value) writel((value), (void *)(address))
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#define SEP_READ_REGISTER(address, value) (value) = readl((void *)(address))
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#endif
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#endif
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#if 0
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#define SEP_WRITE_ROM(address, value) writel((value), (void *)(address))
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#define SEP_WRITE_REGISTER(address, value) \
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do { \
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unsigned long i; \
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for (i = 0; i < 1000; i++); \
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writel((value), (void *)(address)); \
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} while (0)
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#define SEP_READ_REGISTER(address , value) \
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do { \
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unsigned long i; \
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for (i = 0; i < 1000; i++); \
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(value) = readl((void *) (address)); \
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} while (0)
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#endif
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/* wait for SRAM write complete(indirect write */
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#define SEP_WAIT_SRAM_WRITE_COMPLETE() \
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do { \
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unsigned long reg_val; \
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do { \
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SEP_READ_REGISTER(g_sep_reg_base_address + \
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HW_SRAM_DATA_READY_REG_ADDR, (reg_val)); \
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} while (!(reg_val & 0x1)); \
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} while (0)
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#endif
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@@ -0,0 +1,106 @@
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/*
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*
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* sep_driver_ext_api.h - Security Processor Driver external api definitions
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*
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* Copyright(c) 2009 Intel Corporation. All rights reserved.
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* Copyright(c) 2009 Discretix. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
|
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* Software Foundation; either version 2 of the License, or (at your option)
|
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
|
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
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* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59
|
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
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*
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* CONTACTS:
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*
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* Mark Allyn mark.a.allyn@intel.com
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*
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* CHANGES:
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*
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* 2009.06.26 Initial publish
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*
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*/
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#ifndef __SEP_DRIVER_EXT_API_H__
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#define __SEP_DRIVER_EXT_API_H__
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/* shared variables */
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extern int sepDebug;
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extern unsigned long g_sep_reg_base_address;
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/*
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this function loads the ROM code in SEP (needed only in the debug mode on FPGA)
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*/
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void sep_load_rom_code(void);
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/*
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This functions locks the area of the resident and cache sep code (if possible)
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*/
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void sep_lock_cache_resident_area(void);
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/*
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This functions copies the cache and resident from their source location into
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destination memory, which is external to Linux VM and is given as physical
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address
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*/
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int sep_copy_cache_resident_to_area(unsigned long src_cache_addr,
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unsigned long cache_size_in_bytes,
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unsigned long src_resident_addr,
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unsigned long resident_size_in_bytes,
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unsigned long *dst_new_cache_addr_ptr,
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unsigned long *dst_new_resident_addr_ptr);
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/*
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This functions maps and allocates the shared area on the external
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RAM (device) The input is shared_area_size - the size of the memory
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to allocate. The outputs are kernel_shared_area_addr_ptr - the kerenl
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address of the mapped and allocated shared area, and
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phys_shared_area_addr_ptr - the physical address of the shared area
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*/
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int sep_map_and_alloc_shared_area(unsigned long shared_area_size,
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unsigned long *kernel_shared_area_addr_ptr,
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unsigned long *phys_shared_area_addr_ptr);
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/*
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This functions unmaps and deallocates the shared area on the external
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RAM (device) The input is shared_area_size - the size of the memory to
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deallocate,kernel_shared_area_addr_ptr - the kernel address of the
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mapped and allocated shared area,phys_shared_area_addr_ptr - the physical
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address of the shared area
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*/
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void sep_unmap_and_free_shared_area(unsigned long shared_area_size,
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unsigned long kernel_shared_area_addr,
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unsigned long phys_shared_area_addr);
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/*
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This functions returns the physical address inside shared area according
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to the virtual address. It can be either on the externa RAM device
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(ioremapped), or on the system RAM
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*/
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unsigned long sep_shared_area_virt_to_phys(unsigned long virt_address);
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/*
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This functions returns the vitrual address inside shared area according
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to the physical address. It can be either on the externa RAM device
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(ioremapped), or on the system RAM This implementation is for the external RAM
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*/
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unsigned long sep_shared_area_phys_to_virt(unsigned long phys_address);
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/*
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This function registers th driver to the device
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subsystem (either PCI, USB, etc)
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*/
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int sep_register_driver_to_device(void);
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#endif /*__SEP_DRIVER_EXT_API_H__*/
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@@ -0,0 +1,240 @@
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/*
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*
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* sep_driver_hw_defs.h - Security Processor Driver hardware definitions
|
||||
*
|
||||
* Copyright(c) 2009 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2009 Discretix. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59
|
||||
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* CONTACTS:
|
||||
*
|
||||
* Mark Allyn mark.a.allyn@intel.com
|
||||
*
|
||||
* CHANGES:
|
||||
*
|
||||
* 2009.06.26 Initial publish
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef SEP_DRIVER_HW_DEFS__H
|
||||
#define SEP_DRIVER_HW_DEFS__H
|
||||
|
||||
/*--------------------------------------------------------------------------*/
|
||||
/* Abstract: HW Registers Defines. */
|
||||
/* */
|
||||
/* Note: This file was automatically created !!! */
|
||||
/* DO NOT EDIT THIS FILE !!! */
|
||||
/*--------------------------------------------------------------------------*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* cf registers */
|
||||
#define HW_R0B_ADDR_0_REG_ADDR 0x0000UL
|
||||
#define HW_R0B_ADDR_1_REG_ADDR 0x0004UL
|
||||
#define HW_R0B_ADDR_2_REG_ADDR 0x0008UL
|
||||
#define HW_R0B_ADDR_3_REG_ADDR 0x000cUL
|
||||
#define HW_R0B_ADDR_4_REG_ADDR 0x0010UL
|
||||
#define HW_R0B_ADDR_5_REG_ADDR 0x0014UL
|
||||
#define HW_R0B_ADDR_6_REG_ADDR 0x0018UL
|
||||
#define HW_R0B_ADDR_7_REG_ADDR 0x001cUL
|
||||
#define HW_R0B_ADDR_8_REG_ADDR 0x0020UL
|
||||
#define HW_R2B_ADDR_0_REG_ADDR 0x0080UL
|
||||
#define HW_R2B_ADDR_1_REG_ADDR 0x0084UL
|
||||
#define HW_R2B_ADDR_2_REG_ADDR 0x0088UL
|
||||
#define HW_R2B_ADDR_3_REG_ADDR 0x008cUL
|
||||
#define HW_R2B_ADDR_4_REG_ADDR 0x0090UL
|
||||
#define HW_R2B_ADDR_5_REG_ADDR 0x0094UL
|
||||
#define HW_R2B_ADDR_6_REG_ADDR 0x0098UL
|
||||
#define HW_R2B_ADDR_7_REG_ADDR 0x009cUL
|
||||
#define HW_R2B_ADDR_8_REG_ADDR 0x00a0UL
|
||||
#define HW_R3B_REG_ADDR 0x00C0UL
|
||||
#define HW_R4B_REG_ADDR 0x0100UL
|
||||
#define HW_CSA_ADDR_0_REG_ADDR 0x0140UL
|
||||
#define HW_CSA_ADDR_1_REG_ADDR 0x0144UL
|
||||
#define HW_CSA_ADDR_2_REG_ADDR 0x0148UL
|
||||
#define HW_CSA_ADDR_3_REG_ADDR 0x014cUL
|
||||
#define HW_CSA_ADDR_4_REG_ADDR 0x0150UL
|
||||
#define HW_CSA_ADDR_5_REG_ADDR 0x0154UL
|
||||
#define HW_CSA_ADDR_6_REG_ADDR 0x0158UL
|
||||
#define HW_CSA_ADDR_7_REG_ADDR 0x015cUL
|
||||
#define HW_CSA_ADDR_8_REG_ADDR 0x0160UL
|
||||
#define HW_CSA_REG_ADDR 0x0140UL
|
||||
#define HW_SINB_REG_ADDR 0x0180UL
|
||||
#define HW_SOUTB_REG_ADDR 0x0184UL
|
||||
#define HW_PKI_CONTROL_REG_ADDR 0x01C0UL
|
||||
#define HW_PKI_STATUS_REG_ADDR 0x01C4UL
|
||||
#define HW_PKI_BUSY_REG_ADDR 0x01C8UL
|
||||
#define HW_PKI_A_1025_REG_ADDR 0x01CCUL
|
||||
#define HW_PKI_SDMA_CTL_REG_ADDR 0x01D0UL
|
||||
#define HW_PKI_SDMA_OFFSET_REG_ADDR 0x01D4UL
|
||||
#define HW_PKI_SDMA_POINTERS_REG_ADDR 0x01D8UL
|
||||
#define HW_PKI_SDMA_DLENG_REG_ADDR 0x01DCUL
|
||||
#define HW_PKI_SDMA_EXP_POINTERS_REG_ADDR 0x01E0UL
|
||||
#define HW_PKI_SDMA_RES_POINTERS_REG_ADDR 0x01E4UL
|
||||
#define HW_PKI_CLR_REG_ADDR 0x01E8UL
|
||||
#define HW_PKI_SDMA_BUSY_REG_ADDR 0x01E8UL
|
||||
#define HW_PKI_SDMA_FIRST_EXP_N_REG_ADDR 0x01ECUL
|
||||
#define HW_PKI_SDMA_MUL_BY1_REG_ADDR 0x01F0UL
|
||||
#define HW_PKI_SDMA_RMUL_SEL_REG_ADDR 0x01F4UL
|
||||
#define HW_DES_KEY_0_REG_ADDR 0x0208UL
|
||||
#define HW_DES_KEY_1_REG_ADDR 0x020CUL
|
||||
#define HW_DES_KEY_2_REG_ADDR 0x0210UL
|
||||
#define HW_DES_KEY_3_REG_ADDR 0x0214UL
|
||||
#define HW_DES_KEY_4_REG_ADDR 0x0218UL
|
||||
#define HW_DES_KEY_5_REG_ADDR 0x021CUL
|
||||
#define HW_DES_CONTROL_0_REG_ADDR 0x0220UL
|
||||
#define HW_DES_CONTROL_1_REG_ADDR 0x0224UL
|
||||
#define HW_DES_IV_0_REG_ADDR 0x0228UL
|
||||
#define HW_DES_IV_1_REG_ADDR 0x022CUL
|
||||
#define HW_AES_KEY_0_ADDR_0_REG_ADDR 0x0400UL
|
||||
#define HW_AES_KEY_0_ADDR_1_REG_ADDR 0x0404UL
|
||||
#define HW_AES_KEY_0_ADDR_2_REG_ADDR 0x0408UL
|
||||
#define HW_AES_KEY_0_ADDR_3_REG_ADDR 0x040cUL
|
||||
#define HW_AES_KEY_0_ADDR_4_REG_ADDR 0x0410UL
|
||||
#define HW_AES_KEY_0_ADDR_5_REG_ADDR 0x0414UL
|
||||
#define HW_AES_KEY_0_ADDR_6_REG_ADDR 0x0418UL
|
||||
#define HW_AES_KEY_0_ADDR_7_REG_ADDR 0x041cUL
|
||||
#define HW_AES_KEY_0_REG_ADDR 0x0400UL
|
||||
#define HW_AES_IV_0_ADDR_0_REG_ADDR 0x0440UL
|
||||
#define HW_AES_IV_0_ADDR_1_REG_ADDR 0x0444UL
|
||||
#define HW_AES_IV_0_ADDR_2_REG_ADDR 0x0448UL
|
||||
#define HW_AES_IV_0_ADDR_3_REG_ADDR 0x044cUL
|
||||
#define HW_AES_IV_0_REG_ADDR 0x0440UL
|
||||
#define HW_AES_CTR1_ADDR_0_REG_ADDR 0x0460UL
|
||||
#define HW_AES_CTR1_ADDR_1_REG_ADDR 0x0464UL
|
||||
#define HW_AES_CTR1_ADDR_2_REG_ADDR 0x0468UL
|
||||
#define HW_AES_CTR1_ADDR_3_REG_ADDR 0x046cUL
|
||||
#define HW_AES_CTR1_REG_ADDR 0x0460UL
|
||||
#define HW_AES_SK_REG_ADDR 0x0478UL
|
||||
#define HW_AES_MAC_OK_REG_ADDR 0x0480UL
|
||||
#define HW_AES_PREV_IV_0_ADDR_0_REG_ADDR 0x0490UL
|
||||
#define HW_AES_PREV_IV_0_ADDR_1_REG_ADDR 0x0494UL
|
||||
#define HW_AES_PREV_IV_0_ADDR_2_REG_ADDR 0x0498UL
|
||||
#define HW_AES_PREV_IV_0_ADDR_3_REG_ADDR 0x049cUL
|
||||
#define HW_AES_PREV_IV_0_REG_ADDR 0x0490UL
|
||||
#define HW_AES_CONTROL_REG_ADDR 0x04C0UL
|
||||
#define HW_HASH_H0_REG_ADDR 0x0640UL
|
||||
#define HW_HASH_H1_REG_ADDR 0x0644UL
|
||||
#define HW_HASH_H2_REG_ADDR 0x0648UL
|
||||
#define HW_HASH_H3_REG_ADDR 0x064CUL
|
||||
#define HW_HASH_H4_REG_ADDR 0x0650UL
|
||||
#define HW_HASH_H5_REG_ADDR 0x0654UL
|
||||
#define HW_HASH_H6_REG_ADDR 0x0658UL
|
||||
#define HW_HASH_H7_REG_ADDR 0x065CUL
|
||||
#define HW_HASH_H8_REG_ADDR 0x0660UL
|
||||
#define HW_HASH_H9_REG_ADDR 0x0664UL
|
||||
#define HW_HASH_H10_REG_ADDR 0x0668UL
|
||||
#define HW_HASH_H11_REG_ADDR 0x066CUL
|
||||
#define HW_HASH_H12_REG_ADDR 0x0670UL
|
||||
#define HW_HASH_H13_REG_ADDR 0x0674UL
|
||||
#define HW_HASH_H14_REG_ADDR 0x0678UL
|
||||
#define HW_HASH_H15_REG_ADDR 0x067CUL
|
||||
#define HW_HASH_CONTROL_REG_ADDR 0x07C0UL
|
||||
#define HW_HASH_PAD_EN_REG_ADDR 0x07C4UL
|
||||
#define HW_HASH_PAD_CFG_REG_ADDR 0x07C8UL
|
||||
#define HW_HASH_CUR_LEN_0_REG_ADDR 0x07CCUL
|
||||
#define HW_HASH_CUR_LEN_1_REG_ADDR 0x07D0UL
|
||||
#define HW_HASH_CUR_LEN_2_REG_ADDR 0x07D4UL
|
||||
#define HW_HASH_CUR_LEN_3_REG_ADDR 0x07D8UL
|
||||
#define HW_HASH_PARAM_REG_ADDR 0x07DCUL
|
||||
#define HW_HASH_INT_BUSY_REG_ADDR 0x07E0UL
|
||||
#define HW_HASH_SW_RESET_REG_ADDR 0x07E4UL
|
||||
#define HW_HASH_ENDIANESS_REG_ADDR 0x07E8UL
|
||||
#define HW_HASH_DATA_REG_ADDR 0x07ECUL
|
||||
#define HW_DRNG_CONTROL_REG_ADDR 0x0800UL
|
||||
#define HW_DRNG_VALID_REG_ADDR 0x0804UL
|
||||
#define HW_DRNG_DATA_REG_ADDR 0x0808UL
|
||||
#define HW_RND_SRC_EN_REG_ADDR 0x080CUL
|
||||
#define HW_AES_CLK_ENABLE_REG_ADDR 0x0810UL
|
||||
#define HW_DES_CLK_ENABLE_REG_ADDR 0x0814UL
|
||||
#define HW_HASH_CLK_ENABLE_REG_ADDR 0x0818UL
|
||||
#define HW_PKI_CLK_ENABLE_REG_ADDR 0x081CUL
|
||||
#define HW_CLK_STATUS_REG_ADDR 0x0824UL
|
||||
#define HW_CLK_ENABLE_REG_ADDR 0x0828UL
|
||||
#define HW_DRNG_SAMPLE_REG_ADDR 0x0850UL
|
||||
#define HW_RND_SRC_CTL_REG_ADDR 0x0858UL
|
||||
#define HW_CRYPTO_CTL_REG_ADDR 0x0900UL
|
||||
#define HW_CRYPTO_STATUS_REG_ADDR 0x090CUL
|
||||
#define HW_CRYPTO_BUSY_REG_ADDR 0x0910UL
|
||||
#define HW_AES_BUSY_REG_ADDR 0x0914UL
|
||||
#define HW_DES_BUSY_REG_ADDR 0x0918UL
|
||||
#define HW_HASH_BUSY_REG_ADDR 0x091CUL
|
||||
#define HW_CONTENT_REG_ADDR 0x0924UL
|
||||
#define HW_VERSION_REG_ADDR 0x0928UL
|
||||
#define HW_CONTEXT_ID_REG_ADDR 0x0930UL
|
||||
#define HW_DIN_BUFFER_REG_ADDR 0x0C00UL
|
||||
#define HW_DIN_MEM_DMA_BUSY_REG_ADDR 0x0c20UL
|
||||
#define HW_SRC_LLI_MEM_ADDR_REG_ADDR 0x0c24UL
|
||||
#define HW_SRC_LLI_WORD0_REG_ADDR 0x0C28UL
|
||||
#define HW_SRC_LLI_WORD1_REG_ADDR 0x0C2CUL
|
||||
#define HW_SRAM_SRC_ADDR_REG_ADDR 0x0c30UL
|
||||
#define HW_DIN_SRAM_BYTES_LEN_REG_ADDR 0x0c34UL
|
||||
#define HW_DIN_SRAM_DMA_BUSY_REG_ADDR 0x0C38UL
|
||||
#define HW_WRITE_ALIGN_REG_ADDR 0x0C3CUL
|
||||
#define HW_OLD_DATA_REG_ADDR 0x0C48UL
|
||||
#define HW_WRITE_ALIGN_LAST_REG_ADDR 0x0C4CUL
|
||||
#define HW_DOUT_BUFFER_REG_ADDR 0x0C00UL
|
||||
#define HW_DST_LLI_WORD0_REG_ADDR 0x0D28UL
|
||||
#define HW_DST_LLI_WORD1_REG_ADDR 0x0D2CUL
|
||||
#define HW_DST_LLI_MEM_ADDR_REG_ADDR 0x0D24UL
|
||||
#define HW_DOUT_MEM_DMA_BUSY_REG_ADDR 0x0D20UL
|
||||
#define HW_SRAM_DEST_ADDR_REG_ADDR 0x0D30UL
|
||||
#define HW_DOUT_SRAM_BYTES_LEN_REG_ADDR 0x0D34UL
|
||||
#define HW_DOUT_SRAM_DMA_BUSY_REG_ADDR 0x0D38UL
|
||||
#define HW_READ_ALIGN_REG_ADDR 0x0D3CUL
|
||||
#define HW_READ_LAST_DATA_REG_ADDR 0x0D44UL
|
||||
#define HW_RC4_THRU_CPU_REG_ADDR 0x0D4CUL
|
||||
#define HW_AHB_SINGLE_REG_ADDR 0x0E00UL
|
||||
#define HW_SRAM_DATA_REG_ADDR 0x0F00UL
|
||||
#define HW_SRAM_ADDR_REG_ADDR 0x0F04UL
|
||||
#define HW_SRAM_DATA_READY_REG_ADDR 0x0F08UL
|
||||
#define HW_HOST_IRR_REG_ADDR 0x0A00UL
|
||||
#define HW_HOST_IMR_REG_ADDR 0x0A04UL
|
||||
#define HW_HOST_ICR_REG_ADDR 0x0A08UL
|
||||
#define HW_HOST_SEP_SRAM_THRESHOLD_REG_ADDR 0x0A10UL
|
||||
#define HW_HOST_SEP_BUSY_REG_ADDR 0x0A14UL
|
||||
#define HW_HOST_SEP_LCS_REG_ADDR 0x0A18UL
|
||||
#define HW_HOST_CC_SW_RST_REG_ADDR 0x0A40UL
|
||||
#define HW_HOST_SEP_SW_RST_REG_ADDR 0x0A44UL
|
||||
#define HW_HOST_FLOW_DMA_SW_INT0_REG_ADDR 0x0A80UL
|
||||
#define HW_HOST_FLOW_DMA_SW_INT1_REG_ADDR 0x0A84UL
|
||||
#define HW_HOST_FLOW_DMA_SW_INT2_REG_ADDR 0x0A88UL
|
||||
#define HW_HOST_FLOW_DMA_SW_INT3_REG_ADDR 0x0A8cUL
|
||||
#define HW_HOST_FLOW_DMA_SW_INT4_REG_ADDR 0x0A90UL
|
||||
#define HW_HOST_FLOW_DMA_SW_INT5_REG_ADDR 0x0A94UL
|
||||
#define HW_HOST_FLOW_DMA_SW_INT6_REG_ADDR 0x0A98UL
|
||||
#define HW_HOST_FLOW_DMA_SW_INT7_REG_ADDR 0x0A9cUL
|
||||
#define HW_HOST_SEP_HOST_GPR0_REG_ADDR 0x0B00UL
|
||||
#define HW_HOST_SEP_HOST_GPR1_REG_ADDR 0x0B04UL
|
||||
#define HW_HOST_SEP_HOST_GPR2_REG_ADDR 0x0B08UL
|
||||
#define HW_HOST_SEP_HOST_GPR3_REG_ADDR 0x0B0CUL
|
||||
#define HW_HOST_HOST_SEP_GPR0_REG_ADDR 0x0B80UL
|
||||
#define HW_HOST_HOST_SEP_GPR1_REG_ADDR 0x0B84UL
|
||||
#define HW_HOST_HOST_SEP_GPR2_REG_ADDR 0x0B88UL
|
||||
#define HW_HOST_HOST_SEP_GPR3_REG_ADDR 0x0B8CUL
|
||||
#define HW_HOST_HOST_ENDIAN_REG_ADDR 0x0B90UL
|
||||
#define HW_HOST_HOST_COMM_CLK_EN_REG_ADDR 0x0B94UL
|
||||
#define HW_CLR_SRAM_BUSY_REG_REG_ADDR 0x0F0CUL
|
||||
#define HW_CC_SRAM_BASE_ADDRESS 0x5800UL
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef HW_DEFS */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user