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Merge tag 'soc-exynos5420-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/late

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From Kukjin Kim, this adds pinctrl support for Exynos 5420.

* tag 'soc-exynos5420-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  pinctrl: exynos: add exynos5420 SoC specific data
  ARM: dts: add pinctrl support to EXYNOS5420

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
2013-06-25 08:50:18 -07:00
parent e8f2ca9715 983dbeb35f
commit cbe461f654
6 changed files with 847 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+1
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@@ -11,6 +11,7 @@ Required Properties:
- "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
- "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
- "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
the address space it occupies.
arch/arm/boot/dts/exynos5420-pinctrl.dtsi
+680
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File diff suppressed because it is too large Load Diff
arch/arm/boot/dts/exynos5420.dtsi
+45
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@@ -14,9 +14,18 @@
*/
#include "exynos5.dtsi"
/include/ "exynos5420-pinctrl.dtsi"
/ {
compatible = "samsung,exynos5420";
aliases {
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
pinctrl2 = &pinctrl_2;
pinctrl3 = &pinctrl_3;
pinctrl4 = &pinctrl_4;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -81,6 +90,42 @@
};
};
pinctrl_0: pinctrl@13400000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x13400000 0x1000>;
interrupts = <0 45 0>;
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
interrupts = <0 32 0>;
};
};
pinctrl_1: pinctrl@13410000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x13410000 0x1000>;
interrupts = <0 78 0>;
};
pinctrl_2: pinctrl@14000000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x14000000 0x1000>;
interrupts = <0 46 0>;
};
pinctrl_3: pinctrl@14010000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x14010000 0x1000>;
interrupts = <0 50 0>;
};
pinctrl_4: pinctrl@03860000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x03860000 0x1000>;
interrupts = <0 47 0>;
};
serial@12C00000 {
clocks = <&clock 257>, <&clock 128>;
clock-names = "uart", "clk_uart_baud0";
drivers/pinctrl/pinctrl-exynos.c
+118
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@@ -941,3 +941,121 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
.label = "exynos5250-gpio-ctrl3",
},
};
/* pin banks of exynos5420 pin-controller 0 */
static struct samsung_pin_bank exynos5420_pin_banks0[] = {
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
};
/* pin banks of exynos5420 pin-controller 1 */
static struct samsung_pin_bank exynos5420_pin_banks1[] = {
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10),
EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14),
EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"),
EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"),
EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"),
EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"),
EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"),
EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"),
EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"),
};
/* pin banks of exynos5420 pin-controller 2 */
static struct samsung_pin_bank exynos5420_pin_banks2[] = {
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c),
EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c),
};
/* pin banks of exynos5420 pin-controller 3 */
static struct samsung_pin_bank exynos5420_pin_banks3[] = {
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c),
EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20),
};
/* pin banks of exynos5420 pin-controller 4 */
static struct samsung_pin_bank exynos5420_pin_banks4[] = {
EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
};
/*
* Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes
* four gpio/pin-mux/pinconfig controllers.
*/
struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
{
/* pin-controller instance 0 data */
.pin_banks = exynos5420_pin_banks0,
.nr_banks = ARRAY_SIZE(exynos5420_pin_banks0),
.geint_con = EXYNOS_GPIO_ECON_OFFSET,
.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
.weint_con = EXYNOS_WKUP_ECON_OFFSET,
.weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
.weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
.svc = EXYNOS_SVC_OFFSET,
.eint_gpio_init = exynos_eint_gpio_init,
.eint_wkup_init = exynos_eint_wkup_init,
.label = "exynos5420-gpio-ctrl0",
}, {
/* pin-controller instance 1 data */
.pin_banks = exynos5420_pin_banks1,
.nr_banks = ARRAY_SIZE(exynos5420_pin_banks1),
.geint_con = EXYNOS_GPIO_ECON_OFFSET,
.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
.svc = EXYNOS_SVC_OFFSET,
.eint_gpio_init = exynos_eint_gpio_init,
.label = "exynos5420-gpio-ctrl1",
}, {
/* pin-controller instance 2 data */
.pin_banks = exynos5420_pin_banks2,
.nr_banks = ARRAY_SIZE(exynos5420_pin_banks2),
.geint_con = EXYNOS_GPIO_ECON_OFFSET,
.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
.svc = EXYNOS_SVC_OFFSET,
.eint_gpio_init = exynos_eint_gpio_init,
.label = "exynos5420-gpio-ctrl2",
}, {
/* pin-controller instance 3 data */
.pin_banks = exynos5420_pin_banks3,
.nr_banks = ARRAY_SIZE(exynos5420_pin_banks3),
.geint_con = EXYNOS_GPIO_ECON_OFFSET,
.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
.svc = EXYNOS_SVC_OFFSET,
.eint_gpio_init = exynos_eint_gpio_init,
.label = "exynos5420-gpio-ctrl3",
}, {
/* pin-controller instance 4 data */
.pin_banks = exynos5420_pin_banks4,
.nr_banks = ARRAY_SIZE(exynos5420_pin_banks4),
.geint_con = EXYNOS_GPIO_ECON_OFFSET,
.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
.svc = EXYNOS_SVC_OFFSET,
.eint_gpio_init = exynos_eint_gpio_init,
.label = "exynos5420-gpio-ctrl4",
},
};
drivers/pinctrl/pinctrl-samsung.c
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@@ -1113,6 +1113,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
.data = (void *)exynos4x12_pin_ctrl },
{ .compatible = "samsung,exynos5250-pinctrl",
.data = (void *)exynos5250_pin_ctrl },
{ .compatible = "samsung,exynos5420-pinctrl",
.data = (void *)exynos5420_pin_ctrl },
#endif
#ifdef CONFIG_PINCTRL_S3C64XX
{ .compatible = "samsung,s3c64xx-pinctrl",
drivers/pinctrl/pinctrl-samsung.h
+1
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@@ -254,6 +254,7 @@ struct samsung_pmx_func {
extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
extern struct samsung_pin_ctrl exynos5250_pin_ctrl[];
extern struct samsung_pin_ctrl exynos5420_pin_ctrl[];
extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[];
#endif /* __PINCTRL_SAMSUNG_H */