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sparc64: correctly recognise M6 and M7 cpu type
The following patch adds support for correctly recognising M6 and M7 cpu type. Signed-off-by: Allen Pais <allen.pais@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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committed by
David S. Miller
parent
619df5d287
commit
cadbb58039
@@ -45,6 +45,8 @@
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#define SUN4V_CHIP_NIAGARA3 0x03
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#define SUN4V_CHIP_NIAGARA4 0x04
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#define SUN4V_CHIP_NIAGARA5 0x05
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#define SUN4V_CHIP_SPARC_M6 0x06
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#define SUN4V_CHIP_SPARC_M7 0x07
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#define SUN4V_CHIP_SPARC64X 0x8a
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#define SUN4V_CHIP_UNKNOWN 0xff
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@@ -494,6 +494,18 @@ static void __init sun4v_cpu_probe(void)
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sparc_pmu_type = "niagara5";
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break;
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case SUN4V_CHIP_SPARC_M6:
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sparc_cpu_type = "SPARC-M6";
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sparc_fpu_type = "SPARC-M6 integrated FPU";
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sparc_pmu_type = "sparc-m6";
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break;
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case SUN4V_CHIP_SPARC_M7:
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sparc_cpu_type = "SPARC-M7";
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sparc_fpu_type = "SPARC-M7 integrated FPU";
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sparc_pmu_type = "sparc-m7";
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break;
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case SUN4V_CHIP_SPARC64X:
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sparc_cpu_type = "SPARC64-X";
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sparc_fpu_type = "SPARC64-X integrated FPU";
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@@ -427,6 +427,12 @@ sun4v_chip_type:
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cmp %g2, '5'
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be,pt %xcc, 5f
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mov SUN4V_CHIP_NIAGARA5, %g4
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cmp %g2, '6'
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be,pt %xcc, 5f
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mov SUN4V_CHIP_SPARC_M6, %g4
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cmp %g2, '7'
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be,pt %xcc, 5f
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mov SUN4V_CHIP_SPARC_M7, %g4
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ba,pt %xcc, 49f
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nop
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@@ -583,6 +589,12 @@ niagara_tlb_fixup:
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be,pt %xcc, niagara4_patch
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nop
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cmp %g1, SUN4V_CHIP_NIAGARA5
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be,pt %xcc, niagara4_patch
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nop
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cmp %g1, SUN4V_CHIP_SPARC_M6
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be,pt %xcc, niagara4_patch
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nop
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cmp %g1, SUN4V_CHIP_SPARC_M7
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be,pt %xcc, niagara4_patch
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nop
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