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Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 updates from Will Deacon:
"The big highlight is support for the Scalable Vector Extension (SVE)
which required extensive ABI work to ensure we don't break existing
applications by blowing away their signal stack with the rather large
new vector context (<= 2 kbit per vector register). There's further
work to be done optimising things like exception return, but the ABI
is solid now.
Much of the line count comes from some new PMU drivers we have, but
they're pretty self-contained and I suspect we'll have more of them in
future.
Plenty of acronym soup here:
- initial support for the Scalable Vector Extension (SVE)
- improved handling for SError interrupts (required to handle RAS
events)
- enable GCC support for 128-bit integer types
- remove kernel text addresses from backtraces and register dumps
- use of WFE to implement long delay()s
- ACPI IORT updates from Lorenzo Pieralisi
- perf PMU driver for the Statistical Profiling Extension (SPE)
- perf PMU driver for Hisilicon's system PMUs
- misc cleanups and non-critical fixes"
* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (97 commits)
arm64: Make ARMV8_DEPRECATED depend on SYSCTL
arm64: Implement __lshrti3 library function
arm64: support __int128 on gcc 5+
arm64/sve: Add documentation
arm64/sve: Detect SVE and activate runtime support
arm64/sve: KVM: Hide SVE from CPU features exposed to guests
arm64/sve: KVM: Treat guest SVE use as undefined instruction execution
arm64/sve: KVM: Prevent guests from using SVE
arm64/sve: Add sysctl to set the default vector length for new processes
arm64/sve: Add prctl controls for userspace vector length management
arm64/sve: ptrace and ELF coredump support
arm64/sve: Preserve SVE registers around EFI runtime service calls
arm64/sve: Preserve SVE registers around kernel-mode NEON use
arm64/sve: Probe SVE capabilities and usable vector lengths
arm64: cpufeature: Move sys_caps_initialised declarations
arm64/sve: Backend logic for setting the vector length
arm64/sve: Signal handling support
arm64/sve: Support vector length resetting for new processes
arm64/sve: Core task context handling
arm64/sve: Low-level CPU setup
...
This commit is contained in:
Linus Torvalds
@@ -110,10 +110,20 @@ infrastructure:
|
||||
x--------------------------------------------------x
|
||||
| Name | bits | visible |
|
||||
|--------------------------------------------------|
|
||||
| RES0 | [63-32] | n |
|
||||
| RES0 | [63-48] | n |
|
||||
|--------------------------------------------------|
|
||||
| DP | [47-44] | y |
|
||||
|--------------------------------------------------|
|
||||
| SM4 | [43-40] | y |
|
||||
|--------------------------------------------------|
|
||||
| SM3 | [39-36] | y |
|
||||
|--------------------------------------------------|
|
||||
| SHA3 | [35-32] | y |
|
||||
|--------------------------------------------------|
|
||||
| RDM | [31-28] | y |
|
||||
|--------------------------------------------------|
|
||||
| RES0 | [27-24] | n |
|
||||
|--------------------------------------------------|
|
||||
| ATOMICS | [23-20] | y |
|
||||
|--------------------------------------------------|
|
||||
| CRC32 | [19-16] | y |
|
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@@ -132,7 +142,11 @@ infrastructure:
|
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x--------------------------------------------------x
|
||||
| Name | bits | visible |
|
||||
|--------------------------------------------------|
|
||||
| RES0 | [63-28] | n |
|
||||
| RES0 | [63-36] | n |
|
||||
|--------------------------------------------------|
|
||||
| SVE | [35-32] | y |
|
||||
|--------------------------------------------------|
|
||||
| RES0 | [31-28] | n |
|
||||
|--------------------------------------------------|
|
||||
| GIC | [27-24] | n |
|
||||
|--------------------------------------------------|
|
||||
|
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@@ -0,0 +1,160 @@
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ARM64 ELF hwcaps
|
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================
|
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|
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This document describes the usage and semantics of the arm64 ELF hwcaps.
|
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|
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|
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1. Introduction
|
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---------------
|
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|
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Some hardware or software features are only available on some CPU
|
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implementations, and/or with certain kernel configurations, but have no
|
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architected discovery mechanism available to userspace code at EL0. The
|
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kernel exposes the presence of these features to userspace through a set
|
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of flags called hwcaps, exposed in the auxilliary vector.
|
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|
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Userspace software can test for features by acquiring the AT_HWCAP entry
|
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of the auxilliary vector, and testing whether the relevant flags are
|
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set, e.g.
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|
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bool floating_point_is_present(void)
|
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{
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unsigned long hwcaps = getauxval(AT_HWCAP);
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if (hwcaps & HWCAP_FP)
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return true;
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return false;
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}
|
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|
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Where software relies on a feature described by a hwcap, it should check
|
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the relevant hwcap flag to verify that the feature is present before
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attempting to make use of the feature.
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|
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Features cannot be probed reliably through other means. When a feature
|
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is not available, attempting to use it may result in unpredictable
|
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behaviour, and is not guaranteed to result in any reliable indication
|
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that the feature is unavailable, such as a SIGILL.
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|
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|
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2. Interpretation of hwcaps
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---------------------------
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|
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The majority of hwcaps are intended to indicate the presence of features
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which are described by architected ID registers inaccessible to
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userspace code at EL0. These hwcaps are defined in terms of ID register
|
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fields, and should be interpreted with reference to the definition of
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these fields in the ARM Architecture Reference Manual (ARM ARM).
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|
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Such hwcaps are described below in the form:
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|
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Functionality implied by idreg.field == val.
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|
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Such hwcaps indicate the availability of functionality that the ARM ARM
|
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defines as being present when idreg.field has value val, but do not
|
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indicate that idreg.field is precisely equal to val, nor do they
|
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indicate the absence of functionality implied by other values of
|
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idreg.field.
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|
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Other hwcaps may indicate the presence of features which cannot be
|
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described by ID registers alone. These may be described without
|
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reference to ID registers, and may refer to other documentation.
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|
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|
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3. The hwcaps exposed in AT_HWCAP
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---------------------------------
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HWCAP_FP
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Functionality implied by ID_AA64PFR0_EL1.FP == 0b0000.
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|
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HWCAP_ASIMD
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|
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Functionality implied by ID_AA64PFR0_EL1.AdvSIMD == 0b0000.
|
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|
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HWCAP_EVTSTRM
|
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|
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The generic timer is configured to generate events at a frequency of
|
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approximately 100KHz.
|
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|
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HWCAP_AES
|
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|
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Functionality implied by ID_AA64ISAR1_EL1.AES == 0b0001.
|
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|
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HWCAP_PMULL
|
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|
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Functionality implied by ID_AA64ISAR1_EL1.AES == 0b0010.
|
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|
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HWCAP_SHA1
|
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|
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Functionality implied by ID_AA64ISAR0_EL1.SHA1 == 0b0001.
|
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|
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HWCAP_SHA2
|
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|
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Functionality implied by ID_AA64ISAR0_EL1.SHA2 == 0b0001.
|
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|
||||
HWCAP_CRC32
|
||||
|
||||
Functionality implied by ID_AA64ISAR0_EL1.CRC32 == 0b0001.
|
||||
|
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HWCAP_ATOMICS
|
||||
|
||||
Functionality implied by ID_AA64ISAR0_EL1.Atomic == 0b0010.
|
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|
||||
HWCAP_FPHP
|
||||
|
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Functionality implied by ID_AA64PFR0_EL1.FP == 0b0001.
|
||||
|
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HWCAP_ASIMDHP
|
||||
|
||||
Functionality implied by ID_AA64PFR0_EL1.AdvSIMD == 0b0001.
|
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|
||||
HWCAP_CPUID
|
||||
|
||||
EL0 access to certain ID registers is available, to the extent
|
||||
described by Documentation/arm64/cpu-feature-registers.txt.
|
||||
|
||||
These ID registers may imply the availability of features.
|
||||
|
||||
HWCAP_ASIMDRDM
|
||||
|
||||
Functionality implied by ID_AA64ISAR0_EL1.RDM == 0b0001.
|
||||
|
||||
HWCAP_JSCVT
|
||||
|
||||
Functionality implied by ID_AA64ISAR1_EL1.JSCVT == 0b0001.
|
||||
|
||||
HWCAP_FCMA
|
||||
|
||||
Functionality implied by ID_AA64ISAR1_EL1.FCMA == 0b0001.
|
||||
|
||||
HWCAP_LRCPC
|
||||
|
||||
Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0001.
|
||||
|
||||
HWCAP_DCPOP
|
||||
|
||||
Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0001.
|
||||
|
||||
HWCAP_SHA3
|
||||
|
||||
Functionality implied by ID_AA64ISAR0_EL1.SHA3 == 0b0001.
|
||||
|
||||
HWCAP_SM3
|
||||
|
||||
Functionality implied by ID_AA64ISAR0_EL1.SM3 == 0b0001.
|
||||
|
||||
HWCAP_SM4
|
||||
|
||||
Functionality implied by ID_AA64ISAR0_EL1.SM4 == 0b0001.
|
||||
|
||||
HWCAP_ASIMDDP
|
||||
|
||||
Functionality implied by ID_AA64ISAR0_EL1.DP == 0b0001.
|
||||
|
||||
HWCAP_SHA512
|
||||
|
||||
Functionality implied by ID_AA64ISAR0_EL1.SHA2 == 0b0002.
|
||||
|
||||
HWCAP_SVE
|
||||
|
||||
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001.
|
||||
@@ -86,9 +86,9 @@ Translation table lookup with 64KB pages:
|
||||
+-------------------------------------------------> [63] TTBR0/1
|
||||
|
||||
|
||||
When using KVM, the hypervisor maps kernel pages in EL2, at a fixed
|
||||
offset from the kernel VA (top 24bits of the kernel VA set to zero):
|
||||
When using KVM without the Virtualization Host Extensions, the hypervisor
|
||||
maps kernel pages in EL2 at a fixed offset from the kernel VA. See the
|
||||
kern_hyp_va macro for more details.
|
||||
|
||||
Start End Size Use
|
||||
-----------------------------------------------------------------------
|
||||
0000004000000000 0000007fffffffff 256GB kernel objects mapped in HYP
|
||||
When using KVM with the Virtualization Host Extensions, no additional
|
||||
mappings are created, since the host kernel runs directly in EL2.
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,20 @@
|
||||
* ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU)
|
||||
|
||||
ARMv8.2 introduces the optional Statistical Profiling Extension for collecting
|
||||
performance sample data using an in-memory trace buffer.
|
||||
|
||||
** SPE Required properties:
|
||||
|
||||
- compatible : should be one of:
|
||||
"arm,statistical-profiling-extension-v1"
|
||||
|
||||
- interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where
|
||||
SPE is only supported on a subset of the CPUs, please consult
|
||||
the arm,gic-v3 binding for details on describing a PPI partition.
|
||||
|
||||
** Example:
|
||||
|
||||
spe-pmu {
|
||||
compatible = "arm,statistical-profiling-extension-v1";
|
||||
interrupts = <GIC_PPI 05 IRQ_TYPE_LEVEL_HIGH &part1>;
|
||||
};
|
||||
@@ -0,0 +1,53 @@
|
||||
HiSilicon SoC uncore Performance Monitoring Unit (PMU)
|
||||
======================================================
|
||||
The HiSilicon SoC chip includes various independent system device PMUs
|
||||
such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
|
||||
independent and have hardware logic to gather statistics and performance
|
||||
information.
|
||||
|
||||
The HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster
|
||||
(CCL) is made up of 4 cpu cores sharing one L3 cache; each CPU die is
|
||||
called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has
|
||||
two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
|
||||
|
||||
HiSilicon SoC uncore PMU driver
|
||||
---------------------------------------
|
||||
Each device PMU has separate registers for event counting, control and
|
||||
interrupt, and the PMU driver shall register perf PMU drivers like L3C,
|
||||
HHA and DDRC etc. The available events and configuration options shall
|
||||
be described in the sysfs, see :
|
||||
/sys/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>/, or
|
||||
/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>.
|
||||
The "perf list" command shall list the available events from sysfs.
|
||||
|
||||
Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
|
||||
name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>.
|
||||
where "sccl-id" is the identifier of the SCCL and "index-id" is the index of
|
||||
module.
|
||||
e.g. hisi_sccl3_l3c0/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 in
|
||||
SCCL ID #3.
|
||||
e.g. hisi_sccl1_hha0/rx_operations is RX_OPERATIONS event of HHA index #0 in
|
||||
SCCL ID #1.
|
||||
|
||||
The driver also provides a "cpumask" sysfs attribute, which shows the CPU core
|
||||
ID used to count the uncore PMU event.
|
||||
|
||||
Example usage of perf:
|
||||
$# perf list
|
||||
hisi_sccl3_l3c0/rd_hit_cpipe/ [kernel PMU event]
|
||||
------------------------------------------
|
||||
hisi_sccl3_l3c0/wr_hit_cpipe/ [kernel PMU event]
|
||||
------------------------------------------
|
||||
hisi_sccl1_l3c0/rd_hit_cpipe/ [kernel PMU event]
|
||||
------------------------------------------
|
||||
hisi_sccl1_l3c0/wr_hit_cpipe/ [kernel PMU event]
|
||||
------------------------------------------
|
||||
|
||||
$# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5
|
||||
$# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5
|
||||
|
||||
The current driver does not support sampling. So "perf record" is unsupported.
|
||||
Also attach to a task is unsupported as the events are all uncore.
|
||||
|
||||
Note: Please contact the maintainer for a complete list of events supported for
|
||||
the PMU devices in the SoC and its information if needed.
|
||||
@@ -6259,6 +6259,13 @@ S: Maintained
|
||||
F: drivers/net/ethernet/hisilicon/
|
||||
F: Documentation/devicetree/bindings/net/hisilicon*.txt
|
||||
|
||||
HISILICON PMU DRIVER
|
||||
M: Shaokun Zhang <zhangshaokun@hisilicon.com>
|
||||
W: http://www.hisilicon.com
|
||||
S: Supported
|
||||
F: drivers/perf/hisilicon
|
||||
F: Documentation/perf/hisi-pmu.txt
|
||||
|
||||
HISILICON ROCE DRIVER
|
||||
M: Lijun Ou <oulijun@huawei.com>
|
||||
M: Wei Hu(Xavier) <xavier.huwei@huawei.com>
|
||||
|
||||
@@ -107,6 +107,7 @@ static inline u32 arch_timer_get_cntkctl(void)
|
||||
static inline void arch_timer_set_cntkctl(u32 cntkctl)
|
||||
{
|
||||
asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
|
||||
isb();
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -293,4 +293,7 @@ int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
|
||||
int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
|
||||
struct kvm_device_attr *attr);
|
||||
|
||||
/* All host FP/SIMD state is restored on guest exit, so nothing to save: */
|
||||
static inline void kvm_fpsimd_flush_cpu_state(void) {}
|
||||
|
||||
#endif /* __ARM_KVM_HOST_H__ */
|
||||
|
||||
+16
-2
@@ -21,7 +21,7 @@ config ARM64
|
||||
select ARCH_HAS_STRICT_KERNEL_RWX
|
||||
select ARCH_HAS_STRICT_MODULE_RWX
|
||||
select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
|
||||
select ARCH_HAVE_NMI_SAFE_CMPXCHG if ACPI_APEI_SEA
|
||||
select ARCH_HAVE_NMI_SAFE_CMPXCHG
|
||||
select ARCH_INLINE_READ_LOCK if !PREEMPT
|
||||
select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
|
||||
select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
|
||||
@@ -115,7 +115,7 @@ config ARM64
|
||||
select HAVE_IRQ_TIME_ACCOUNTING
|
||||
select HAVE_MEMBLOCK
|
||||
select HAVE_MEMBLOCK_NODE_MAP if NUMA
|
||||
select HAVE_NMI if ACPI_APEI_SEA
|
||||
select HAVE_NMI
|
||||
select HAVE_PATA_PLATFORM
|
||||
select HAVE_PERF_EVENTS
|
||||
select HAVE_PERF_REGS
|
||||
@@ -136,6 +136,7 @@ config ARM64
|
||||
select PCI_ECAM if ACPI
|
||||
select POWER_RESET
|
||||
select POWER_SUPPLY
|
||||
select REFCOUNT_FULL
|
||||
select SPARSE_IRQ
|
||||
select SYSCTL_EXCEPTION_TRACE
|
||||
select THREAD_INFO_IN_TASK
|
||||
@@ -842,6 +843,7 @@ config FORCE_MAX_ZONEORDER
|
||||
menuconfig ARMV8_DEPRECATED
|
||||
bool "Emulate deprecated/obsolete ARMv8 instructions"
|
||||
depends on COMPAT
|
||||
depends on SYSCTL
|
||||
help
|
||||
Legacy software support may require certain instructions
|
||||
that have been deprecated or obsoleted in the architecture.
|
||||
@@ -1011,6 +1013,17 @@ config ARM64_PMEM
|
||||
|
||||
endmenu
|
||||
|
||||
config ARM64_SVE
|
||||
bool "ARM Scalable Vector Extension support"
|
||||
default y
|
||||
help
|
||||
The Scalable Vector Extension (SVE) is an extension to the AArch64
|
||||
execution state which complements and extends the SIMD functionality
|
||||
of the base architecture to support much larger vectors and to enable
|
||||
additional vectorisation opportunities.
|
||||
|
||||
To enable use of this extension on CPUs that implement it, say Y.
|
||||
|
||||
config ARM64_MODULE_CMODEL_LARGE
|
||||
bool
|
||||
|
||||
@@ -1099,6 +1112,7 @@ config EFI_STUB
|
||||
config EFI
|
||||
bool "UEFI runtime support"
|
||||
depends on OF && !CPU_BIG_ENDIAN
|
||||
depends on KERNEL_MODE_NEON
|
||||
select LIBFDT
|
||||
select UCS2_STRING
|
||||
select EFI_PARAMS_FROM_FDT
|
||||
|
||||
+8
-2
@@ -14,8 +14,12 @@ LDFLAGS_vmlinux :=-p --no-undefined -X
|
||||
CPPFLAGS_vmlinux.lds = -DTEXT_OFFSET=$(TEXT_OFFSET)
|
||||
GZFLAGS :=-9
|
||||
|
||||
ifneq ($(CONFIG_RELOCATABLE),)
|
||||
LDFLAGS_vmlinux += -pie -shared -Bsymbolic
|
||||
ifeq ($(CONFIG_RELOCATABLE), y)
|
||||
# Pass --no-apply-dynamic-relocs to restore pre-binutils-2.27 behaviour
|
||||
# for relative relocs, since this leads to better Image compression
|
||||
# with the relocation offsets always being zero.
|
||||
LDFLAGS_vmlinux += -pie -shared -Bsymbolic \
|
||||
$(call ld-option, --no-apply-dynamic-relocs)
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARM64_ERRATUM_843419),y)
|
||||
@@ -53,6 +57,8 @@ KBUILD_AFLAGS += $(lseinstr) $(brokengasinst)
|
||||
KBUILD_CFLAGS += $(call cc-option,-mabi=lp64)
|
||||
KBUILD_AFLAGS += $(call cc-option,-mabi=lp64)
|
||||
|
||||
KBUILD_CFLAGS += $(call cc-ifversion, -ge, 0500, -DCONFIG_ARCH_SUPPORTS_INT128)
|
||||
|
||||
ifeq ($(CONFIG_CPU_BIG_ENDIAN), y)
|
||||
KBUILD_CPPFLAGS += -mbig-endian
|
||||
CHECKFLAGS += -D__AARCH64EB__
|
||||
|
||||
@@ -144,6 +144,7 @@ static inline u32 arch_timer_get_cntkctl(void)
|
||||
static inline void arch_timer_set_cntkctl(u32 cntkctl)
|
||||
{
|
||||
write_sysreg(cntkctl, cntkctl_el1);
|
||||
isb();
|
||||
}
|
||||
|
||||
static inline u64 arch_counter_get_cntpct(void)
|
||||
|
||||
@@ -22,10 +22,10 @@
|
||||
#define _BUGVERBOSE_LOCATION(file, line) __BUGVERBOSE_LOCATION(file, line)
|
||||
#define __BUGVERBOSE_LOCATION(file, line) \
|
||||
.pushsection .rodata.str,"aMS",@progbits,1; \
|
||||
2: .string file; \
|
||||
14472: .string file; \
|
||||
.popsection; \
|
||||
\
|
||||
.long 2b - 0b; \
|
||||
.long 14472b - 14470b; \
|
||||
.short line;
|
||||
#else
|
||||
#define _BUGVERBOSE_LOCATION(file, line)
|
||||
@@ -36,11 +36,11 @@
|
||||
#define __BUG_ENTRY(flags) \
|
||||
.pushsection __bug_table,"aw"; \
|
||||
.align 2; \
|
||||
0: .long 1f - 0b; \
|
||||
14470: .long 14471f - 14470b; \
|
||||
_BUGVERBOSE_LOCATION(__FILE__, __LINE__) \
|
||||
.short flags; \
|
||||
.popsection; \
|
||||
1:
|
||||
14471:
|
||||
#else
|
||||
#define __BUG_ENTRY(flags)
|
||||
#endif
|
||||
|
||||
@@ -25,12 +25,41 @@
|
||||
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/cpufeature.h>
|
||||
#include <asm/debug-monitors.h>
|
||||
#include <asm/mmu_context.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/pgtable-hwdef.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/thread_info.h>
|
||||
|
||||
.macro save_and_disable_daif, flags
|
||||
mrs \flags, daif
|
||||
msr daifset, #0xf
|
||||
.endm
|
||||
|
||||
.macro disable_daif
|
||||
msr daifset, #0xf
|
||||
.endm
|
||||
|
||||
.macro enable_daif
|
||||
msr daifclr, #0xf
|
||||
.endm
|
||||
|
||||
.macro restore_daif, flags:req
|
||||
msr daif, \flags
|
||||
.endm
|
||||
|
||||
/* Only on aarch64 pstate, PSR_D_BIT is different for aarch32 */
|
||||
.macro inherit_daif, pstate:req, tmp:req
|
||||
and \tmp, \pstate, #(PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
|
||||
msr daif, \tmp
|
||||
.endm
|
||||
|
||||
/* IRQ is the lowest priority flag, unconditionally unmask the rest. */
|
||||
.macro enable_da_f
|
||||
msr daifclr, #(8 | 4 | 1)
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Enable and disable interrupts.
|
||||
*/
|
||||
@@ -51,13 +80,6 @@
|
||||
msr daif, \flags
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Enable and disable debug exceptions.
|
||||
*/
|
||||
.macro disable_dbg
|
||||
msr daifset, #8
|
||||
.endm
|
||||
|
||||
.macro enable_dbg
|
||||
msr daifclr, #8
|
||||
.endm
|
||||
@@ -65,30 +87,21 @@
|
||||
.macro disable_step_tsk, flgs, tmp
|
||||
tbz \flgs, #TIF_SINGLESTEP, 9990f
|
||||
mrs \tmp, mdscr_el1
|
||||
bic \tmp, \tmp, #1
|
||||
bic \tmp, \tmp, #DBG_MDSCR_SS
|
||||
msr mdscr_el1, \tmp
|
||||
isb // Synchronise with enable_dbg
|
||||
9990:
|
||||
.endm
|
||||
|
||||
/* call with daif masked */
|
||||
.macro enable_step_tsk, flgs, tmp
|
||||
tbz \flgs, #TIF_SINGLESTEP, 9990f
|
||||
disable_dbg
|
||||
mrs \tmp, mdscr_el1
|
||||
orr \tmp, \tmp, #1
|
||||
orr \tmp, \tmp, #DBG_MDSCR_SS
|
||||
msr mdscr_el1, \tmp
|
||||
9990:
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Enable both debug exceptions and interrupts. This is likely to be
|
||||
* faster than two daifclr operations, since writes to this register
|
||||
* are self-synchronising.
|
||||
*/
|
||||
.macro enable_dbg_and_irq
|
||||
msr daifclr, #(8 | 2)
|
||||
.endm
|
||||
|
||||
/*
|
||||
* SMP data memory barrier
|
||||
*/
|
||||
|
||||
@@ -31,6 +31,8 @@
|
||||
#define dmb(opt) asm volatile("dmb " #opt : : : "memory")
|
||||
#define dsb(opt) asm volatile("dsb " #opt : : : "memory")
|
||||
|
||||
#define psb_csync() asm volatile("hint #17" : : : "memory")
|
||||
|
||||
#define mb() dsb(sy)
|
||||
#define rmb() dsb(ld)
|
||||
#define wmb() dsb(st)
|
||||
|
||||
@@ -41,6 +41,7 @@ struct cpuinfo_arm64 {
|
||||
u64 reg_id_aa64mmfr2;
|
||||
u64 reg_id_aa64pfr0;
|
||||
u64 reg_id_aa64pfr1;
|
||||
u64 reg_id_aa64zfr0;
|
||||
|
||||
u32 reg_id_dfr0;
|
||||
u32 reg_id_isar0;
|
||||
@@ -59,6 +60,9 @@ struct cpuinfo_arm64 {
|
||||
u32 reg_mvfr0;
|
||||
u32 reg_mvfr1;
|
||||
u32 reg_mvfr2;
|
||||
|
||||
/* pseudo-ZCR for recording maximum ZCR_EL1 LEN value: */
|
||||
u64 reg_zcr;
|
||||
};
|
||||
|
||||
DECLARE_PER_CPU(struct cpuinfo_arm64, cpu_data);
|
||||
|
||||
@@ -40,7 +40,8 @@
|
||||
#define ARM64_WORKAROUND_858921 19
|
||||
#define ARM64_WORKAROUND_CAVIUM_30115 20
|
||||
#define ARM64_HAS_DCPOP 21
|
||||
#define ARM64_SVE 22
|
||||
|
||||
#define ARM64_NCAPS 22
|
||||
#define ARM64_NCAPS 23
|
||||
|
||||
#endif /* __ASM_CPUCAPS_H */
|
||||
|
||||
@@ -10,7 +10,9 @@
|
||||
#define __ASM_CPUFEATURE_H
|
||||
|
||||
#include <asm/cpucaps.h>
|
||||
#include <asm/fpsimd.h>
|
||||
#include <asm/hwcap.h>
|
||||
#include <asm/sigcontext.h>
|
||||
#include <asm/sysreg.h>
|
||||
|
||||
/*
|
||||
@@ -223,6 +225,13 @@ static inline bool id_aa64pfr0_32bit_el0(u64 pfr0)
|
||||
return val == ID_AA64PFR0_EL0_32BIT_64BIT;
|
||||
}
|
||||
|
||||
static inline bool id_aa64pfr0_sve(u64 pfr0)
|
||||
{
|
||||
u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_SVE_SHIFT);
|
||||
|
||||
return val > 0;
|
||||
}
|
||||
|
||||
void __init setup_cpu_features(void);
|
||||
|
||||
void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
|
||||
@@ -262,6 +271,39 @@ static inline bool system_uses_ttbr0_pan(void)
|
||||
!cpus_have_const_cap(ARM64_HAS_PAN);
|
||||
}
|
||||
|
||||
static inline bool system_supports_sve(void)
|
||||
{
|
||||
return IS_ENABLED(CONFIG_ARM64_SVE) &&
|
||||
cpus_have_const_cap(ARM64_SVE);
|
||||
}
|
||||
|
||||
/*
|
||||
* Read the pseudo-ZCR used by cpufeatures to identify the supported SVE
|
||||
* vector length.
|
||||
*
|
||||
* Use only if SVE is present.
|
||||
* This function clobbers the SVE vector length.
|
||||
*/
|
||||
static inline u64 read_zcr_features(void)
|
||||
{
|
||||
u64 zcr;
|
||||
unsigned int vq_max;
|
||||
|
||||
/*
|
||||
* Set the maximum possible VL, and write zeroes to all other
|
||||
* bits to see if they stick.
|
||||
*/
|
||||
sve_kernel_enable(NULL);
|
||||
write_sysreg_s(ZCR_ELx_LEN_MASK, SYS_ZCR_EL1);
|
||||
|
||||
zcr = read_sysreg_s(SYS_ZCR_EL1);
|
||||
zcr &= ~(u64)ZCR_ELx_LEN_MASK; /* find sticky 1s outside LEN field */
|
||||
vq_max = sve_vq_from_vl(sve_get_vl());
|
||||
zcr |= vq_max - 1; /* set LEN field to maximum effective value */
|
||||
|
||||
return zcr;
|
||||
}
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,72 @@
|
||||
/*
|
||||
* Copyright (C) 2017 ARM Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#ifndef __ASM_DAIFFLAGS_H
|
||||
#define __ASM_DAIFFLAGS_H
|
||||
|
||||
#include <linux/irqflags.h>
|
||||
|
||||
#define DAIF_PROCCTX 0
|
||||
#define DAIF_PROCCTX_NOIRQ PSR_I_BIT
|
||||
|
||||
/* mask/save/unmask/restore all exceptions, including interrupts. */
|
||||
static inline void local_daif_mask(void)
|
||||
{
|
||||
asm volatile(
|
||||
"msr daifset, #0xf // local_daif_mask\n"
|
||||
:
|
||||
:
|
||||
: "memory");
|
||||
trace_hardirqs_off();
|
||||
}
|
||||
|
||||
static inline unsigned long local_daif_save(void)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
asm volatile(
|
||||
"mrs %0, daif // local_daif_save\n"
|
||||
: "=r" (flags)
|
||||
:
|
||||
: "memory");
|
||||
local_daif_mask();
|
||||
|
||||
return flags;
|
||||
}
|
||||
|
||||
static inline void local_daif_unmask(void)
|
||||
{
|
||||
trace_hardirqs_on();
|
||||
asm volatile(
|
||||
"msr daifclr, #0xf // local_daif_unmask"
|
||||
:
|
||||
:
|
||||
: "memory");
|
||||
}
|
||||
|
||||
static inline void local_daif_restore(unsigned long flags)
|
||||
{
|
||||
if (!arch_irqs_disabled_flags(flags))
|
||||
trace_hardirqs_on();
|
||||
asm volatile(
|
||||
"msr daif, %0 // local_daif_restore"
|
||||
:
|
||||
: "r" (flags)
|
||||
: "memory");
|
||||
if (arch_irqs_disabled_flags(flags))
|
||||
trace_hardirqs_off();
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -188,8 +188,8 @@ typedef compat_elf_greg_t compat_elf_gregset_t[COMPAT_ELF_NGREG];
|
||||
|
||||
#define compat_start_thread compat_start_thread
|
||||
/*
|
||||
* Unlike the native SET_PERSONALITY macro, the compat version inherits
|
||||
* READ_IMPLIES_EXEC across a fork() since this is the behaviour on
|
||||
* Unlike the native SET_PERSONALITY macro, the compat version maintains
|
||||
* READ_IMPLIES_EXEC across an execve() since this is the behaviour on
|
||||
* arch/arm/.
|
||||
*/
|
||||
#define COMPAT_SET_PERSONALITY(ex) \
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user